Commit | Line | Data |
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8593790d MG |
1 | /* |
2 | * TI DA830/OMAP L137 EVM board | |
3 | * | |
4 | * Author: Mark A. Greer <mgreer@mvista.com> | |
5 | * Derived from: arch/arm/mach-davinci/board-dm644x-evm.c | |
6 | * | |
7 | * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under | |
8 | * the terms of the GNU General Public License version 2. This program | |
9 | * is licensed "as is" without any warranty of any kind, whether express | |
10 | * or implied. | |
11 | */ | |
12 | #include <linux/kernel.h> | |
8593790d MG |
13 | #include <linux/init.h> |
14 | #include <linux/console.h> | |
0e9a3ddc | 15 | #include <linux/interrupt.h> |
13e1f044 | 16 | #include <linux/gpio.h> |
733975a3 | 17 | #include <linux/platform_device.h> |
8593790d | 18 | #include <linux/i2c.h> |
13e1f044 | 19 | #include <linux/i2c/pcf857x.h> |
8593790d | 20 | #include <linux/i2c/at24.h> |
733975a3 DG |
21 | #include <linux/mtd/mtd.h> |
22 | #include <linux/mtd/partitions.h> | |
8593790d MG |
23 | |
24 | #include <asm/mach-types.h> | |
25 | #include <asm/mach/arch.h> | |
26 | ||
8593790d | 27 | #include <mach/cp_intc.h> |
32bf078c | 28 | #include <mach/mux.h> |
733975a3 | 29 | #include <mach/nand.h> |
8593790d | 30 | #include <mach/da8xx.h> |
0e9a3ddc | 31 | #include <mach/usb.h> |
8593790d MG |
32 | |
33 | #define DA830_EVM_PHY_MASK 0x0 | |
34 | #define DA830_EVM_MDIO_FREQUENCY 2200000 /* PHY bus frequency */ | |
35 | ||
733975a3 DG |
36 | #define DA830_EMIF25_ASYNC_DATA_CE3_BASE 0x62000000 |
37 | #define DA830_EMIF25_CONTROL_BASE 0x68000000 | |
38 | ||
0e9a3ddc SS |
39 | /* |
40 | * USB1 VBUS is controlled by GPIO1[15], over-current is reported on GPIO2[4]. | |
41 | */ | |
42 | #define ON_BD_USB_DRV GPIO_TO_PIN(1, 15) | |
43 | #define ON_BD_USB_OVC GPIO_TO_PIN(2, 4) | |
44 | ||
45 | static const short da830_evm_usb11_pins[] = { | |
46 | DA830_GPIO1_15, DA830_GPIO2_4, | |
47 | -1 | |
48 | }; | |
49 | ||
50 | static da8xx_ocic_handler_t da830_evm_usb_ocic_handler; | |
51 | ||
52 | static int da830_evm_usb_set_power(unsigned port, int on) | |
53 | { | |
54 | gpio_set_value(ON_BD_USB_DRV, on); | |
55 | return 0; | |
56 | } | |
57 | ||
58 | static int da830_evm_usb_get_power(unsigned port) | |
59 | { | |
60 | return gpio_get_value(ON_BD_USB_DRV); | |
61 | } | |
62 | ||
63 | static int da830_evm_usb_get_oci(unsigned port) | |
64 | { | |
65 | return !gpio_get_value(ON_BD_USB_OVC); | |
66 | } | |
67 | ||
68 | static irqreturn_t da830_evm_usb_ocic_irq(int, void *); | |
69 | ||
70 | static int da830_evm_usb_ocic_notify(da8xx_ocic_handler_t handler) | |
71 | { | |
72 | int irq = gpio_to_irq(ON_BD_USB_OVC); | |
73 | int error = 0; | |
74 | ||
75 | if (handler != NULL) { | |
76 | da830_evm_usb_ocic_handler = handler; | |
77 | ||
78 | error = request_irq(irq, da830_evm_usb_ocic_irq, IRQF_DISABLED | | |
79 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, | |
80 | "OHCI over-current indicator", NULL); | |
81 | if (error) | |
82 | printk(KERN_ERR "%s: could not request IRQ to watch " | |
83 | "over-current indicator changes\n", __func__); | |
84 | } else | |
85 | free_irq(irq, NULL); | |
86 | ||
87 | return error; | |
88 | } | |
89 | ||
90 | static struct da8xx_ohci_root_hub da830_evm_usb11_pdata = { | |
91 | .set_power = da830_evm_usb_set_power, | |
92 | .get_power = da830_evm_usb_get_power, | |
93 | .get_oci = da830_evm_usb_get_oci, | |
94 | .ocic_notify = da830_evm_usb_ocic_notify, | |
95 | ||
96 | /* TPS2065 switch @ 5V */ | |
97 | .potpgt = (3 + 1) / 2, /* 3 ms max */ | |
98 | }; | |
99 | ||
100 | static irqreturn_t da830_evm_usb_ocic_irq(int irq, void *dev_id) | |
101 | { | |
102 | da830_evm_usb_ocic_handler(&da830_evm_usb11_pdata, 1); | |
103 | return IRQ_HANDLED; | |
104 | } | |
105 | ||
106 | static __init void da830_evm_usb_init(void) | |
107 | { | |
108 | u32 cfgchip2; | |
109 | int ret; | |
110 | ||
111 | /* | |
112 | * Set up USB clock/mode in the CFGCHIP2 register. | |
113 | * FYI: CFGCHIP2 is 0x0000ef00 initially. | |
114 | */ | |
115 | cfgchip2 = __raw_readl(DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP2_REG)); | |
116 | ||
117 | /* USB2.0 PHY reference clock is 24 MHz */ | |
118 | cfgchip2 &= ~CFGCHIP2_REFFREQ; | |
119 | cfgchip2 |= CFGCHIP2_REFFREQ_24MHZ; | |
120 | ||
121 | /* | |
122 | * Select internal reference clock for USB 2.0 PHY | |
123 | * and use it as a clock source for USB 1.1 PHY | |
124 | * (this is the default setting anyway). | |
125 | */ | |
126 | cfgchip2 &= ~CFGCHIP2_USB1PHYCLKMUX; | |
127 | cfgchip2 |= CFGCHIP2_USB2PHYCLKMUX; | |
128 | ||
ca6a272a SS |
129 | /* |
130 | * We have to override VBUS/ID signals when MUSB is configured into the | |
131 | * host-only mode -- ID pin will float if no cable is connected, so the | |
132 | * controller won't be able to drive VBUS thinking that it's a B-device. | |
133 | * Otherwise, we want to use the OTG mode and enable VBUS comparators. | |
134 | */ | |
135 | cfgchip2 &= ~CFGCHIP2_OTGMODE; | |
136 | #ifdef CONFIG_USB_MUSB_HOST | |
137 | cfgchip2 |= CFGCHIP2_FORCE_HOST; | |
138 | #else | |
139 | cfgchip2 |= CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN; | |
140 | #endif | |
141 | ||
0e9a3ddc SS |
142 | __raw_writel(cfgchip2, DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP2_REG)); |
143 | ||
ca6a272a SS |
144 | /* USB_REFCLKIN is not used. */ |
145 | ret = davinci_cfg_reg(DA830_USB0_DRVVBUS); | |
146 | if (ret) | |
147 | pr_warning("%s: USB 2.0 PinMux setup failed: %d\n", | |
148 | __func__, ret); | |
149 | else { | |
150 | /* | |
151 | * TPS2065 switch @ 5V supplies 1 A (sustains 1.5 A), | |
152 | * with the power on to power good time of 3 ms. | |
153 | */ | |
154 | ret = da8xx_register_usb20(1000, 3); | |
155 | if (ret) | |
156 | pr_warning("%s: USB 2.0 registration failed: %d\n", | |
157 | __func__, ret); | |
158 | } | |
159 | ||
0e9a3ddc SS |
160 | ret = da8xx_pinmux_setup(da830_evm_usb11_pins); |
161 | if (ret) { | |
162 | pr_warning("%s: USB 1.1 PinMux setup failed: %d\n", | |
163 | __func__, ret); | |
164 | return; | |
165 | } | |
166 | ||
167 | ret = gpio_request(ON_BD_USB_DRV, "ON_BD_USB_DRV"); | |
168 | if (ret) { | |
169 | printk(KERN_ERR "%s: failed to request GPIO for USB 1.1 port " | |
170 | "power control: %d\n", __func__, ret); | |
171 | return; | |
172 | } | |
173 | gpio_direction_output(ON_BD_USB_DRV, 0); | |
174 | ||
175 | ret = gpio_request(ON_BD_USB_OVC, "ON_BD_USB_OVC"); | |
176 | if (ret) { | |
177 | printk(KERN_ERR "%s: failed to request GPIO for USB 1.1 port " | |
178 | "over-current indicator: %d\n", __func__, ret); | |
179 | return; | |
180 | } | |
181 | gpio_direction_input(ON_BD_USB_OVC); | |
182 | ||
183 | ret = da8xx_register_usb11(&da830_evm_usb11_pdata); | |
184 | if (ret) | |
185 | pr_warning("%s: USB 1.1 registration failed: %d\n", | |
186 | __func__, ret); | |
187 | } | |
188 | ||
8593790d MG |
189 | static struct davinci_uart_config da830_evm_uart_config __initdata = { |
190 | .enabled_uarts = 0x7, | |
191 | }; | |
192 | ||
32bf078c MG |
193 | static const short da830_evm_mcasp1_pins[] = { |
194 | DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1, DA830_AHCLKR1, DA830_AFSR1, | |
195 | DA830_AMUTE1, DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_5, | |
196 | DA830_ACLKR1, DA830_AXR1_6, DA830_AXR1_7, DA830_AXR1_8, DA830_AXR1_10, | |
197 | DA830_AXR1_11, | |
198 | -1 | |
199 | }; | |
200 | ||
e33ef5e3 C |
201 | static u8 da830_iis_serializer_direction[] = { |
202 | RX_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, | |
203 | INACTIVE_MODE, TX_MODE, INACTIVE_MODE, INACTIVE_MODE, | |
204 | INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, | |
205 | }; | |
206 | ||
207 | static struct snd_platform_data da830_evm_snd_data = { | |
208 | .tx_dma_offset = 0x2000, | |
209 | .rx_dma_offset = 0x2000, | |
210 | .op_mode = DAVINCI_MCASP_IIS_MODE, | |
211 | .num_serializer = ARRAY_SIZE(da830_iis_serializer_direction), | |
212 | .tdm_slots = 2, | |
213 | .serial_dir = da830_iis_serializer_direction, | |
214 | .eventq_no = EVENTQ_0, | |
215 | .version = MCASP_VERSION_2, | |
216 | .txnumevt = 1, | |
217 | .rxnumevt = 1, | |
218 | }; | |
219 | ||
2eb30c81 DG |
220 | /* |
221 | * GPIO2[1] is used as MMC_SD_WP and GPIO2[2] as MMC_SD_INS. | |
222 | */ | |
223 | static const short da830_evm_mmc_sd_pins[] = { | |
224 | DA830_MMCSD_DAT_0, DA830_MMCSD_DAT_1, DA830_MMCSD_DAT_2, | |
225 | DA830_MMCSD_DAT_3, DA830_MMCSD_DAT_4, DA830_MMCSD_DAT_5, | |
226 | DA830_MMCSD_DAT_6, DA830_MMCSD_DAT_7, DA830_MMCSD_CLK, | |
227 | DA830_MMCSD_CMD, DA830_GPIO2_1, DA830_GPIO2_2, | |
228 | -1 | |
229 | }; | |
230 | ||
231 | #define DA830_MMCSD_WP_PIN GPIO_TO_PIN(2, 1) | |
232 | ||
233 | static int da830_evm_mmc_get_ro(int index) | |
234 | { | |
235 | return gpio_get_value(DA830_MMCSD_WP_PIN); | |
236 | } | |
237 | ||
238 | static struct davinci_mmc_config da830_evm_mmc_config = { | |
239 | .get_ro = da830_evm_mmc_get_ro, | |
240 | .wires = 4, | |
241 | .version = MMC_CTLR_VERSION_2, | |
242 | }; | |
243 | ||
244 | static inline void da830_evm_init_mmc(void) | |
245 | { | |
246 | int ret; | |
247 | ||
248 | ret = da8xx_pinmux_setup(da830_evm_mmc_sd_pins); | |
249 | if (ret) { | |
250 | pr_warning("da830_evm_init: mmc/sd mux setup failed: %d\n", | |
251 | ret); | |
252 | return; | |
253 | } | |
254 | ||
255 | ret = gpio_request(DA830_MMCSD_WP_PIN, "MMC WP"); | |
256 | if (ret) { | |
257 | pr_warning("da830_evm_init: can not open GPIO %d\n", | |
258 | DA830_MMCSD_WP_PIN); | |
259 | return; | |
260 | } | |
261 | gpio_direction_input(DA830_MMCSD_WP_PIN); | |
262 | ||
263 | ret = da8xx_register_mmcsd0(&da830_evm_mmc_config); | |
264 | if (ret) { | |
265 | pr_warning("da830_evm_init: mmc/sd registration failed: %d\n", | |
266 | ret); | |
267 | gpio_free(DA830_MMCSD_WP_PIN); | |
268 | } | |
269 | } | |
270 | ||
a0433ac3 SN |
271 | /* |
272 | * UI board NAND/NOR flashes only use 8-bit data bus. | |
273 | */ | |
274 | static const short da830_evm_emif25_pins[] = { | |
275 | DA830_EMA_D_0, DA830_EMA_D_1, DA830_EMA_D_2, DA830_EMA_D_3, | |
276 | DA830_EMA_D_4, DA830_EMA_D_5, DA830_EMA_D_6, DA830_EMA_D_7, | |
277 | DA830_EMA_A_0, DA830_EMA_A_1, DA830_EMA_A_2, DA830_EMA_A_3, | |
278 | DA830_EMA_A_4, DA830_EMA_A_5, DA830_EMA_A_6, DA830_EMA_A_7, | |
279 | DA830_EMA_A_8, DA830_EMA_A_9, DA830_EMA_A_10, DA830_EMA_A_11, | |
280 | DA830_EMA_A_12, DA830_EMA_BA_0, DA830_EMA_BA_1, DA830_NEMA_WE, | |
281 | DA830_NEMA_CS_2, DA830_NEMA_CS_3, DA830_NEMA_OE, DA830_EMA_WAIT_0, | |
282 | -1 | |
283 | }; | |
284 | ||
b5ebe4e1 SN |
285 | #if defined(CONFIG_MMC_DAVINCI) || defined(CONFIG_MMC_DAVINCI_MODULE) |
286 | #define HAS_MMC 1 | |
287 | #else | |
288 | #define HAS_MMC 0 | |
289 | #endif | |
290 | ||
733975a3 DG |
291 | #ifdef CONFIG_DA830_UI_NAND |
292 | static struct mtd_partition da830_evm_nand_partitions[] = { | |
293 | /* bootloader (U-Boot, etc) in first sector */ | |
294 | [0] = { | |
295 | .name = "bootloader", | |
296 | .offset = 0, | |
297 | .size = SZ_128K, | |
298 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | |
299 | }, | |
300 | /* bootloader params in the next sector */ | |
301 | [1] = { | |
302 | .name = "params", | |
303 | .offset = MTDPART_OFS_APPEND, | |
304 | .size = SZ_128K, | |
305 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | |
306 | }, | |
307 | /* kernel */ | |
308 | [2] = { | |
309 | .name = "kernel", | |
310 | .offset = MTDPART_OFS_APPEND, | |
311 | .size = SZ_2M, | |
312 | .mask_flags = 0, | |
313 | }, | |
314 | /* file system */ | |
315 | [3] = { | |
316 | .name = "filesystem", | |
317 | .offset = MTDPART_OFS_APPEND, | |
318 | .size = MTDPART_SIZ_FULL, | |
319 | .mask_flags = 0, | |
320 | } | |
321 | }; | |
322 | ||
323 | /* flash bbt decriptors */ | |
324 | static uint8_t da830_evm_nand_bbt_pattern[] = { 'B', 'b', 't', '0' }; | |
325 | static uint8_t da830_evm_nand_mirror_pattern[] = { '1', 't', 'b', 'B' }; | |
326 | ||
327 | static struct nand_bbt_descr da830_evm_nand_bbt_main_descr = { | |
328 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | | |
329 | NAND_BBT_WRITE | NAND_BBT_2BIT | | |
330 | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
331 | .offs = 2, | |
332 | .len = 4, | |
333 | .veroffs = 16, | |
334 | .maxblocks = 4, | |
335 | .pattern = da830_evm_nand_bbt_pattern | |
336 | }; | |
337 | ||
338 | static struct nand_bbt_descr da830_evm_nand_bbt_mirror_descr = { | |
339 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | | |
340 | NAND_BBT_WRITE | NAND_BBT_2BIT | | |
341 | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
342 | .offs = 2, | |
343 | .len = 4, | |
344 | .veroffs = 16, | |
345 | .maxblocks = 4, | |
346 | .pattern = da830_evm_nand_mirror_pattern | |
347 | }; | |
348 | ||
349 | static struct davinci_nand_pdata da830_evm_nand_pdata = { | |
350 | .parts = da830_evm_nand_partitions, | |
351 | .nr_parts = ARRAY_SIZE(da830_evm_nand_partitions), | |
352 | .ecc_mode = NAND_ECC_HW, | |
353 | .ecc_bits = 4, | |
354 | .options = NAND_USE_FLASH_BBT, | |
355 | .bbt_td = &da830_evm_nand_bbt_main_descr, | |
356 | .bbt_md = &da830_evm_nand_bbt_mirror_descr, | |
357 | }; | |
358 | ||
359 | static struct resource da830_evm_nand_resources[] = { | |
360 | [0] = { /* First memory resource is NAND I/O window */ | |
361 | .start = DA830_EMIF25_ASYNC_DATA_CE3_BASE, | |
362 | .end = DA830_EMIF25_ASYNC_DATA_CE3_BASE + PAGE_SIZE - 1, | |
363 | .flags = IORESOURCE_MEM, | |
364 | }, | |
365 | [1] = { /* Second memory resource is AEMIF control registers */ | |
366 | .start = DA830_EMIF25_CONTROL_BASE, | |
367 | .end = DA830_EMIF25_CONTROL_BASE + SZ_32K - 1, | |
368 | .flags = IORESOURCE_MEM, | |
369 | }, | |
370 | }; | |
371 | ||
372 | static struct platform_device da830_evm_nand_device = { | |
373 | .name = "davinci_nand", | |
374 | .id = 1, | |
375 | .dev = { | |
376 | .platform_data = &da830_evm_nand_pdata, | |
377 | }, | |
378 | .num_resources = ARRAY_SIZE(da830_evm_nand_resources), | |
379 | .resource = da830_evm_nand_resources, | |
380 | }; | |
a0433ac3 | 381 | |
77316f05 | 382 | static inline void da830_evm_init_nand(int mux_mode) |
a0433ac3 SN |
383 | { |
384 | int ret; | |
385 | ||
b5ebe4e1 SN |
386 | if (HAS_MMC) { |
387 | pr_warning("WARNING: both MMC/SD and NAND are " | |
388 | "enabled, but they share AEMIF pins.\n" | |
389 | "\tDisable MMC/SD for NAND support.\n"); | |
390 | return; | |
391 | } | |
392 | ||
a0433ac3 SN |
393 | ret = da8xx_pinmux_setup(da830_evm_emif25_pins); |
394 | if (ret) | |
395 | pr_warning("da830_evm_init: emif25 mux setup failed: %d\n", | |
396 | ret); | |
397 | ||
398 | ret = platform_device_register(&da830_evm_nand_device); | |
399 | if (ret) | |
400 | pr_warning("da830_evm_init: NAND device not registered.\n"); | |
77316f05 SN |
401 | |
402 | gpio_direction_output(mux_mode, 1); | |
a0433ac3 SN |
403 | } |
404 | #else | |
77316f05 | 405 | static inline void da830_evm_init_nand(int mux_mode) { } |
733975a3 DG |
406 | #endif |
407 | ||
a0433ac3 | 408 | #ifdef CONFIG_DA830_UI_LCD |
77316f05 | 409 | static inline void da830_evm_init_lcdc(int mux_mode) |
a0433ac3 SN |
410 | { |
411 | int ret; | |
412 | ||
413 | ret = da8xx_pinmux_setup(da830_lcdcntl_pins); | |
414 | if (ret) | |
415 | pr_warning("da830_evm_init: lcdcntl mux setup failed: %d\n", | |
416 | ret); | |
417 | ||
418 | ret = da8xx_register_lcdc(&sharp_lcd035q3dg01_pdata); | |
419 | if (ret) | |
420 | pr_warning("da830_evm_init: lcd setup failed: %d\n", ret); | |
77316f05 SN |
421 | |
422 | gpio_direction_output(mux_mode, 0); | |
a0433ac3 SN |
423 | } |
424 | #else | |
77316f05 | 425 | static inline void da830_evm_init_lcdc(int mux_mode) { } |
a0433ac3 | 426 | #endif |
733975a3 | 427 | |
77316f05 SN |
428 | static struct at24_platform_data da830_evm_i2c_eeprom_info = { |
429 | .byte_len = SZ_256K / 8, | |
430 | .page_size = 64, | |
431 | .flags = AT24_FLAG_ADDR16, | |
432 | .setup = davinci_get_mac_addr, | |
433 | .context = (void *)0x7f00, | |
434 | }; | |
435 | ||
436 | static int da830_evm_ui_expander_setup(struct i2c_client *client, int gpio, | |
437 | unsigned ngpio, void *context) | |
438 | { | |
439 | gpio_request(gpio + 6, "UI MUX_MODE"); | |
440 | ||
b5ebe4e1 SN |
441 | /* Drive mux mode low to match the default without UI card */ |
442 | gpio_direction_output(gpio + 6, 0); | |
443 | ||
77316f05 SN |
444 | da830_evm_init_lcdc(gpio + 6); |
445 | ||
446 | da830_evm_init_nand(gpio + 6); | |
447 | ||
448 | return 0; | |
449 | } | |
450 | ||
451 | static int da830_evm_ui_expander_teardown(struct i2c_client *client, int gpio, | |
452 | unsigned ngpio, void *context) | |
453 | { | |
454 | gpio_free(gpio + 6); | |
455 | return 0; | |
456 | } | |
457 | ||
458 | static struct pcf857x_platform_data da830_evm_ui_expander_info = { | |
459 | .gpio_base = DAVINCI_N_GPIO, | |
460 | .setup = da830_evm_ui_expander_setup, | |
461 | .teardown = da830_evm_ui_expander_teardown, | |
462 | }; | |
463 | ||
464 | static struct i2c_board_info __initdata da830_evm_i2c_devices[] = { | |
465 | { | |
466 | I2C_BOARD_INFO("24c256", 0x50), | |
467 | .platform_data = &da830_evm_i2c_eeprom_info, | |
468 | }, | |
469 | { | |
470 | I2C_BOARD_INFO("tlv320aic3x", 0x18), | |
471 | }, | |
472 | { | |
473 | I2C_BOARD_INFO("pcf8574", 0x3f), | |
474 | .platform_data = &da830_evm_ui_expander_info, | |
475 | }, | |
476 | }; | |
477 | ||
478 | static struct davinci_i2c_platform_data da830_evm_i2c_0_pdata = { | |
479 | .bus_freq = 100, /* kHz */ | |
480 | .bus_delay = 0, /* usec */ | |
481 | }; | |
482 | ||
8593790d MG |
483 | static __init void da830_evm_init(void) |
484 | { | |
485 | struct davinci_soc_info *soc_info = &davinci_soc_info; | |
486 | int ret; | |
487 | ||
488 | ret = da8xx_register_edma(); | |
489 | if (ret) | |
490 | pr_warning("da830_evm_init: edma registration failed: %d\n", | |
491 | ret); | |
492 | ||
c96b56c5 | 493 | ret = da8xx_pinmux_setup(da830_i2c0_pins); |
8593790d MG |
494 | if (ret) |
495 | pr_warning("da830_evm_init: i2c0 mux setup failed: %d\n", | |
496 | ret); | |
497 | ||
498 | ret = da8xx_register_i2c(0, &da830_evm_i2c_0_pdata); | |
499 | if (ret) | |
500 | pr_warning("da830_evm_init: i2c0 registration failed: %d\n", | |
501 | ret); | |
502 | ||
0e9a3ddc SS |
503 | da830_evm_usb_init(); |
504 | ||
8593790d MG |
505 | soc_info->emac_pdata->phy_mask = DA830_EVM_PHY_MASK; |
506 | soc_info->emac_pdata->mdio_max_freq = DA830_EVM_MDIO_FREQUENCY; | |
507 | soc_info->emac_pdata->rmii_en = 1; | |
508 | ||
c96b56c5 | 509 | ret = da8xx_pinmux_setup(da830_cpgmac_pins); |
8593790d MG |
510 | if (ret) |
511 | pr_warning("da830_evm_init: cpgmac mux setup failed: %d\n", | |
512 | ret); | |
513 | ||
514 | ret = da8xx_register_emac(); | |
515 | if (ret) | |
516 | pr_warning("da830_evm_init: emac registration failed: %d\n", | |
517 | ret); | |
518 | ||
519 | ret = da8xx_register_watchdog(); | |
520 | if (ret) | |
521 | pr_warning("da830_evm_init: watchdog registration failed: %d\n", | |
522 | ret); | |
523 | ||
524 | davinci_serial_init(&da830_evm_uart_config); | |
525 | i2c_register_board_info(1, da830_evm_i2c_devices, | |
526 | ARRAY_SIZE(da830_evm_i2c_devices)); | |
e33ef5e3 | 527 | |
32bf078c | 528 | ret = da8xx_pinmux_setup(da830_evm_mcasp1_pins); |
e33ef5e3 C |
529 | if (ret) |
530 | pr_warning("da830_evm_init: mcasp1 mux setup failed: %d\n", | |
531 | ret); | |
532 | ||
b8864aa4 | 533 | da8xx_register_mcasp(1, &da830_evm_snd_data); |
2eb30c81 DG |
534 | |
535 | da830_evm_init_mmc(); | |
13e1f044 | 536 | |
c51df70b MG |
537 | ret = da8xx_register_rtc(); |
538 | if (ret) | |
539 | pr_warning("da830_evm_init: rtc setup failed: %d\n", ret); | |
8593790d MG |
540 | } |
541 | ||
542 | #ifdef CONFIG_SERIAL_8250_CONSOLE | |
543 | static int __init da830_evm_console_init(void) | |
544 | { | |
545 | return add_preferred_console("ttyS", 2, "115200"); | |
546 | } | |
547 | console_initcall(da830_evm_console_init); | |
548 | #endif | |
549 | ||
550 | static __init void da830_evm_irq_init(void) | |
551 | { | |
552 | struct davinci_soc_info *soc_info = &davinci_soc_info; | |
553 | ||
554 | cp_intc_init((void __iomem *)DA8XX_CP_INTC_VIRT, DA830_N_CP_INTC_IRQ, | |
555 | soc_info->intc_irq_prios); | |
556 | } | |
557 | ||
558 | static void __init da830_evm_map_io(void) | |
559 | { | |
560 | da830_init(); | |
561 | } | |
562 | ||
6af6564d | 563 | MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137 EVM") |
8593790d MG |
564 | .phys_io = IO_PHYS, |
565 | .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, | |
566 | .boot_params = (DA8XX_DDR_BASE + 0x100), | |
567 | .map_io = da830_evm_map_io, | |
568 | .init_irq = da830_evm_irq_init, | |
569 | .timer = &davinci_timer, | |
570 | .init_machine = da830_evm_init, | |
571 | MACHINE_END |