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misc: (at24) move header to linux/platform_data/
[deliverable/linux.git] / arch / arm / mach-davinci / board-da850-evm.c
CommitLineData
0fbc5592
SR		 1/*
2 * TI DA850/OMAP-L138 EVM board
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Derived from: arch/arm/mach-davinci/board-da830-evm.c
7 * Original Copyrights follow:
8 *
9 * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
0fbc5592 14#include <linux/console.h>
6809084a
MP		 15#include <linux/delay.h>
16#include <linux/gpio.h>
17#include <linux/gpio_keys.h>
18#include <linux/init.h>
19#include <linux/kernel.h>
0fbc5592 20#include <linux/i2c.h>
25f73ed5 21#include <linux/platform_data/at24.h>
5877457a 22#include <linux/platform_data/pca953x.h>
75929f5e 23#include <linux/input.h>
6809084a 24#include <linux/input/tps6507x-ts.h>
0bc20bba 25#include <linux/mfd/tps6507x.h>
38beb929
SR		 26#include <linux/mtd/mtd.h>
27#include <linux/mtd/nand.h>
28#include <linux/mtd/partitions.h>
7c5ec609 29#include <linux/mtd/physmap.h>
6809084a
MP		 30#include <linux/platform_device.h>
31#include <linux/platform_data/mtd-davinci.h>
32#include <linux/platform_data/mtd-davinci-aemif.h>
33#include <linux/platform_data/spi-davinci.h>
ae41d17a 34#include <linux/platform_data/uio_pruss.h>
a9eb1f67 35#include <linux/regulator/machine.h>
8b24599e 36#include <linux/regulator/tps6507x.h>
fdce5568
SN		 37#include <linux/spi/spi.h>
38#include <linux/spi/flash.h>
ab3f5c1f 39#include <linux/wl12xx.h>
0fbc5592 40
0fbc5592
SR		 41#include <mach/cp_intc.h>
42#include <mach/da8xx.h>
7761ef67 43#include <mach/mux.h>
6a2461a4 44#include <mach/sram.h>
6809084a
MP		 45
46#include <asm/mach-types.h>
47#include <asm/mach/arch.h>
48#include <asm/system_info.h>
0fbc5592 49
1e046d17 50#include <media/tvp514x.h>
2bd4e58c 51#include <media/adv7343.h>
1e046d17 52
f6f97588 53#define DA850_EVM_PHY_ID "davinci_mdio-0:00"
7761ef67 54#define DA850_LCD_PWR_PIN GPIO_TO_PIN(2, 8)
5cbdf276 55#define DA850_LCD_BL_PIN GPIO_TO_PIN(2, 15)
5cbdf276 56
700691f2
SR		 57#define DA850_MMCSD_CD_PIN GPIO_TO_PIN(4, 0)
58#define DA850_MMCSD_WP_PIN GPIO_TO_PIN(4, 1)
59
ab3f5c1f
IY		 60#define DA850_WLAN_EN GPIO_TO_PIN(6, 9)
61#define DA850_WLAN_IRQ GPIO_TO_PIN(6, 10)
62
2206771c
C		 63#define DA850_MII_MDIO_CLKEN_PIN GPIO_TO_PIN(2, 6)
64
fdce5568
SN		 65static struct mtd_partition da850evm_spiflash_part[] = {
66 [0] = {
67 .name = "UBL",
68 .offset = 0,
69 .size = SZ_64K,
70 .mask_flags = MTD_WRITEABLE,
71 },
72 [1] = {
73 .name = "U-Boot",
74 .offset = MTDPART_OFS_APPEND,
75 .size = SZ_512K,
76 .mask_flags = MTD_WRITEABLE,
77 },
78 [2] = {
79 .name = "U-Boot-Env",
80 .offset = MTDPART_OFS_APPEND,
81 .size = SZ_64K,
82 .mask_flags = MTD_WRITEABLE,
83 },
84 [3] = {
85 .name = "Kernel",
86 .offset = MTDPART_OFS_APPEND,
87 .size = SZ_2M + SZ_512K,
88 .mask_flags = 0,
89 },
90 [4] = {
91 .name = "Filesystem",
92 .offset = MTDPART_OFS_APPEND,
93 .size = SZ_4M,
94 .mask_flags = 0,
95 },
96 [5] = {
97 .name = "MAC-Address",
98 .offset = SZ_8M - SZ_64K,
99 .size = SZ_64K,
100 .mask_flags = MTD_WRITEABLE,
101 },
102};
103
104static struct flash_platform_data da850evm_spiflash_data = {
105 .name = "m25p80",
106 .parts = da850evm_spiflash_part,
107 .nr_parts = ARRAY_SIZE(da850evm_spiflash_part),
108 .type = "m25p64",
109};
110
111static struct davinci_spi_config da850evm_spiflash_cfg = {
112 .io_type = SPI_IO_TYPE_DMA,
113 .c2tdelay = 8,
114 .t2cdelay = 8,
115};
116
117static struct spi_board_info da850evm_spi_info[] = {
118 {
119 .modalias = "m25p80",
120 .platform_data = &da850evm_spiflash_data,
121 .controller_data = &da850evm_spiflash_cfg,
122 .mode = SPI_MODE_0,
123 .max_speed_hz = 30000000,
124 .bus_num = 1,
125 .chip_select = 0,
126 },
127};
128
810198bc
RS		 129#ifdef CONFIG_MTD
130static void da850_evm_m25p80_notify_add(struct mtd_info *mtd)
131{
132 char *mac_addr = davinci_soc_info.emac_pdata->mac_addr;
133 size_t retlen;
134
135 if (!strcmp(mtd->name, "MAC-Address")) {
329ad399 136 mtd_read(mtd, 0, ETH_ALEN, &retlen, mac_addr);
810198bc
RS		 137 if (retlen == ETH_ALEN)
138 pr_info("Read MAC addr from SPI Flash: %pM\n",
139 mac_addr);
140 }
141}
142
143static struct mtd_notifier da850evm_spi_notifier = {
144 .add = da850_evm_m25p80_notify_add,
145};
146
147static void da850_evm_setup_mac_addr(void)
148{
149 register_mtd_user(&da850evm_spi_notifier);
150}
151#else
152static void da850_evm_setup_mac_addr(void) { }
153#endif
154
7c5ec609
SR		 155static struct mtd_partition da850_evm_norflash_partition[] = {
156 {
e2abd5a2 157 .name = "bootloaders + env",
7c5ec609 158 .offset = 0,
e2abd5a2
SR		 159 .size = SZ_512K,
160 .mask_flags = MTD_WRITEABLE,
161 },
162 {
163 .name = "kernel",
164 .offset = MTDPART_OFS_APPEND,
165 .size = SZ_2M,
166 .mask_flags = 0,
167 },
168 {
169 .name = "filesystem",
170 .offset = MTDPART_OFS_APPEND,
7c5ec609
SR		 171 .size = MTDPART_SIZ_FULL,
172 .mask_flags = 0,
173 },
174};
175
176static struct physmap_flash_data da850_evm_norflash_data = {
177 .width = 2,
178 .parts = da850_evm_norflash_partition,
179 .nr_parts = ARRAY_SIZE(da850_evm_norflash_partition),
180};
181
182static struct resource da850_evm_norflash_resource[] = {
183 {
184 .start = DA8XX_AEMIF_CS2_BASE,
185 .end = DA8XX_AEMIF_CS2_BASE + SZ_32M - 1,
186 .flags = IORESOURCE_MEM,
187 },
188};
189
190static struct platform_device da850_evm_norflash_device = {
191 .name = "physmap-flash",
192 .id = 0,
193 .dev = {
194 .platform_data = &da850_evm_norflash_data,
195 },
196 .num_resources = 1,
197 .resource = da850_evm_norflash_resource,
198};
199
63534443
SN		 200static struct davinci_pm_config da850_pm_pdata = {
201 .sleepcount = 128,
202};
203
204static struct platform_device da850_pm_device = {
205 .name = "pm-davinci",
206 .dev = {
207 .platform_data = &da850_pm_pdata,
208 },
209 .id = -1,
210};
211
38beb929
SR		 212/* DA850/OMAP-L138 EVM includes a 512 MByte large-page NAND flash
213 * (128K blocks). It may be used instead of the (default) SPI flash
214 * to boot, using TI's tools to install the secondary boot loader
215 * (UBL) and U-Boot.
216 */
db549d22 217static struct mtd_partition da850_evm_nandflash_partition[] = {
38beb929
SR		 218 {
219 .name = "u-boot env",
220 .offset = 0,
221 .size = SZ_128K,
222 .mask_flags = MTD_WRITEABLE,
223 },
224 {
225 .name = "UBL",
226 .offset = MTDPART_OFS_APPEND,
227 .size = SZ_128K,
228 .mask_flags = MTD_WRITEABLE,
229 },
230 {
231 .name = "u-boot",
232 .offset = MTDPART_OFS_APPEND,
233 .size = 4 * SZ_128K,
234 .mask_flags = MTD_WRITEABLE,
235 },
236 {
237 .name = "kernel",
238 .offset = 0x200000,
239 .size = SZ_2M,
240 .mask_flags = 0,
241 },
242 {
243 .name = "filesystem",
244 .offset = MTDPART_OFS_APPEND,
245 .size = MTDPART_SIZ_FULL,
246 .mask_flags = 0,
247 },
248};
249
18a8505c
SN		 250static struct davinci_aemif_timing da850_evm_nandflash_timing = {
251 .wsetup = 24,
252 .wstrobe = 21,
253 .whold = 14,
254 .rsetup = 19,
255 .rstrobe = 50,
256 .rhold = 0,
257 .ta = 20,
258};
259
38beb929
SR		 260static struct davinci_nand_pdata da850_evm_nandflash_data = {
261 .parts = da850_evm_nandflash_partition,
262 .nr_parts = ARRAY_SIZE(da850_evm_nandflash_partition),
263 .ecc_mode = NAND_ECC_HW,
fc42e335 264 .ecc_bits = 4,
bb9ebd4e 265 .bbt_options = NAND_BBT_USE_FLASH,
18a8505c 266 .timing = &da850_evm_nandflash_timing,
38beb929
SR		 267};
268
269static struct resource da850_evm_nandflash_resource[] = {
270 {
271 .start = DA8XX_AEMIF_CS3_BASE,
272 .end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
273 .flags = IORESOURCE_MEM,
274 },
275 {
276 .start = DA8XX_AEMIF_CTL_BASE,
277 .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
278 .flags = IORESOURCE_MEM,
279 },
280};
281
282static struct platform_device da850_evm_nandflash_device = {
283 .name = "davinci_nand",
284 .id = 1,
285 .dev = {
286 .platform_data = &da850_evm_nandflash_data,
287 },
288 .num_resources = ARRAY_SIZE(da850_evm_nandflash_resource),
289 .resource = da850_evm_nandflash_resource,
290};
291
59858b71 292static struct platform_device *da850_evm_devices[] = {
039c5ee3
SR		 293 &da850_evm_nandflash_device,
294 &da850_evm_norflash_device,
295};
296
297#define DA8XX_AEMIF_CE2CFG_OFFSET 0x10
298#define DA8XX_AEMIF_ASIZE_16BIT 0x1
299
300static void __init da850_evm_init_nor(void)
301{
302 void __iomem *aemif_addr;
303
304 aemif_addr = ioremap(DA8XX_AEMIF_CTL_BASE, SZ_32K);
305
306 /* Configure data bus width of CS2 to 16 bit */
307 writel(readl(aemif_addr + DA8XX_AEMIF_CE2CFG_OFFSET) |
308 DA8XX_AEMIF_ASIZE_16BIT,
309 aemif_addr + DA8XX_AEMIF_CE2CFG_OFFSET);
310
311 iounmap(aemif_addr);
312}
313
f48ecc2f
SS		 314static const short da850_evm_nand_pins[] = {
315 DA850_EMA_D_0, DA850_EMA_D_1, DA850_EMA_D_2, DA850_EMA_D_3,
316 DA850_EMA_D_4, DA850_EMA_D_5, DA850_EMA_D_6, DA850_EMA_D_7,
317 DA850_EMA_A_1, DA850_EMA_A_2, DA850_NEMA_CS_3, DA850_NEMA_CS_4,
318 DA850_NEMA_WE, DA850_NEMA_OE,
319 -1
320};
321
322static const short da850_evm_nor_pins[] = {
323 DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2,
324 DA850_NEMA_WE, DA850_NEMA_OE, DA850_EMA_D_0, DA850_EMA_D_1,
325 DA850_EMA_D_2, DA850_EMA_D_3, DA850_EMA_D_4, DA850_EMA_D_5,
326 DA850_EMA_D_6, DA850_EMA_D_7, DA850_EMA_D_8, DA850_EMA_D_9,
327 DA850_EMA_D_10, DA850_EMA_D_11, DA850_EMA_D_12, DA850_EMA_D_13,
328 DA850_EMA_D_14, DA850_EMA_D_15, DA850_EMA_A_0, DA850_EMA_A_1,
329 DA850_EMA_A_2, DA850_EMA_A_3, DA850_EMA_A_4, DA850_EMA_A_5,
330 DA850_EMA_A_6, DA850_EMA_A_7, DA850_EMA_A_8, DA850_EMA_A_9,
331 DA850_EMA_A_10, DA850_EMA_A_11, DA850_EMA_A_12, DA850_EMA_A_13,
332 DA850_EMA_A_14, DA850_EMA_A_15, DA850_EMA_A_16, DA850_EMA_A_17,
333 DA850_EMA_A_18, DA850_EMA_A_19, DA850_EMA_A_20, DA850_EMA_A_21,
334 DA850_EMA_A_22, DA850_EMA_A_23,
335 -1
336};
337
a0a56db9 338#define HAS_MMC IS_ENABLED(CONFIG_MMC_DAVINCI)
039c5ee3 339
f48ecc2f 340static inline void da850_evm_setup_nor_nand(void)
039c5ee3
SR		 341{
342 int ret = 0;
343
b688c2fb 344 if (!HAS_MMC) {
f48ecc2f 345 ret = davinci_cfg_reg_list(da850_evm_nand_pins);
039c5ee3 346 if (ret)
6c7c23cc
RT		 347 pr_warn("%s: NAND mux setup failed: %d\n",
348 __func__, ret);
039c5ee3 349
f48ecc2f 350 ret = davinci_cfg_reg_list(da850_evm_nor_pins);
039c5ee3 351 if (ret)
6c7c23cc
RT		 352 pr_warn("%s: NOR mux setup failed: %d\n",
353 __func__, ret);
039c5ee3
SR		 354
355 da850_evm_init_nor();
356
357 platform_add_devices(da850_evm_devices,
358 ARRAY_SIZE(da850_evm_devices));
359 }
360}
75e2ea64 361
bae10587
SN		 362#ifdef CONFIG_DA850_UI_RMII
363static inline void da850_evm_setup_emac_rmii(int rmii_sel)
364{
365 struct davinci_soc_info *soc_info = &davinci_soc_info;
366
367 soc_info->emac_pdata->rmii_en = 1;
47e7cb14 368 gpio_set_value_cansleep(rmii_sel, 0);
bae10587
SN		 369}
370#else
371static inline void da850_evm_setup_emac_rmii(int rmii_sel) { }
372#endif
373
75929f5e
BG		 374
375#define DA850_KEYS_DEBOUNCE_MS 10
376/*
377 * At 200ms polling interval it is possible to miss an
378 * event by tapping very lightly on the push button but most
379 * pushes do result in an event; longer intervals require the
380 * user to hold the button whereas shorter intervals require
381 * more CPU time for polling.
382 */
383#define DA850_GPIO_KEYS_POLL_MS 200
384
385enum da850_evm_ui_exp_pins {
386 DA850_EVM_UI_EXP_SEL_C = 5,
387 DA850_EVM_UI_EXP_SEL_B,
388 DA850_EVM_UI_EXP_SEL_A,
389 DA850_EVM_UI_EXP_PB8,
390 DA850_EVM_UI_EXP_PB7,
391 DA850_EVM_UI_EXP_PB6,
392 DA850_EVM_UI_EXP_PB5,
393 DA850_EVM_UI_EXP_PB4,
394 DA850_EVM_UI_EXP_PB3,
395 DA850_EVM_UI_EXP_PB2,
396 DA850_EVM_UI_EXP_PB1,
397};
398
58b6c5a1 399static const char * const da850_evm_ui_exp[] = {
75929f5e
BG		 400 [DA850_EVM_UI_EXP_SEL_C] = "sel_c",
401 [DA850_EVM_UI_EXP_SEL_B] = "sel_b",
402 [DA850_EVM_UI_EXP_SEL_A] = "sel_a",
403 [DA850_EVM_UI_EXP_PB8] = "pb8",
404 [DA850_EVM_UI_EXP_PB7] = "pb7",
405 [DA850_EVM_UI_EXP_PB6] = "pb6",
406 [DA850_EVM_UI_EXP_PB5] = "pb5",
407 [DA850_EVM_UI_EXP_PB4] = "pb4",
408 [DA850_EVM_UI_EXP_PB3] = "pb3",
409 [DA850_EVM_UI_EXP_PB2] = "pb2",
410 [DA850_EVM_UI_EXP_PB1] = "pb1",
411};
412
413#define DA850_N_UI_PB 8
414
415static struct gpio_keys_button da850_evm_ui_keys[] = {
416 [0 ... DA850_N_UI_PB - 1] = {
417 .type = EV_KEY,
418 .active_low = 1,
419 .wakeup = 0,
420 .debounce_interval = DA850_KEYS_DEBOUNCE_MS,
421 .code = -1, /* assigned at runtime */
422 .gpio = -1, /* assigned at runtime */
423 .desc = NULL, /* assigned at runtime */
424 },
425};
426
427static struct gpio_keys_platform_data da850_evm_ui_keys_pdata = {
428 .buttons = da850_evm_ui_keys,
429 .nbuttons = ARRAY_SIZE(da850_evm_ui_keys),
430 .poll_interval = DA850_GPIO_KEYS_POLL_MS,
431};
432
433static struct platform_device da850_evm_ui_keys_device = {
434 .name = "gpio-keys-polled",
435 .id = 0,
436 .dev = {
437 .platform_data = &da850_evm_ui_keys_pdata
438 },
439};
440
441static void da850_evm_ui_keys_init(unsigned gpio)
442{
443 int i;
444 struct gpio_keys_button *button;
445
446 for (i = 0; i < DA850_N_UI_PB; i++) {
447 button = &da850_evm_ui_keys[i];
448 button->code = KEY_F8 - i;
449 button->desc = (char *)
450 da850_evm_ui_exp[DA850_EVM_UI_EXP_PB8 + i];
451 button->gpio = gpio + DA850_EVM_UI_EXP_PB8 + i;
452 }
453}
454
1e046d17
MH		 455#ifdef CONFIG_DA850_UI_SD_VIDEO_PORT
456static inline void da850_evm_setup_video_port(int video_sel)
457{
458 gpio_set_value_cansleep(video_sel, 0);
459}
460#else
461static inline void da850_evm_setup_video_port(int video_sel) { }
462#endif
463
75e2ea64
C		 464static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
465 unsigned ngpio, void *c)
466{
467 int sel_a, sel_b, sel_c, ret;
468
53c2897d
BG		 469 sel_a = gpio + DA850_EVM_UI_EXP_SEL_A;
470 sel_b = gpio + DA850_EVM_UI_EXP_SEL_B;
471 sel_c = gpio + DA850_EVM_UI_EXP_SEL_C;
75e2ea64 472
53c2897d 473 ret = gpio_request(sel_a, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_A]);
75e2ea64 474 if (ret) {
6c7c23cc 475 pr_warn("Cannot open UI expander pin %d\n", sel_a);
75e2ea64
C		 476 goto exp_setup_sela_fail;
477 }
478
53c2897d 479 ret = gpio_request(sel_b, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_B]);
75e2ea64 480 if (ret) {
6c7c23cc 481 pr_warn("Cannot open UI expander pin %d\n", sel_b);
75e2ea64
C		 482 goto exp_setup_selb_fail;
483 }
484
53c2897d 485 ret = gpio_request(sel_c, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_C]);
75e2ea64 486 if (ret) {
6c7c23cc 487 pr_warn("Cannot open UI expander pin %d\n", sel_c);
75e2ea64
C		 488 goto exp_setup_selc_fail;
489 }
490
491 /* deselect all functionalities */
492 gpio_direction_output(sel_a, 1);
493 gpio_direction_output(sel_b, 1);
494 gpio_direction_output(sel_c, 1);
495
75929f5e
BG		 496 da850_evm_ui_keys_init(gpio);
497 ret = platform_device_register(&da850_evm_ui_keys_device);
498 if (ret) {
6c7c23cc 499 pr_warn("Could not register UI GPIO expander push-buttons");
75929f5e
BG		 500 goto exp_setup_keys_fail;
501 }
502
75e2ea64
C		 503 pr_info("DA850/OMAP-L138 EVM UI card detected\n");
504
505 da850_evm_setup_nor_nand();
506
bae10587 507 da850_evm_setup_emac_rmii(sel_a);
2206771c 508
1e046d17
MH		 509 da850_evm_setup_video_port(sel_c);
510
75e2ea64
C		 511 return 0;
512
75929f5e
BG		 513exp_setup_keys_fail:
514 gpio_free(sel_c);
75e2ea64
C		 515exp_setup_selc_fail:
516 gpio_free(sel_b);
517exp_setup_selb_fail:
518 gpio_free(sel_a);
519exp_setup_sela_fail:
520 return ret;
521}
522
523static int da850_evm_ui_expander_teardown(struct i2c_client *client,
524 unsigned gpio, unsigned ngpio, void *c)
525{
75929f5e
BG		 526 platform_device_unregister(&da850_evm_ui_keys_device);
527
75e2ea64 528 /* deselect all functionalities */
53c2897d
BG		 529 gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_C, 1);
530 gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_B, 1);
531 gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_A, 1);
75e2ea64 532
53c2897d
BG		 533 gpio_free(gpio + DA850_EVM_UI_EXP_SEL_C);
534 gpio_free(gpio + DA850_EVM_UI_EXP_SEL_B);
535 gpio_free(gpio + DA850_EVM_UI_EXP_SEL_A);
75e2ea64
C		 536
537 return 0;
538}
539
70b30939
BG		 540/* assign the baseboard expander's GPIOs after the UI board's */
541#define DA850_UI_EXPANDER_N_GPIOS ARRAY_SIZE(da850_evm_ui_exp)
542#define DA850_BB_EXPANDER_GPIO_BASE (DAVINCI_N_GPIO + DA850_UI_EXPANDER_N_GPIOS)
543
544enum da850_evm_bb_exp_pins {
545 DA850_EVM_BB_EXP_DEEP_SLEEP_EN = 0,
546 DA850_EVM_BB_EXP_SW_RST,
547 DA850_EVM_BB_EXP_TP_23,
548 DA850_EVM_BB_EXP_TP_22,
549 DA850_EVM_BB_EXP_TP_21,
550 DA850_EVM_BB_EXP_USER_PB1,
551 DA850_EVM_BB_EXP_USER_LED2,
552 DA850_EVM_BB_EXP_USER_LED1,
553 DA850_EVM_BB_EXP_USER_SW1,
554 DA850_EVM_BB_EXP_USER_SW2,
555 DA850_EVM_BB_EXP_USER_SW3,
556 DA850_EVM_BB_EXP_USER_SW4,
557 DA850_EVM_BB_EXP_USER_SW5,
558 DA850_EVM_BB_EXP_USER_SW6,
559 DA850_EVM_BB_EXP_USER_SW7,
560 DA850_EVM_BB_EXP_USER_SW8
561};
562
58b6c5a1 563static const char * const da850_evm_bb_exp[] = {
70b30939
BG		 564 [DA850_EVM_BB_EXP_DEEP_SLEEP_EN] = "deep_sleep_en",
565 [DA850_EVM_BB_EXP_SW_RST] = "sw_rst",
566 [DA850_EVM_BB_EXP_TP_23] = "tp_23",
567 [DA850_EVM_BB_EXP_TP_22] = "tp_22",
568 [DA850_EVM_BB_EXP_TP_21] = "tp_21",
569 [DA850_EVM_BB_EXP_USER_PB1] = "user_pb1",
570 [DA850_EVM_BB_EXP_USER_LED2] = "user_led2",
571 [DA850_EVM_BB_EXP_USER_LED1] = "user_led1",
572 [DA850_EVM_BB_EXP_USER_SW1] = "user_sw1",
573 [DA850_EVM_BB_EXP_USER_SW2] = "user_sw2",
574 [DA850_EVM_BB_EXP_USER_SW3] = "user_sw3",
575 [DA850_EVM_BB_EXP_USER_SW4] = "user_sw4",
576 [DA850_EVM_BB_EXP_USER_SW5] = "user_sw5",
577 [DA850_EVM_BB_EXP_USER_SW6] = "user_sw6",
578 [DA850_EVM_BB_EXP_USER_SW7] = "user_sw7",
579 [DA850_EVM_BB_EXP_USER_SW8] = "user_sw8",
580};
581
582#define DA850_N_BB_USER_SW 8
583
584static struct gpio_keys_button da850_evm_bb_keys[] = {
585 [0] = {
586 .type = EV_KEY,
587 .active_low = 1,
588 .wakeup = 0,
589 .debounce_interval = DA850_KEYS_DEBOUNCE_MS,
590 .code = KEY_PROG1,
591 .desc = NULL, /* assigned at runtime */
592 .gpio = -1, /* assigned at runtime */
593 },
594 [1 ... DA850_N_BB_USER_SW] = {
595 .type = EV_SW,
596 .active_low = 1,
597 .wakeup = 0,
598 .debounce_interval = DA850_KEYS_DEBOUNCE_MS,
599 .code = -1, /* assigned at runtime */
600 .desc = NULL, /* assigned at runtime */
601 .gpio = -1, /* assigned at runtime */
602 },
603};
604
605static struct gpio_keys_platform_data da850_evm_bb_keys_pdata = {
606 .buttons = da850_evm_bb_keys,
607 .nbuttons = ARRAY_SIZE(da850_evm_bb_keys),
608 .poll_interval = DA850_GPIO_KEYS_POLL_MS,
609};
610
611static struct platform_device da850_evm_bb_keys_device = {
612 .name = "gpio-keys-polled",
613 .id = 1,
614 .dev = {
615 .platform_data = &da850_evm_bb_keys_pdata
616 },
617};
618
619static void da850_evm_bb_keys_init(unsigned gpio)
620{
621 int i;
622 struct gpio_keys_button *button;
623
624 button = &da850_evm_bb_keys[0];
625 button->desc = (char *)
626 da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_PB1];
627 button->gpio = gpio + DA850_EVM_BB_EXP_USER_PB1;
628
629 for (i = 0; i < DA850_N_BB_USER_SW; i++) {
630 button = &da850_evm_bb_keys[i + 1];
631 button->code = SW_LID + i;
632 button->desc = (char *)
633 da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_SW1 + i];
634 button->gpio = gpio + DA850_EVM_BB_EXP_USER_SW1 + i;
635 }
636}
637
638#define DA850_N_BB_USER_LED 2
639
640static struct gpio_led da850_evm_bb_leds[] = {
641 [0 ... DA850_N_BB_USER_LED - 1] = {
642 .active_low = 1,
643 .gpio = -1, /* assigned at runtime */
644 .name = NULL, /* assigned at runtime */
645 },
646};
647
648static struct gpio_led_platform_data da850_evm_bb_leds_pdata = {
649 .leds = da850_evm_bb_leds,
650 .num_leds = ARRAY_SIZE(da850_evm_bb_leds),
651};
652
653static struct platform_device da850_evm_bb_leds_device = {
654 .name = "leds-gpio",
655 .id = -1,
656 .dev = {
657 .platform_data = &da850_evm_bb_leds_pdata
658 }
659};
660
661static void da850_evm_bb_leds_init(unsigned gpio)
662{
663 int i;
664 struct gpio_led *led;
665
666 for (i = 0; i < DA850_N_BB_USER_LED; i++) {
667 led = &da850_evm_bb_leds[i];
668
669 led->gpio = gpio + DA850_EVM_BB_EXP_USER_LED2 + i;
670 led->name =
671 da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_LED2 + i];
672 }
673}
674
675static int da850_evm_bb_expander_setup(struct i2c_client *client,
676 unsigned gpio, unsigned ngpio,
677 void *c)
678{
679 int ret;
680
681 /*
682 * Register the switches and pushbutton on the baseboard as a gpio-keys
683 * device.
684 */
685 da850_evm_bb_keys_init(gpio);
686 ret = platform_device_register(&da850_evm_bb_keys_device);
687 if (ret) {
6c7c23cc 688 pr_warn("Could not register baseboard GPIO expander keys");
70b30939
BG		 689 goto io_exp_setup_sw_fail;
690 }
691
692 da850_evm_bb_leds_init(gpio);
693 ret = platform_device_register(&da850_evm_bb_leds_device);
694 if (ret) {
6c7c23cc 695 pr_warn("Could not register baseboard GPIO expander LEDs");
70b30939
BG		 696 goto io_exp_setup_leds_fail;
697 }
698
699 return 0;
700
701io_exp_setup_leds_fail:
702 platform_device_unregister(&da850_evm_bb_keys_device);
703io_exp_setup_sw_fail:
704 return ret;
705}
706
707static int da850_evm_bb_expander_teardown(struct i2c_client *client,
708 unsigned gpio, unsigned ngpio, void *c)
709{
710 platform_device_unregister(&da850_evm_bb_leds_device);
711 platform_device_unregister(&da850_evm_bb_keys_device);
712
713 return 0;
714}
715
75e2ea64
C		 716static struct pca953x_platform_data da850_evm_ui_expander_info = {
717 .gpio_base = DAVINCI_N_GPIO,
718 .setup = da850_evm_ui_expander_setup,
719 .teardown = da850_evm_ui_expander_teardown,
75929f5e 720 .names = da850_evm_ui_exp,
75e2ea64
C		 721};
722
70b30939
BG		 723static struct pca953x_platform_data da850_evm_bb_expander_info = {
724 .gpio_base = DA850_BB_EXPANDER_GPIO_BASE,
725 .setup = da850_evm_bb_expander_setup,
726 .teardown = da850_evm_bb_expander_teardown,
727 .names = da850_evm_bb_exp,
728};
729
1a7ff8ff
C		 730static struct i2c_board_info __initdata da850_evm_i2c_devices[] = {
731 {
732 I2C_BOARD_INFO("tlv320aic3x", 0x18),
75e2ea64
C		 733 },
734 {
735 I2C_BOARD_INFO("tca6416", 0x20),
736 .platform_data = &da850_evm_ui_expander_info,
737 },
70b30939
BG		 738 {
739 I2C_BOARD_INFO("tca6416", 0x21),
740 .platform_data = &da850_evm_bb_expander_info,
741 },
1a7ff8ff
C		 742};
743
0fbc5592
SR		 744static struct davinci_i2c_platform_data da850_evm_i2c_0_pdata = {
745 .bus_freq = 100, /* kHz */
746 .bus_delay = 0, /* usec */
747};
748
491214e1
C		 749/* davinci da850 evm audio machine driver */
750static u8 da850_iis_serializer_direction[] = {
751 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
752 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
753 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, TX_MODE,
754 RX_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
755};
756
757static struct snd_platform_data da850_evm_snd_data = {
88abfd5b
MP		 758 .tx_dma_offset = 0x2000,
759 .rx_dma_offset = 0x2000,
760 .op_mode = DAVINCI_MCASP_IIS_MODE,
761 .num_serializer = ARRAY_SIZE(da850_iis_serializer_direction),
762 .tdm_slots = 2,
763 .serial_dir = da850_iis_serializer_direction,
764 .asp_chan_q = EVENTQ_0,
765 .ram_chan_q = EVENTQ_1,
766 .version = MCASP_VERSION_2,
767 .txnumevt = 1,
768 .rxnumevt = 1,
769 .sram_size_playback = SZ_8K,
770 .sram_size_capture = SZ_8K,
491214e1
C		 771};
772
c840fc74
MW		 773static const short da850_evm_mcasp_pins[] __initconst = {
774 DA850_AHCLKX, DA850_ACLKX, DA850_AFSX,
775 DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE,
776 DA850_AXR_11, DA850_AXR_12,
777 -1
778};
779
700691f2
SR		 780static int da850_evm_mmc_get_ro(int index)
781{
782 return gpio_get_value(DA850_MMCSD_WP_PIN);
783}
784
785static int da850_evm_mmc_get_cd(int index)
786{
787 return !gpio_get_value(DA850_MMCSD_CD_PIN);
788}
789
790static struct davinci_mmc_config da850_mmc_config = {
791 .get_ro = da850_evm_mmc_get_ro,
792 .get_cd = da850_evm_mmc_get_cd,
793 .wires = 4,
0046d0bf
C		 794 .max_freq = 50000000,
795 .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
700691f2
SR		 796};
797
5a0d80ea
MW		 798static const short da850_evm_mmcsd0_pins[] __initconst = {
799 DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2,
800 DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD,
801 DA850_GPIO4_0, DA850_GPIO4_1,
802 -1
803};
804
d52f235f
C		 805static void da850_panel_power_ctrl(int val)
806{
807 /* lcd backlight */
808 gpio_set_value(DA850_LCD_BL_PIN, val);
809
810 /* lcd power */
811 gpio_set_value(DA850_LCD_PWR_PIN, val);
812}
813
5cbdf276
SR		 814static int da850_lcd_hw_init(void)
815{
816 int status;
817
818 status = gpio_request(DA850_LCD_BL_PIN, "lcd bl\n");
819 if (status < 0)
820 return status;
821
822 status = gpio_request(DA850_LCD_PWR_PIN, "lcd pwr\n");
823 if (status < 0) {
824 gpio_free(DA850_LCD_BL_PIN);
825 return status;
826 }
827
828 gpio_direction_output(DA850_LCD_BL_PIN, 0);
829 gpio_direction_output(DA850_LCD_PWR_PIN, 0);
830
d52f235f
C		 831 /* Switch off panel power and backlight */
832 da850_panel_power_ctrl(0);
5cbdf276 833
d52f235f
C		 834 /* Switch on panel power and backlight */
835 da850_panel_power_ctrl(1);
5cbdf276
SR		 836
837 return 0;
838}
491214e1 839
a9eb1f67
SN		 840/* TPS65070 voltage regulator support */
841
842/* 3.3V */
db549d22 843static struct regulator_consumer_supply tps65070_dcdc1_consumers[] = {
a9eb1f67
SN		 844 {
845 .supply = "usb0_vdda33",
846 },
847 {
848 .supply = "usb1_vdda33",
849 },
850};
851
852/* 3.3V or 1.8V */
db549d22 853static struct regulator_consumer_supply tps65070_dcdc2_consumers[] = {
a9eb1f67
SN		 854 {
855 .supply = "dvdd3318_a",
856 },
857 {
858 .supply = "dvdd3318_b",
859 },
860 {
861 .supply = "dvdd3318_c",
862 },
863};
864
865/* 1.2V */
db549d22 866static struct regulator_consumer_supply tps65070_dcdc3_consumers[] = {
a9eb1f67
SN		 867 {
868 .supply = "cvdd",
869 },
870};
871
872/* 1.8V LDO */
db549d22 873static struct regulator_consumer_supply tps65070_ldo1_consumers[] = {
a9eb1f67
SN		 874 {
875 .supply = "sata_vddr",
876 },
877 {
878 .supply = "usb0_vdda18",
879 },
880 {
881 .supply = "usb1_vdda18",
882 },
883 {
884 .supply = "ddr_dvdd18",
885 },
886};
887
888/* 1.2V LDO */
db549d22 889static struct regulator_consumer_supply tps65070_ldo2_consumers[] = {
a9eb1f67
SN		 890 {
891 .supply = "sata_vdd",
892 },
893 {
894 .supply = "pll0_vdda",
895 },
896 {
897 .supply = "pll1_vdda",
898 },
899 {
900 .supply = "usbs_cvdd",
901 },
902 {
903 .supply = "vddarnwa1",
904 },
905};
906
8b24599e
SN		 907/* We take advantage of the fact that both defdcdc{2,3} are tied high */
908static struct tps6507x_reg_platform_data tps6507x_platform_data = {
909 .defdcdc_default = true,
910};
911
db549d22 912static struct regulator_init_data tps65070_regulator_data[] = {
a9eb1f67
SN		 913 /* dcdc1 */
914 {
915 .constraints = {
916 .min_uV = 3150000,
917 .max_uV = 3450000,
918 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
919 REGULATOR_CHANGE_STATUS),
920 .boot_on = 1,
921 },
922 .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc1_consumers),
923 .consumer_supplies = tps65070_dcdc1_consumers,
924 },
925
926 /* dcdc2 */
927 {
928 .constraints = {
929 .min_uV = 1710000,
930 .max_uV = 3450000,
931 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
932 REGULATOR_CHANGE_STATUS),
933 .boot_on = 1,
934 },
935 .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc2_consumers),
936 .consumer_supplies = tps65070_dcdc2_consumers,
8b24599e 937 .driver_data = &tps6507x_platform_data,
a9eb1f67
SN		 938 },
939
940 /* dcdc3 */
941 {
942 .constraints = {
943 .min_uV = 950000,
28bd2c34 944 .max_uV = 1350000,
a9eb1f67
SN		 945 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
946 REGULATOR_CHANGE_STATUS),
947 .boot_on = 1,
948 },
949 .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc3_consumers),
950 .consumer_supplies = tps65070_dcdc3_consumers,
8b24599e 951 .driver_data = &tps6507x_platform_data,
a9eb1f67
SN		 952 },
953
954 /* ldo1 */
955 {
956 .constraints = {
957 .min_uV = 1710000,
958 .max_uV = 1890000,
959 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
960 REGULATOR_CHANGE_STATUS),
961 .boot_on = 1,
962 },
963 .num_consumer_supplies = ARRAY_SIZE(tps65070_ldo1_consumers),
964 .consumer_supplies = tps65070_ldo1_consumers,
965 },
966
967 /* ldo2 */
968 {
969 .constraints = {
970 .min_uV = 1140000,
971 .max_uV = 1320000,
972 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
973 REGULATOR_CHANGE_STATUS),
974 .boot_on = 1,
975 },
976 .num_consumer_supplies = ARRAY_SIZE(tps65070_ldo2_consumers),
977 .consumer_supplies = tps65070_ldo2_consumers,
978 },
979};
980
da1e3680
TF		 981static struct touchscreen_init_data tps6507x_touchscreen_data = {
982 .poll_period = 30, /* ms between touch samples */
983 .min_pressure = 0x30, /* minimum pressure to trigger touch */
da1e3680
TF		 984 .vendor = 0, /* /sys/class/input/input?/id/vendor */
985 .product = 65070, /* /sys/class/input/input?/id/product */
986 .version = 0x100, /* /sys/class/input/input?/id/version */
987};
988
0bc20bba
TF		 989static struct tps6507x_board tps_board = {
990 .tps6507x_pmic_init_data = &tps65070_regulator_data[0],
da1e3680 991 .tps6507x_ts_init_data = &tps6507x_touchscreen_data,
0bc20bba
TF		 992};
993
3506f277 994static struct i2c_board_info __initdata da850_evm_tps65070_info[] = {
a9eb1f67
SN		 995 {
996 I2C_BOARD_INFO("tps6507x", 0x48),
0bc20bba 997 .platform_data = &tps_board,
a9eb1f67
SN		 998 },
999};
1000
1001static int __init pmic_tps65070_init(void)
1002{
3506f277
BG		 1003 return i2c_register_board_info(1, da850_evm_tps65070_info,
1004 ARRAY_SIZE(da850_evm_tps65070_info));
a9eb1f67
SN		 1005}
1006
7761ef67
SR		 1007static const short da850_evm_lcdc_pins[] = {
1008 DA850_GPIO2_8, DA850_GPIO2_15,
1009 -1
1010};
1011
85b8307f
SS		 1012static const short da850_evm_mii_pins[] = {
1013 DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
1014 DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
1015 DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
1016 DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
1017 DA850_MDIO_D,
1018 -1
1019};
1020
1021static const short da850_evm_rmii_pins[] = {
1022 DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
1023 DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
1024 DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
1025 DA850_MDIO_D,
1026 -1
1027};
1028
bae10587 1029static int __init da850_evm_config_emac(void)
2206771c
C		 1030{
1031 void __iomem *cfg_chip3_base;
1032 int ret;
1033 u32 val;
bae10587
SN		 1034 struct davinci_soc_info *soc_info = &davinci_soc_info;
1035 u8 rmii_en = soc_info->emac_pdata->rmii_en;
1036
1037 if (!machine_is_davinci_da850_evm())
1038 return 0;
2206771c 1039
d2de0582 1040 cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
2206771c 1041
2206771c 1042 val = __raw_readl(cfg_chip3_base);
17fadd9a
SN		 1043
1044 if (rmii_en) {
2206771c 1045 val |= BIT(8);
85b8307f 1046 ret = davinci_cfg_reg_list(da850_evm_rmii_pins);
17fadd9a
SN		 1047 pr_info("EMAC: RMII PHY configured, MII PHY will not be"
1048 " functional\n");
1049 } else {
2206771c 1050 val &= ~BIT(8);
85b8307f 1051 ret = davinci_cfg_reg_list(da850_evm_mii_pins);
17fadd9a
SN		 1052 pr_info("EMAC: MII PHY configured, RMII PHY will not be"
1053 " functional\n");
1054 }
1055
2206771c 1056 if (ret)
6c7c23cc
RT		 1057 pr_warn("%s: CPGMAC/RMII mux setup failed: %d\n",
1058 __func__, ret);
2206771c 1059
17fadd9a
SN		 1060 /* configure the CFGCHIP3 register for RMII or MII */
1061 __raw_writel(val, cfg_chip3_base);
1062
2206771c
C		 1063 ret = davinci_cfg_reg(DA850_GPIO2_6);
1064 if (ret)
6c7c23cc 1065 pr_warn("%s:GPIO(2,6) mux setup failed\n", __func__);
2206771c
C		 1066
1067 ret = gpio_request(DA850_MII_MDIO_CLKEN_PIN, "mdio_clk_en");
1068 if (ret) {
6c7c23cc 1069 pr_warn("Cannot open GPIO %d\n", DA850_MII_MDIO_CLKEN_PIN);
2206771c
C		 1070 return ret;
1071 }
1072
17fadd9a
SN		 1073 /* Enable/Disable MII MDIO clock */
1074 gpio_direction_output(DA850_MII_MDIO_CLKEN_PIN, rmii_en);
2206771c 1075
782f2d78 1076 soc_info->emac_pdata->phy_id = DA850_EVM_PHY_ID;
bae10587
SN		 1077
1078 ret = da8xx_register_emac();
1079 if (ret)
6c7c23cc 1080 pr_warn("%s: EMAC registration failed: %d\n", __func__, ret);
bae10587 1081
2206771c
C		 1082 return 0;
1083}
bae10587 1084device_initcall(da850_evm_config_emac);
2206771c 1085
a941c503
RS		 1086/*
1087 * The following EDMA channels/slots are not being used by drivers (for
1088 * example: Timer, GPIO, UART events etc) on da850/omap-l138 EVM, hence
1089 * they are being reserved for codecs on the DSP side.
1090 */
1091static const s16 da850_dma0_rsv_chans[][2] = {
1092 /* (offset, number) */
1093 { 8, 6},
1094 {24, 4},
1095 {30, 2},
1096 {-1, -1}
1097};
1098
1099static const s16 da850_dma0_rsv_slots[][2] = {
1100 /* (offset, number) */
1101 { 8, 6},
1102 {24, 4},
1103 {30, 50},
1104 {-1, -1}
1105};
1106
1107static const s16 da850_dma1_rsv_chans[][2] = {
1108 /* (offset, number) */
1109 { 0, 28},
1110 {30, 2},
1111 {-1, -1}
1112};
1113
1114static const s16 da850_dma1_rsv_slots[][2] = {
1115 /* (offset, number) */
1116 { 0, 28},
1117 {30, 90},
1118 {-1, -1}
1119};
1120
1121static struct edma_rsv_info da850_edma_cc0_rsv = {
1122 .rsv_chans = da850_dma0_rsv_chans,
1123 .rsv_slots = da850_dma0_rsv_slots,
1124};
1125
1126static struct edma_rsv_info da850_edma_cc1_rsv = {
1127 .rsv_chans = da850_dma1_rsv_chans,
1128 .rsv_slots = da850_dma1_rsv_slots,
1129};
1130
1131static struct edma_rsv_info *da850_edma_rsv[2] = {
1132 &da850_edma_cc0_rsv,
1133 &da850_edma_cc1_rsv,
1134};
1135
28bd2c34
SN		 1136#ifdef CONFIG_CPU_FREQ
1137static __init int da850_evm_init_cpufreq(void)
1138{
1139 switch (system_rev & 0xF) {
1140 case 3:
1141 da850_max_speed = 456000;
1142 break;
1143 case 2:
1144 da850_max_speed = 408000;
1145 break;
1146 case 1:
1147 da850_max_speed = 372000;
1148 break;
1149 }
1150
1151 return da850_register_cpufreq("pll0_sysclk3");
1152}
1153#else
1154static __init int da850_evm_init_cpufreq(void) { return 0; }
1155#endif
1156
1e046d17
MH		 1157#if defined(CONFIG_DA850_UI_SD_VIDEO_PORT)
1158
1159#define TVP5147_CH0 "tvp514x-0"
1160#define TVP5147_CH1 "tvp514x-1"
1161
1162/* VPIF capture configuration */
1163static struct tvp514x_platform_data tvp5146_pdata = {
1164 .clk_polarity = 0,
1165 .hs_polarity = 1,
1166 .vs_polarity = 1,
1167};
1168
1169#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
1170
1171static const struct vpif_input da850_ch0_inputs[] = {
1172 {
1173 .input = {
1174 .index = 0,
1175 .name = "Composite",
1176 .type = V4L2_INPUT_TYPE_CAMERA,
7aaad131 1177 .capabilities = V4L2_IN_CAP_STD,
1e046d17
MH		 1178 .std = TVP514X_STD_ALL,
1179 },
7aaad131
HV		 1180 .input_route = INPUT_CVBS_VI2B,
1181 .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC,
1e046d17
MH		 1182 .subdev_name = TVP5147_CH0,
1183 },
1184};
1185
1186static const struct vpif_input da850_ch1_inputs[] = {
1187 {
1188 .input = {
1189 .index = 0,
1190 .name = "S-Video",
1191 .type = V4L2_INPUT_TYPE_CAMERA,
7aaad131 1192 .capabilities = V4L2_IN_CAP_STD,
1e046d17
MH		 1193 .std = TVP514X_STD_ALL,
1194 },
7aaad131
HV		 1195 .input_route = INPUT_SVIDEO_VI2C_VI1C,
1196 .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC,
1e046d17
MH		 1197 .subdev_name = TVP5147_CH1,
1198 },
1199};
1200
1201static struct vpif_subdev_info da850_vpif_capture_sdev_info[] = {
1202 {
1203 .name = TVP5147_CH0,
1204 .board_info = {
1205 I2C_BOARD_INFO("tvp5146", 0x5d),
1206 .platform_data = &tvp5146_pdata,
1207 },
1e046d17
MH		 1208 },
1209 {
1210 .name = TVP5147_CH1,
1211 .board_info = {
1212 I2C_BOARD_INFO("tvp5146", 0x5c),
1213 .platform_data = &tvp5146_pdata,
1214 },
1e046d17
MH		 1215 },
1216};
1217
1218static struct vpif_capture_config da850_vpif_capture_config = {
1219 .subdev_info = da850_vpif_capture_sdev_info,
1220 .subdev_count = ARRAY_SIZE(da850_vpif_capture_sdev_info),
1221 .chan_config[0] = {
1222 .inputs = da850_ch0_inputs,
1223 .input_count = ARRAY_SIZE(da850_ch0_inputs),
0d4f35f3
HV		 1224 .vpif_if = {
1225 .if_type = VPIF_IF_BT656,
1226 .hd_pol = 1,
1227 .vd_pol = 1,
1228 .fid_pol = 0,
1229 },
1e046d17
MH		 1230 },
1231 .chan_config[1] = {
1232 .inputs = da850_ch1_inputs,
1233 .input_count = ARRAY_SIZE(da850_ch1_inputs),
0d4f35f3
HV		 1234 .vpif_if = {
1235 .if_type = VPIF_IF_BT656,
1236 .hd_pol = 1,
1237 .vd_pol = 1,
1238 .fid_pol = 0,
1239 },
1e046d17
MH		 1240 },
1241 .card_name = "DA850/OMAP-L138 Video Capture",
1242};
1243
1244/* VPIF display configuration */
3e85a44a
LP		 1245
1246static struct adv7343_platform_data adv7343_pdata = {
1247 .mode_config = {
5e95814f 1248 .dac = { 1, 1, 1 },
3e85a44a
LP		 1249 },
1250 .sd_config = {
5e95814f 1251 .sd_dac_out = { 1 },
3e85a44a
LP		 1252 },
1253};
1254
1e046d17
MH		 1255static struct vpif_subdev_info da850_vpif_subdev[] = {
1256 {
1257 .name = "adv7343",
1258 .board_info = {
1259 I2C_BOARD_INFO("adv7343", 0x2a),
3e85a44a 1260 .platform_data = &adv7343_pdata,
1e046d17
MH		 1261 },
1262 },
1263};
1264
2bd4e58c
LP		 1265static const struct vpif_output da850_ch0_outputs[] = {
1266 {
1267 .output = {
1268 .index = 0,
1269 .name = "Composite",
1270 .type = V4L2_OUTPUT_TYPE_ANALOG,
1271 .capabilities = V4L2_OUT_CAP_STD,
1272 .std = V4L2_STD_ALL,
1273 },
1274 .subdev_name = "adv7343",
1275 .output_route = ADV7343_COMPOSITE_ID,
1276 },
1277 {
1278 .output = {
1279 .index = 1,
1280 .name = "S-Video",
1281 .type = V4L2_OUTPUT_TYPE_ANALOG,
1282 .capabilities = V4L2_OUT_CAP_STD,
1283 .std = V4L2_STD_ALL,
1284 },
1285 .subdev_name = "adv7343",
1286 .output_route = ADV7343_SVIDEO_ID,
1287 },
1e046d17
MH		 1288};
1289
1290static struct vpif_display_config da850_vpif_display_config = {
1291 .subdevinfo = da850_vpif_subdev,
1292 .subdev_count = ARRAY_SIZE(da850_vpif_subdev),
2bd4e58c
LP		 1293 .chan_config[0] = {
1294 .outputs = da850_ch0_outputs,
1295 .output_count = ARRAY_SIZE(da850_ch0_outputs),
1296 },
1e046d17
MH		 1297 .card_name = "DA850/OMAP-L138 Video Display",
1298};
1299
1300static __init void da850_vpif_init(void)
1301{
1302 int ret;
1303
1304 ret = da850_register_vpif();
1305 if (ret)
1306 pr_warn("da850_evm_init: VPIF setup failed: %d\n", ret);
1307
1308 ret = davinci_cfg_reg_list(da850_vpif_capture_pins);
1309 if (ret)
1310 pr_warn("da850_evm_init: VPIF capture mux setup failed: %d\n",
1311 ret);
1312
1313 ret = da850_register_vpif_capture(&da850_vpif_capture_config);
1314 if (ret)
1315 pr_warn("da850_evm_init: VPIF capture setup failed: %d\n", ret);
1316
1317 ret = davinci_cfg_reg_list(da850_vpif_display_pins);
1318 if (ret)
1319 pr_warn("da850_evm_init: VPIF display mux setup failed: %d\n",
1320 ret);
1321
1322 ret = da850_register_vpif_display(&da850_vpif_display_config);
1323 if (ret)
1324 pr_warn("da850_evm_init: VPIF display setup failed: %d\n", ret);
1325}
1326
1327#else
1328static __init void da850_vpif_init(void) {}
1329#endif
1330
ab3f5c1f
IY		 1331#ifdef CONFIG_DA850_WL12XX
1332
1333static void wl12xx_set_power(int index, bool power_on)
1334{
1335 static bool power_state;
1336
1337 pr_debug("Powering %s wl12xx", power_on ? "on" : "off");
1338
1339 if (power_on == power_state)
1340 return;
1341 power_state = power_on;
1342
1343 if (power_on) {
1344 /* Power up sequence required for wl127x devices */
1345 gpio_set_value(DA850_WLAN_EN, 1);
1346 usleep_range(15000, 15000);
1347 gpio_set_value(DA850_WLAN_EN, 0);
1348 usleep_range(1000, 1000);
1349 gpio_set_value(DA850_WLAN_EN, 1);
1350 msleep(70);
1351 } else {
1352 gpio_set_value(DA850_WLAN_EN, 0);
1353 }
1354}
1355
1356static struct davinci_mmc_config da850_wl12xx_mmc_config = {
1357 .set_power = wl12xx_set_power,
1358 .wires = 4,
1359 .max_freq = 25000000,
1360 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_NONREMOVABLE |
1361 MMC_CAP_POWER_OFF_CARD,
ab3f5c1f
IY		 1362};
1363
1364static const short da850_wl12xx_pins[] __initconst = {
1365 DA850_MMCSD1_DAT_0, DA850_MMCSD1_DAT_1, DA850_MMCSD1_DAT_2,
1366 DA850_MMCSD1_DAT_3, DA850_MMCSD1_CLK, DA850_MMCSD1_CMD,
1367 DA850_GPIO6_9, DA850_GPIO6_10,
1368 -1
1369};
1370
1371static struct wl12xx_platform_data da850_wl12xx_wlan_data __initdata = {
1372 .irq = -1,
1373 .board_ref_clock = WL12XX_REFCLOCK_38,
1374 .platform_quirks = WL12XX_PLATFORM_QUIRK_EDGE_IRQ,
1375};
1376
1377static __init int da850_wl12xx_init(void)
1378{
1379 int ret;
1380
1381 ret = davinci_cfg_reg_list(da850_wl12xx_pins);
1382 if (ret) {
1383 pr_err("wl12xx/mmc mux setup failed: %d\n", ret);
1384 goto exit;
1385 }
1386
1387 ret = da850_register_mmcsd1(&da850_wl12xx_mmc_config);
1388 if (ret) {
1389 pr_err("wl12xx/mmc registration failed: %d\n", ret);
1390 goto exit;
1391 }
1392
1393 ret = gpio_request_one(DA850_WLAN_EN, GPIOF_OUT_INIT_LOW, "wl12xx_en");
1394 if (ret) {
1395 pr_err("Could not request wl12xx enable gpio: %d\n", ret);
1396 goto exit;
1397 }
1398
1399 ret = gpio_request_one(DA850_WLAN_IRQ, GPIOF_IN, "wl12xx_irq");
1400 if (ret) {
1401 pr_err("Could not request wl12xx irq gpio: %d\n", ret);
1402 goto free_wlan_en;
1403 }
1404
1405 da850_wl12xx_wlan_data.irq = gpio_to_irq(DA850_WLAN_IRQ);
1406
1407 ret = wl12xx_set_platform_data(&da850_wl12xx_wlan_data);
1408 if (ret) {
1409 pr_err("Could not set wl12xx data: %d\n", ret);
1410 goto free_wlan_irq;
1411 }
1412
1413 return 0;
1414
1415free_wlan_irq:
1416 gpio_free(DA850_WLAN_IRQ);
1417
1418free_wlan_en:
1419 gpio_free(DA850_WLAN_EN);
1420
1421exit:
1422 return ret;
1423}
1424
1425#else /* CONFIG_DA850_WL12XX */
1426
1427static __init int da850_wl12xx_init(void)
1428{
1429 return 0;
1430}
1431
1432#endif /* CONFIG_DA850_WL12XX */
1433
8bb2c481
SN		 1434#define DA850EVM_SATA_REFCLKPN_RATE (100 * 1000 * 1000)
1435
0fbc5592
SR		 1436static __init void da850_evm_init(void)
1437{
1438 int ret;
1439
a9eb1f67
SN		 1440 ret = pmic_tps65070_init();
1441 if (ret)
6c7c23cc 1442 pr_warn("%s: TPS65070 PMIC init failed: %d\n", __func__, ret);
a9eb1f67 1443
a941c503 1444 ret = da850_register_edma(da850_edma_rsv);
0fbc5592 1445 if (ret)
6c7c23cc 1446 pr_warn("%s: EDMA registration failed: %d\n", __func__, ret);
0fbc5592 1447
3821d10a 1448 ret = davinci_cfg_reg_list(da850_i2c0_pins);
0fbc5592 1449 if (ret)
6c7c23cc 1450 pr_warn("%s: I2C0 mux setup failed: %d\n", __func__, ret);
0fbc5592
SR		 1451
1452 ret = da8xx_register_i2c(0, &da850_evm_i2c_0_pdata);
1453 if (ret)
6c7c23cc 1454 pr_warn("%s: I2C0 registration failed: %d\n", __func__, ret);
0fbc5592 1455
5a4b1315 1456
0fbc5592
SR		 1457 ret = da8xx_register_watchdog();
1458 if (ret)
6c7c23cc
RT		 1459 pr_warn("%s: watchdog registration failed: %d\n",
1460 __func__, ret);
0fbc5592 1461
820c4fe3 1462 if (HAS_MMC) {
5a0d80ea 1463 ret = davinci_cfg_reg_list(da850_evm_mmcsd0_pins);
820c4fe3 1464 if (ret)
6c7c23cc
RT		 1465 pr_warn("%s: MMCSD0 mux setup failed: %d\n",
1466 __func__, ret);
820c4fe3
SR		 1467
1468 ret = gpio_request(DA850_MMCSD_CD_PIN, "MMC CD\n");
1469 if (ret)
6c7c23cc
RT		 1470 pr_warn("%s: can not open GPIO %d\n",
1471 __func__, DA850_MMCSD_CD_PIN);
820c4fe3
SR		 1472 gpio_direction_input(DA850_MMCSD_CD_PIN);
1473
1474 ret = gpio_request(DA850_MMCSD_WP_PIN, "MMC WP\n");
1475 if (ret)
6c7c23cc
RT		 1476 pr_warn("%s: can not open GPIO %d\n",
1477 __func__, DA850_MMCSD_WP_PIN);
820c4fe3
SR		 1478 gpio_direction_input(DA850_MMCSD_WP_PIN);
1479
1480 ret = da8xx_register_mmcsd0(&da850_mmc_config);
1481 if (ret)
6c7c23cc
RT		 1482 pr_warn("%s: MMCSD0 registration failed: %d\n",
1483 __func__, ret);
ab3f5c1f
IY		 1484
1485 ret = da850_wl12xx_init();
1486 if (ret)
6c7c23cc
RT		 1487 pr_warn("%s: WL12xx initialization failed: %d\n",
1488 __func__, ret);
820c4fe3 1489 }
700691f2 1490
fcf7157b 1491 davinci_serial_init(da8xx_serial_device);
0fbc5592 1492
1a7ff8ff
C		 1493 i2c_register_board_info(1, da850_evm_i2c_devices,
1494 ARRAY_SIZE(da850_evm_i2c_devices));
1495
0fbc5592
SR		 1496 /*
1497 * shut down uart 0 and 1; they are not used on the board and
1498 * accessing them causes endless "too much work in irq53" messages
1499 * with arago fs
1500 */
1501 __raw_writel(0, IO_ADDRESS(DA8XX_UART1_BASE) + 0x30);
1502 __raw_writel(0, IO_ADDRESS(DA8XX_UART0_BASE) + 0x30);
491214e1 1503
c840fc74 1504 ret = davinci_cfg_reg_list(da850_evm_mcasp_pins);
491214e1 1505 if (ret)
6c7c23cc 1506 pr_warn("%s: McASP mux setup failed: %d\n", __func__, ret);
491214e1 1507
88abfd5b 1508 da850_evm_snd_data.sram_pool = sram_get_gen_pool();
b8864aa4 1509 da8xx_register_mcasp(0, &da850_evm_snd_data);
5cbdf276 1510
3821d10a 1511 ret = davinci_cfg_reg_list(da850_lcdcntl_pins);
5cbdf276 1512 if (ret)
6c7c23cc 1513 pr_warn("%s: LCDC mux setup failed: %d\n", __func__, ret);
5cbdf276 1514
ae41d17a
MP		 1515 ret = da8xx_register_uio_pruss();
1516 if (ret)
1517 pr_warn("da850_evm_init: pruss initialization failed: %d\n",
1518 ret);
1519
7761ef67 1520 /* Handle board specific muxing for LCD here */
3821d10a 1521 ret = davinci_cfg_reg_list(da850_evm_lcdc_pins);
7761ef67 1522 if (ret)
6c7c23cc
RT		 1523 pr_warn("%s: EVM specific LCD mux setup failed: %d\n",
1524 __func__, ret);
7761ef67 1525
5cbdf276
SR		 1526 ret = da850_lcd_hw_init();
1527 if (ret)
6c7c23cc 1528 pr_warn("%s: LCD initialization failed: %d\n", __func__, ret);
5cbdf276 1529
d52f235f 1530 sharp_lk043t1dg01_pdata.panel_power_ctrl = da850_panel_power_ctrl,
b9e6342b 1531 ret = da8xx_register_lcdc(&sharp_lk043t1dg01_pdata);
5cbdf276 1532 if (ret)
6c7c23cc 1533 pr_warn("%s: LCDC registration failed: %d\n", __func__, ret);
c51df70b
MG		 1534
1535 ret = da8xx_register_rtc();
1536 if (ret)
6c7c23cc 1537 pr_warn("%s: RTC setup failed: %d\n", __func__, ret);
09dc2d45 1538
28bd2c34 1539 ret = da850_evm_init_cpufreq();
09dc2d45 1540 if (ret)
6c7c23cc 1541 pr_warn("%s: cpufreq registration failed: %d\n", __func__, ret);
5aeb15aa
SN		 1542
1543 ret = da8xx_register_cpuidle();
1544 if (ret)
6c7c23cc 1545 pr_warn("%s: cpuidle registration failed: %d\n", __func__, ret);
63534443
SN		 1546
1547 ret = da850_register_pm(&da850_pm_device);
1548 if (ret)
6c7c23cc 1549 pr_warn("%s: suspend registration failed: %d\n", __func__, ret);
fdce5568 1550
1e046d17
MH		 1551 da850_vpif_init();
1552
0273612c
VD		 1553 ret = spi_register_board_info(da850evm_spi_info,
1554 ARRAY_SIZE(da850evm_spi_info));
1555 if (ret)
1556 pr_warn("%s: spi info registration failed: %d\n", __func__,
1557 ret);
1558
1559 ret = da8xx_register_spi_bus(1, ARRAY_SIZE(da850evm_spi_info));
fdce5568 1560 if (ret)
6c7c23cc 1561 pr_warn("%s: SPI 1 registration failed: %d\n", __func__, ret);
8bb2c481
SN		 1562
1563 ret = da850_register_sata(DA850EVM_SATA_REFCLKPN_RATE);
1564 if (ret)
6c7c23cc 1565 pr_warn("%s: SATA registration failed: %d\n", __func__, ret);
810198bc
RS		 1566
1567 da850_evm_setup_mac_addr();
54288134
RT		 1568
1569 ret = da8xx_register_rproc();
1570 if (ret)
1571 pr_warn("%s: dsp/rproc registration failed: %d\n",
1572 __func__, ret);
0fbc5592
SR		 1573}
1574
1575#ifdef CONFIG_SERIAL_8250_CONSOLE
1576static int __init da850_evm_console_init(void)
1577{
1aa5f2a9
MW		 1578 if (!machine_is_davinci_da850_evm())
1579 return 0;
1580
0fbc5592
SR		 1581 return add_preferred_console("ttyS", 2, "115200");
1582}
1583console_initcall(da850_evm_console_init);
1584#endif
1585
0fbc5592
SR		 1586static void __init da850_evm_map_io(void)
1587{
1588 da850_init();
1589}
1590
48ea89ea 1591MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138/AM18x EVM")
e7e56014 1592 .atag_offset = 0x100,
0fbc5592 1593 .map_io = da850_evm_map_io,
bd808947 1594 .init_irq = cp_intc_init,
6bb27d73 1595 .init_time = davinci_timer_init,
0fbc5592 1596 .init_machine = da850_evm_init,
3aa3e840 1597 .init_late = davinci_init_late,
f68deabf 1598 .dma_zone_size = SZ_128M,
c6121ddd 1599 .restart = da8xx_restart,
54288134 1600 .reserve = da8xx_rproc_reserve_cma,
0fbc5592 1601MACHINE_END
Linux kernel - Deliverables
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