[deliverable/linux.git] / arch / arm / mach-davinci / board-dm365-evm.c

/*
 * TI DaVinci DM365 EVM board support
 *
 * Copyright (C) 2009 Texas Instruments Incorporated
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/i2c/at24.h>
#include <linux/leds.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/slab.h>
#include <linux/mtd/nand.h>
#include <linux/input.h>
#include <linux/spi/spi.h>
#include <linux/spi/eeprom.h>

#include <asm/mach-types.h>
#include <asm/mach/arch.h>

#include <mach/mux.h>
#include <mach/dm365.h>
#include <mach/common.h>
#include <mach/i2c.h>
#include <mach/serial.h>
#include <mach/mmc.h>
#include <mach/nand.h>
#include <mach/keyscan.h>

#include <media/tvp514x.h>

static inline int have_imager(void)
{
	/* REVISIT when it's supported, trigger via Kconfig */
	return 0;
}

static inline int have_tvp7002(void)
{
	/* REVISIT when it's supported, trigger via Kconfig */
	return 0;
}

#define DM365_EVM_PHY_MASK		(0x2)
#define DM365_EVM_MDIO_FREQUENCY	(2200000) /* PHY bus frequency */

/*
 * A MAX-II CPLD is used for various board control functions.
 */
#define CPLD_OFFSET(a13a8,a2a1)		(((a13a8) << 10) + ((a2a1) << 3))

#define CPLD_VERSION	CPLD_OFFSET(0,0)	/* r/o */
#define CPLD_TEST	CPLD_OFFSET(0,1)
#define CPLD_LEDS	CPLD_OFFSET(0,2)
#define CPLD_MUX	CPLD_OFFSET(0,3)
#define CPLD_SWITCH	CPLD_OFFSET(1,0)	/* r/o */
#define CPLD_POWER	CPLD_OFFSET(1,1)
#define CPLD_VIDEO	CPLD_OFFSET(1,2)
#define CPLD_CARDSTAT	CPLD_OFFSET(1,3)	/* r/o */

#define CPLD_DILC_OUT	CPLD_OFFSET(2,0)
#define CPLD_DILC_IN	CPLD_OFFSET(2,1)	/* r/o */

#define CPLD_IMG_DIR0	CPLD_OFFSET(2,2)
#define CPLD_IMG_MUX0	CPLD_OFFSET(2,3)
#define CPLD_IMG_MUX1	CPLD_OFFSET(3,0)
#define CPLD_IMG_DIR1	CPLD_OFFSET(3,1)
#define CPLD_IMG_MUX2	CPLD_OFFSET(3,2)
#define CPLD_IMG_MUX3	CPLD_OFFSET(3,3)
#define CPLD_IMG_DIR2	CPLD_OFFSET(4,0)
#define CPLD_IMG_MUX4	CPLD_OFFSET(4,1)
#define CPLD_IMG_MUX5	CPLD_OFFSET(4,2)

#define CPLD_RESETS	CPLD_OFFSET(4,3)

#define CPLD_CCD_DIR1	CPLD_OFFSET(0x3e,0)
#define CPLD_CCD_IO1	CPLD_OFFSET(0x3e,1)
#define CPLD_CCD_DIR2	CPLD_OFFSET(0x3e,2)
#define CPLD_CCD_IO2	CPLD_OFFSET(0x3e,3)
#define CPLD_CCD_DIR3	CPLD_OFFSET(0x3f,0)
#define CPLD_CCD_IO3	CPLD_OFFSET(0x3f,1)

static void __iomem *cpld;


/* NOTE:  this is geared for the standard config, with a socketed
 * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors.  If you
 * swap chips with a different block size, partitioning will
 * need to be changed. This NAND chip MT29F16G08FAA is the default
 * NAND shipped with the Spectrum Digital DM365 EVM
 */
#define NAND_BLOCK_SIZE		SZ_128K

static struct mtd_partition davinci_nand_partitions[] = {
	{
		/* UBL (a few copies) plus U-Boot */
		.name		= "bootloader",
		.offset		= 0,
		.size		= 28 * NAND_BLOCK_SIZE,
		.mask_flags	= MTD_WRITEABLE, /* force read-only */
	}, {
		/* U-Boot environment */
		.name		= "params",
		.offset		= MTDPART_OFS_APPEND,
		.size		= 2 * NAND_BLOCK_SIZE,
		.mask_flags	= 0,
	}, {
		.name		= "kernel",
		.offset		= MTDPART_OFS_APPEND,
		.size		= SZ_4M,
		.mask_flags	= 0,
	}, {
		.name		= "filesystem1",
		.offset		= MTDPART_OFS_APPEND,
		.size		= SZ_512M,
		.mask_flags	= 0,
	}, {
		.name		= "filesystem2",
		.offset		= MTDPART_OFS_APPEND,
		.size		= MTDPART_SIZ_FULL,
		.mask_flags	= 0,
	}
	/* two blocks with bad block table (and mirror) at the end */
};

static struct davinci_nand_pdata davinci_nand_data = {
	.mask_chipsel		= BIT(14),
	.parts			= davinci_nand_partitions,
	.nr_parts		= ARRAY_SIZE(davinci_nand_partitions),
	.ecc_mode		= NAND_ECC_HW,
	.options		= NAND_USE_FLASH_BBT,
	.ecc_bits		= 4,
};

static struct resource davinci_nand_resources[] = {
	{
		.start		= DM365_ASYNC_EMIF_DATA_CE0_BASE,
		.end		= DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
		.flags		= IORESOURCE_MEM,
	}, {
		.start		= DM365_ASYNC_EMIF_CONTROL_BASE,
		.end		= DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
		.flags		= IORESOURCE_MEM,
	},
};

static struct platform_device davinci_nand_device = {
	.name			= "davinci_nand",
	.id			= 0,
	.num_resources		= ARRAY_SIZE(davinci_nand_resources),
	.resource		= davinci_nand_resources,
	.dev			= {
		.platform_data	= &davinci_nand_data,
	},
};

static struct at24_platform_data eeprom_info = {
	.byte_len       = (256*1024) / 8,
	.page_size      = 64,
	.flags          = AT24_FLAG_ADDR16,
	.setup          = davinci_get_mac_addr,
	.context	= (void *)0x7f00,
};

static struct snd_platform_data dm365_evm_snd_data;

static struct i2c_board_info i2c_info[] = {
	{
		I2C_BOARD_INFO("24c256", 0x50),
		.platform_data	= &eeprom_info,
	},
	{
		I2C_BOARD_INFO("tlv320aic3x", 0x18),
	},
};

static struct davinci_i2c_platform_data i2c_pdata = {
	.bus_freq	= 400	/* kHz */,
	.bus_delay	= 0	/* usec */,
};

static int dm365evm_keyscan_enable(struct device *dev)
{
	return davinci_cfg_reg(DM365_KEYSCAN);
}

static unsigned short dm365evm_keymap[] = {
	KEY_KP2,
	KEY_LEFT,
	KEY_EXIT,
	KEY_DOWN,
	KEY_ENTER,
	KEY_UP,
	KEY_KP1,
	KEY_RIGHT,
	KEY_MENU,
	KEY_RECORD,
	KEY_REWIND,
	KEY_KPMINUS,
	KEY_STOP,
	KEY_FASTFORWARD,
	KEY_KPPLUS,
	KEY_PLAYPAUSE,
	0
};

static struct davinci_ks_platform_data dm365evm_ks_data = {
	.device_enable	= dm365evm_keyscan_enable,
	.keymap		= dm365evm_keymap,
	.keymapsize	= ARRAY_SIZE(dm365evm_keymap),
	.rep		= 1,
	/* Scan period = strobe + interval */
	.strobe		= 0x5,
	.interval	= 0x2,
	.matrix_type	= DAVINCI_KEYSCAN_MATRIX_4X4,
};

static int cpld_mmc_get_cd(int module)
{
	if (!cpld)
		return -ENXIO;

	/* low == card present */
	return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0));
}

static int cpld_mmc_get_ro(int module)
{
	if (!cpld)
		return -ENXIO;

	/* high == card's write protect switch active */
	return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1));
}

static struct davinci_mmc_config dm365evm_mmc_config = {
	.get_cd		= cpld_mmc_get_cd,
	.get_ro		= cpld_mmc_get_ro,
	.wires		= 4,
	.max_freq	= 50000000,
	.caps		= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
	.version	= MMC_CTLR_VERSION_2,
};

static void dm365evm_emac_configure(void)
{
	/*
	 * EMAC pins are multiplexed with GPIO and UART
	 * Further details are available at the DM365 ARM
	 * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127
	 */
	davinci_cfg_reg(DM365_EMAC_TX_EN);
	davinci_cfg_reg(DM365_EMAC_TX_CLK);
	davinci_cfg_reg(DM365_EMAC_COL);
	davinci_cfg_reg(DM365_EMAC_TXD3);
	davinci_cfg_reg(DM365_EMAC_TXD2);
	davinci_cfg_reg(DM365_EMAC_TXD1);
	davinci_cfg_reg(DM365_EMAC_TXD0);
	davinci_cfg_reg(DM365_EMAC_RXD3);
	davinci_cfg_reg(DM365_EMAC_RXD2);
	davinci_cfg_reg(DM365_EMAC_RXD1);
	davinci_cfg_reg(DM365_EMAC_RXD0);
	davinci_cfg_reg(DM365_EMAC_RX_CLK);
	davinci_cfg_reg(DM365_EMAC_RX_DV);
	davinci_cfg_reg(DM365_EMAC_RX_ER);
	davinci_cfg_reg(DM365_EMAC_CRS);
	davinci_cfg_reg(DM365_EMAC_MDIO);
	davinci_cfg_reg(DM365_EMAC_MDCLK);

	/*
	 * EMAC interrupts are multiplexed with GPIO interrupts
	 * Details are available at the DM365 ARM
	 * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134
	 */
	davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH);
	davinci_cfg_reg(DM365_INT_EMAC_RXPULSE);
	davinci_cfg_reg(DM365_INT_EMAC_TXPULSE);
	davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE);
}

static void dm365evm_mmc_configure(void)
{
	/*
	 * MMC/SD pins are multiplexed with GPIO and EMIF
	 * Further details are available at the DM365 ARM
	 * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131
	 */
	davinci_cfg_reg(DM365_SD1_CLK);
	davinci_cfg_reg(DM365_SD1_CMD);
	davinci_cfg_reg(DM365_SD1_DATA3);
	davinci_cfg_reg(DM365_SD1_DATA2);
	davinci_cfg_reg(DM365_SD1_DATA1);
	davinci_cfg_reg(DM365_SD1_DATA0);
}

static struct tvp514x_platform_data tvp5146_pdata = {
	.clk_polarity = 0,
	.hs_polarity = 1,
	.vs_polarity = 1
};

#define TVP514X_STD_ALL        (V4L2_STD_NTSC | V4L2_STD_PAL)
/* Inputs available at the TVP5146 */
static struct v4l2_input tvp5146_inputs[] = {
	{
		.index = 0,
		.name = "Composite",
		.type = V4L2_INPUT_TYPE_CAMERA,
		.std = TVP514X_STD_ALL,
	},
	{
		.index = 1,
		.name = "S-Video",
		.type = V4L2_INPUT_TYPE_CAMERA,
		.std = TVP514X_STD_ALL,
	},
};

/*
 * this is the route info for connecting each input to decoder
 * ouput that goes to vpfe. There is a one to one correspondence
 * with tvp5146_inputs
 */
static struct vpfe_route tvp5146_routes[] = {
	{
		.input = INPUT_CVBS_VI2B,
		.output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
	},
{
		.input = INPUT_SVIDEO_VI2C_VI1C,
		.output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
	},
};

static struct vpfe_subdev_info vpfe_sub_devs[] = {
	{
		.name = "tvp5146",
		.grp_id = 0,
		.num_inputs = ARRAY_SIZE(tvp5146_inputs),
		.inputs = tvp5146_inputs,
		.routes = tvp5146_routes,
		.can_route = 1,
		.ccdc_if_params = {
			.if_type = VPFE_BT656,
			.hdpol = VPFE_PINPOL_POSITIVE,
			.vdpol = VPFE_PINPOL_POSITIVE,
		},
		.board_info = {
			I2C_BOARD_INFO("tvp5146", 0x5d),
			.platform_data = &tvp5146_pdata,
		},
	},
};

static struct vpfe_config vpfe_cfg = {
	.num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
	.sub_devs = vpfe_sub_devs,
	.i2c_adapter_id = 1,
	.card_name = "DM365 EVM",
	.ccdc = "ISIF",
};

static void __init evm_init_i2c(void)
{
	davinci_init_i2c(&i2c_pdata);
	i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
}

static struct platform_device *dm365_evm_nand_devices[] __initdata = {
	&davinci_nand_device,
};

static inline int have_leds(void)
{
#ifdef CONFIG_LEDS_CLASS
	return 1;
#else
	return 0;
#endif
}

struct cpld_led {
	struct led_classdev	cdev;
	u8			mask;
};

static const struct {
	const char *name;
	const char *trigger;
} cpld_leds[] = {
	{ "dm365evm::ds2", },
	{ "dm365evm::ds3", },
	{ "dm365evm::ds4", },
	{ "dm365evm::ds5", },
	{ "dm365evm::ds6", "nand-disk", },
	{ "dm365evm::ds7", "mmc1", },
	{ "dm365evm::ds8", "mmc0", },
	{ "dm365evm::ds9", "heartbeat", },
};

static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b)
{
	struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
	u8 reg = __raw_readb(cpld + CPLD_LEDS);

	if (b != LED_OFF)
		reg &= ~led->mask;
	else
		reg |= led->mask;
	__raw_writeb(reg, cpld + CPLD_LEDS);
}

static enum led_brightness cpld_led_get(struct led_classdev *cdev)
{
	struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
	u8 reg = __raw_readb(cpld + CPLD_LEDS);

	return (reg & led->mask) ? LED_OFF : LED_FULL;
}

static int __init cpld_leds_init(void)
{
	int	i;

	if (!have_leds() ||  !cpld)
		return 0;

	/* setup LEDs */
	__raw_writeb(0xff, cpld + CPLD_LEDS);
	for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) {
		struct cpld_led *led;

		led = kzalloc(sizeof(*led), GFP_KERNEL);
		if (!led)
			break;

		led->cdev.name = cpld_leds[i].name;
		led->cdev.brightness_set = cpld_led_set;
		led->cdev.brightness_get = cpld_led_get;
		led->cdev.default_trigger = cpld_leds[i].trigger;
		led->mask = BIT(i);

		if (led_classdev_register(NULL, &led->cdev) < 0) {
			kfree(led);
			break;
		}
	}

	return 0;
}
/* run after subsys_initcall() for LEDs */
fs_initcall(cpld_leds_init);


static void __init evm_init_cpld(void)
{
	u8 mux, resets;
	const char *label;
	struct clk *aemif_clk;

	/* Make sure we can configure the CPLD through CS1.  Then
	 * leave it on for later access to MMC and LED registers.
	 */
	aemif_clk = clk_get(NULL, "aemif");
	if (IS_ERR(aemif_clk))
		return;
	clk_enable(aemif_clk);

	if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
			"cpld") == NULL)
		goto fail;
	cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE);
	if (!cpld) {
		release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE,
				SECTION_SIZE);
fail:
		pr_err("ERROR: can't map CPLD\n");
		clk_disable(aemif_clk);
		return;
	}

	/* External muxing for some signals */
	mux = 0;

	/* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read).
	 * NOTE:  SW4 bus width setting must match!
	 */
	if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) {
		/* external keypad mux */
		mux |= BIT(7);

		platform_add_devices(dm365_evm_nand_devices,
				ARRAY_SIZE(dm365_evm_nand_devices));
	} else {
		/* no OneNAND support yet */
	}

	/* Leave external chips in reset when unused. */
	resets = BIT(3) | BIT(2) | BIT(1) | BIT(0);

	/* Static video input config with SN74CBT16214 1-of-3 mux:
	 *  - port b1 == tvp7002 (mux lowbits == 1 or 6)
	 *  - port b2 == imager (mux lowbits == 2 or 7)
	 *  - port b3 == tvp5146 (mux lowbits == 5)
	 *
	 * Runtime switching could work too, with limitations.
	 */
	if (have_imager()) {
		label = "HD imager";
		mux |= 1;

		/* externally mux MMC1/ENET/AIC33 to imager */
		mux |= BIT(6) | BIT(5) | BIT(3);
	} else {
		struct davinci_soc_info *soc_info = &davinci_soc_info;

		/* we can use MMC1 ... */
		dm365evm_mmc_configure();
		davinci_setup_mmc(1, &dm365evm_mmc_config);

		/* ... and ENET ... */
		dm365evm_emac_configure();
		soc_info->emac_pdata->phy_mask = DM365_EVM_PHY_MASK;
		soc_info->emac_pdata->mdio_max_freq = DM365_EVM_MDIO_FREQUENCY;
		resets &= ~BIT(3);

		/* ... and AIC33 */
		resets &= ~BIT(1);

		if (have_tvp7002()) {
			mux |= 2;
			resets &= ~BIT(2);
			label = "tvp7002 HD";
		} else {
			/* default to tvp5146 */
			mux |= 5;
			resets &= ~BIT(0);
			label = "tvp5146 SD";
		}
	}
	__raw_writeb(mux, cpld + CPLD_MUX);
	__raw_writeb(resets, cpld + CPLD_RESETS);
	pr_info("EVM: %s video input\n", label);

	/* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */
}

static struct davinci_uart_config uart_config __initdata = {
	.enabled_uarts = (1 << 0),
};

static void __init dm365_evm_map_io(void)
{
	/* setup input configuration for VPFE input devices */
	dm365_set_vpfe_config(&vpfe_cfg);
	dm365_init();
}

static struct spi_eeprom at25640 = {
	.byte_len	= SZ_64K / 8,
	.name		= "at25640",
	.page_size	= 32,
	.flags		= EE_ADDR2,
};

static struct spi_board_info dm365_evm_spi_info[] __initconst = {
	{
		.modalias	= "at25",
		.platform_data	= &at25640,
		.max_speed_hz	= 10 * 1000 * 1000,
		.bus_num	= 0,
		.chip_select	= 0,
		.mode		= SPI_MODE_0,
	},
};

static __init void dm365_evm_init(void)
{
	evm_init_i2c();
	davinci_serial_init(&uart_config);

	dm365evm_emac_configure();
	dm365evm_mmc_configure();

	davinci_setup_mmc(0, &dm365evm_mmc_config);

	/* maybe setup mmc1/etc ... _after_ mmc0 */
	evm_init_cpld();

	dm365_init_asp(&dm365_evm_snd_data);
	dm365_init_rtc();
	dm365_init_ks(&dm365evm_ks_data);

	dm365_init_spi0(BIT(0), dm365_evm_spi_info,
			ARRAY_SIZE(dm365_evm_spi_info));
}

static __init void dm365_evm_irq_init(void)
{
	davinci_irq_init();
}

MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
	.phys_io	= IO_PHYS,
	.io_pg_offst	= (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
	.boot_params	= (0x80000100),
	.map_io		= dm365_evm_map_io,
	.init_irq	= dm365_evm_irq_init,
	.timer		= &davinci_timer,
	.init_machine	= dm365_evm_init,
MACHINE_END
Commit	Line	Data
37dd0095 SP	1	/*
	2	* TI DaVinci DM365 EVM board support
	3	*
	4	* Copyright (C) 2009 Texas Instruments Incorporated
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation version 2.
	9	*
	10	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	11	* kind, whether express or implied; without even the implied warranty
	12	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15	#include <linux/kernel.h>
37dd0095	16	#include <linux/init.h>
42d399e4	17	#include <linux/err.h>
37dd0095 SP	18	#include <linux/i2c.h>
	19	#include <linux/io.h>
	20	#include <linux/clk.h>
8ed0a9d4	21	#include <linux/i2c/at24.h>
ff255c6c	22	#include <linux/leds.h>
37b798da SP	23	#include <linux/mtd/mtd.h>
37b798da SP	24	#include <linux/mtd/partitions.h>
5a0e3ad6	25	#include <linux/slab.h>
37b798da	26	#include <linux/mtd/nand.h>
990c09d5	27	#include <linux/input.h>
5f19daa1 SP	28	#include <linux/spi/spi.h>
5f19daa1 SP	29	#include <linux/spi/eeprom.h>
42d399e4	30
37dd0095 SP	31	#include <asm/mach-types.h>
37dd0095 SP	32	#include <asm/mach/arch.h>
42d399e4	33
8ed0a9d4	34	#include <mach/mux.h>
37dd0095	35	#include <mach/dm365.h>
37dd0095 SP	36	#include <mach/common.h>
37dd0095 SP	37	#include <mach/i2c.h>
37dd0095	38	#include <mach/serial.h>
a45c8ba3	39	#include <mach/mmc.h>
37b798da	40	#include <mach/nand.h>
990c09d5	41	#include <mach/keyscan.h>
37b798da	42
f2a4c59d MK	43	#include <media/tvp514x.h>
f2a4c59d MK	44
ff255c6c DB	45	static inline int have_imager(void)
	46	{
	47	/* REVISIT when it's supported, trigger via Kconfig */
	48	return 0;
	49	}
	50
	51	static inline int have_tvp7002(void)
	52	{
	53	/* REVISIT when it's supported, trigger via Kconfig */
	54	return 0;
	55	}
	56
8ed0a9d4 SP	57	#define DM365_EVM_PHY_MASK (0x2)
	58	#define DM365_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
	59
ff255c6c DB	60	/*
	61	* A MAX-II CPLD is used for various board control functions.
	62	*/
	63	#define CPLD_OFFSET(a13a8,a2a1) (((a13a8) << 10) + ((a2a1) << 3))
	64
	65	#define CPLD_VERSION CPLD_OFFSET(0,0) /* r/o */
	66	#define CPLD_TEST CPLD_OFFSET(0,1)
	67	#define CPLD_LEDS CPLD_OFFSET(0,2)
	68	#define CPLD_MUX CPLD_OFFSET(0,3)
	69	#define CPLD_SWITCH CPLD_OFFSET(1,0) /* r/o */
	70	#define CPLD_POWER CPLD_OFFSET(1,1)
	71	#define CPLD_VIDEO CPLD_OFFSET(1,2)
	72	#define CPLD_CARDSTAT CPLD_OFFSET(1,3) /* r/o */
	73
	74	#define CPLD_DILC_OUT CPLD_OFFSET(2,0)
	75	#define CPLD_DILC_IN CPLD_OFFSET(2,1) /* r/o */
	76
	77	#define CPLD_IMG_DIR0 CPLD_OFFSET(2,2)
	78	#define CPLD_IMG_MUX0 CPLD_OFFSET(2,3)
	79	#define CPLD_IMG_MUX1 CPLD_OFFSET(3,0)
	80	#define CPLD_IMG_DIR1 CPLD_OFFSET(3,1)
	81	#define CPLD_IMG_MUX2 CPLD_OFFSET(3,2)
	82	#define CPLD_IMG_MUX3 CPLD_OFFSET(3,3)
	83	#define CPLD_IMG_DIR2 CPLD_OFFSET(4,0)
	84	#define CPLD_IMG_MUX4 CPLD_OFFSET(4,1)
	85	#define CPLD_IMG_MUX5 CPLD_OFFSET(4,2)
	86
	87	#define CPLD_RESETS CPLD_OFFSET(4,3)
	88
	89	#define CPLD_CCD_DIR1 CPLD_OFFSET(0x3e,0)
	90	#define CPLD_CCD_IO1 CPLD_OFFSET(0x3e,1)
	91	#define CPLD_CCD_DIR2 CPLD_OFFSET(0x3e,2)
	92	#define CPLD_CCD_IO2 CPLD_OFFSET(0x3e,3)
	93	#define CPLD_CCD_DIR3 CPLD_OFFSET(0x3f,0)
	94	#define CPLD_CCD_IO3 CPLD_OFFSET(0x3f,1)
	95
	96	static void __iomem *cpld;
	97
	98
37b798da SP	99	/* NOTE: this is geared for the standard config, with a socketed
	100	* 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
	101	* swap chips with a different block size, partitioning will
	102	* need to be changed. This NAND chip MT29F16G08FAA is the default
	103	* NAND shipped with the Spectrum Digital DM365 EVM
	104	*/
	105	#define NAND_BLOCK_SIZE SZ_128K
	106
	107	static struct mtd_partition davinci_nand_partitions[] = {
	108	{
	109	/* UBL (a few copies) plus U-Boot */
	110	.name = "bootloader",
	111	.offset = 0,
	112	.size = 28 * NAND_BLOCK_SIZE,
	113	.mask_flags = MTD_WRITEABLE, /* force read-only */
	114	}, {
	115	/* U-Boot environment */
	116	.name = "params",
	117	.offset = MTDPART_OFS_APPEND,
	118	.size = 2 * NAND_BLOCK_SIZE,
	119	.mask_flags = 0,
	120	}, {
	121	.name = "kernel",
	122	.offset = MTDPART_OFS_APPEND,
	123	.size = SZ_4M,
	124	.mask_flags = 0,
	125	}, {
	126	.name = "filesystem1",
	127	.offset = MTDPART_OFS_APPEND,
	128	.size = SZ_512M,
	129	.mask_flags = 0,
	130	}, {
	131	.name = "filesystem2",
	132	.offset = MTDPART_OFS_APPEND,
	133	.size = MTDPART_SIZ_FULL,
	134	.mask_flags = 0,
	135	}
	136	/* two blocks with bad block table (and mirror) at the end */
	137	};
	138
	139	static struct davinci_nand_pdata davinci_nand_data = {
	140	.mask_chipsel = BIT(14),
	141	.parts = davinci_nand_partitions,
	142	.nr_parts = ARRAY_SIZE(davinci_nand_partitions),
	143	.ecc_mode = NAND_ECC_HW,
	144	.options = NAND_USE_FLASH_BBT,
dc4c05a5	145	.ecc_bits = 4,
37b798da SP	146	};
	147
	148	static struct resource davinci_nand_resources[] = {
	149	{
	150	.start = DM365_ASYNC_EMIF_DATA_CE0_BASE,
	151	.end = DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
	152	.flags = IORESOURCE_MEM,
	153	}, {
	154	.start = DM365_ASYNC_EMIF_CONTROL_BASE,
	155	.end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
	156	.flags = IORESOURCE_MEM,
	157	},
	158	};
	159
	160	static struct platform_device davinci_nand_device = {
	161	.name = "davinci_nand",
	162	.id = 0,
	163	.num_resources = ARRAY_SIZE(davinci_nand_resources),
	164	.resource = davinci_nand_resources,
	165	.dev = {
	166	.platform_data = &davinci_nand_data,
	167	},
	168	};
	169
8ed0a9d4 SP	170	static struct at24_platform_data eeprom_info = {
	171	.byte_len = (256*1024) / 8,
	172	.page_size = 64,
	173	.flags = AT24_FLAG_ADDR16,
	174	.setup = davinci_get_mac_addr,
	175	.context = (void *)0x7f00,
	176	};
	177
e9ab3214 MA	178	static struct snd_platform_data dm365_evm_snd_data;
e9ab3214 MA	179
8ed0a9d4 SP	180	static struct i2c_board_info i2c_info[] = {
	181	{
	182	I2C_BOARD_INFO("24c256", 0x50),
	183	.platform_data = &eeprom_info,
	184	},
e9ab3214 MA	185	{
	186	I2C_BOARD_INFO("tlv320aic3x", 0x18),
	187	},
8ed0a9d4 SP	188	};
8ed0a9d4 SP	189
37dd0095 SP	190	static struct davinci_i2c_platform_data i2c_pdata = {
	191	.bus_freq = 400 /* kHz */,
	192	.bus_delay = 0 /* usec */,
	193	};
	194
c92b29ec MA	195	static int dm365evm_keyscan_enable(struct device *dev)
	196	{
	197	return davinci_cfg_reg(DM365_KEYSCAN);
	198	}
	199
990c09d5 MA	200	static unsigned short dm365evm_keymap[] = {
	201	KEY_KP2,
	202	KEY_LEFT,
	203	KEY_EXIT,
	204	KEY_DOWN,
	205	KEY_ENTER,
	206	KEY_UP,
	207	KEY_KP1,
	208	KEY_RIGHT,
	209	KEY_MENU,
	210	KEY_RECORD,
	211	KEY_REWIND,
	212	KEY_KPMINUS,
	213	KEY_STOP,
	214	KEY_FASTFORWARD,
	215	KEY_KPPLUS,
	216	KEY_PLAYPAUSE,
	217	0
	218	};
	219
	220	static struct davinci_ks_platform_data dm365evm_ks_data = {
c92b29ec	221	.device_enable = dm365evm_keyscan_enable,
990c09d5 MA	222	.keymap = dm365evm_keymap,
	223	.keymapsize = ARRAY_SIZE(dm365evm_keymap),
	224	.rep = 1,
	225	/* Scan period = strobe + interval */
	226	.strobe = 0x5,
	227	.interval = 0x2,
	228	.matrix_type = DAVINCI_KEYSCAN_MATRIX_4X4,
	229	};
990c09d5	230
ff255c6c DB	231	static int cpld_mmc_get_cd(int module)
	232	{
	233	if (!cpld)
	234	return -ENXIO;
	235
	236	/* low == card present */
	237	return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0));
	238	}
	239
	240	static int cpld_mmc_get_ro(int module)
	241	{
	242	if (!cpld)
	243	return -ENXIO;
	244
	245	/* high == card's write protect switch active */
	246	return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1));
	247	}
	248
a45c8ba3	249	static struct davinci_mmc_config dm365evm_mmc_config = {
ff255c6c DB	250	.get_cd = cpld_mmc_get_cd,
ff255c6c DB	251	.get_ro = cpld_mmc_get_ro,
a45c8ba3 SP	252	.wires = 4,
	253	.max_freq = 50000000,
	254	.caps = MMC_CAP_MMC_HIGHSPEED \| MMC_CAP_SD_HIGHSPEED,
	255	.version = MMC_CTLR_VERSION_2,
	256	};
	257
8ed0a9d4 SP	258	static void dm365evm_emac_configure(void)
	259	{
	260	/*
	261	* EMAC pins are multiplexed with GPIO and UART
	262	* Further details are available at the DM365 ARM
	263	* Subsystem Users Guide(sprufg5.pdf) pages 125 - 127
	264	*/
	265	davinci_cfg_reg(DM365_EMAC_TX_EN);
	266	davinci_cfg_reg(DM365_EMAC_TX_CLK);
	267	davinci_cfg_reg(DM365_EMAC_COL);
	268	davinci_cfg_reg(DM365_EMAC_TXD3);
	269	davinci_cfg_reg(DM365_EMAC_TXD2);
	270	davinci_cfg_reg(DM365_EMAC_TXD1);
	271	davinci_cfg_reg(DM365_EMAC_TXD0);
	272	davinci_cfg_reg(DM365_EMAC_RXD3);
	273	davinci_cfg_reg(DM365_EMAC_RXD2);
	274	davinci_cfg_reg(DM365_EMAC_RXD1);
	275	davinci_cfg_reg(DM365_EMAC_RXD0);
	276	davinci_cfg_reg(DM365_EMAC_RX_CLK);
	277	davinci_cfg_reg(DM365_EMAC_RX_DV);
	278	davinci_cfg_reg(DM365_EMAC_RX_ER);
	279	davinci_cfg_reg(DM365_EMAC_CRS);
	280	davinci_cfg_reg(DM365_EMAC_MDIO);
	281	davinci_cfg_reg(DM365_EMAC_MDCLK);
	282
	283	/*
	284	* EMAC interrupts are multiplexed with GPIO interrupts
	285	* Details are available at the DM365 ARM
	286	* Subsystem Users Guide(sprufg5.pdf) pages 133 - 134
	287	*/
	288	davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH);
	289	davinci_cfg_reg(DM365_INT_EMAC_RXPULSE);
	290	davinci_cfg_reg(DM365_INT_EMAC_TXPULSE);
	291	davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE);
	292	}
	293
a45c8ba3 SP	294	static void dm365evm_mmc_configure(void)
	295	{
	296	/*
	297	* MMC/SD pins are multiplexed with GPIO and EMIF
	298	* Further details are available at the DM365 ARM
	299	* Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131
	300	*/
	301	davinci_cfg_reg(DM365_SD1_CLK);
	302	davinci_cfg_reg(DM365_SD1_CMD);
	303	davinci_cfg_reg(DM365_SD1_DATA3);
	304	davinci_cfg_reg(DM365_SD1_DATA2);
	305	davinci_cfg_reg(DM365_SD1_DATA1);
	306	davinci_cfg_reg(DM365_SD1_DATA0);
	307	}
	308
f2a4c59d MK	309	static struct tvp514x_platform_data tvp5146_pdata = {
	310	.clk_polarity = 0,
	311	.hs_polarity = 1,
	312	.vs_polarity = 1
	313	};
	314
	315	#define TVP514X_STD_ALL (V4L2_STD_NTSC \| V4L2_STD_PAL)
	316	/* Inputs available at the TVP5146 */
	317	static struct v4l2_input tvp5146_inputs[] = {
	318	{
	319	.index = 0,
	320	.name = "Composite",
	321	.type = V4L2_INPUT_TYPE_CAMERA,
	322	.std = TVP514X_STD_ALL,
	323	},
	324	{
	325	.index = 1,
	326	.name = "S-Video",
	327	.type = V4L2_INPUT_TYPE_CAMERA,
	328	.std = TVP514X_STD_ALL,
	329	},
	330	};
	331
	332	/*
	333	* this is the route info for connecting each input to decoder
	334	* ouput that goes to vpfe. There is a one to one correspondence
	335	* with tvp5146_inputs
	336	*/
	337	static struct vpfe_route tvp5146_routes[] = {
	338	{
	339	.input = INPUT_CVBS_VI2B,
	340	.output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
	341	},
	342	{
	343	.input = INPUT_SVIDEO_VI2C_VI1C,
	344	.output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
	345	},
	346	};
	347
	348	static struct vpfe_subdev_info vpfe_sub_devs[] = {
	349	{
	350	.name = "tvp5146",
	351	.grp_id = 0,
	352	.num_inputs = ARRAY_SIZE(tvp5146_inputs),
	353	.inputs = tvp5146_inputs,
	354	.routes = tvp5146_routes,
	355	.can_route = 1,
	356	.ccdc_if_params = {
	357	.if_type = VPFE_BT656,
	358	.hdpol = VPFE_PINPOL_POSITIVE,
	359	.vdpol = VPFE_PINPOL_POSITIVE,
	360	},
	361	.board_info = {
	362	I2C_BOARD_INFO("tvp5146", 0x5d),
	363	.platform_data = &tvp5146_pdata,
	364	},
	365	},
	366	};
	367
	368	static struct vpfe_config vpfe_cfg = {
	369	.num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
	370	.sub_devs = vpfe_sub_devs,
	371	.i2c_adapter_id = 1,
	372	.card_name = "DM365 EVM",
373	.ccdc = "ISIF",
374	};
375
37dd0095 SP	376	static void __init evm_init_i2c(void)
	377	{
	378	davinci_init_i2c(&i2c_pdata);
8ed0a9d4	379	i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
37dd0095 SP	380	}
37dd0095 SP	381
ff255c6c	382	static struct platform_device *dm365_evm_nand_devices[] __initdata = {
37b798da SP	383	&davinci_nand_device,
	384	};
	385
ff255c6c DB	386	static inline int have_leds(void)
	387	{
	388	#ifdef CONFIG_LEDS_CLASS
	389	return 1;
	390	#else
	391	return 0;
	392	#endif
	393	}
	394
	395	struct cpld_led {
	396	struct led_classdev cdev;
	397	u8 mask;
	398	};
	399
	400	static const struct {
	401	const char *name;
	402	const char *trigger;
	403	} cpld_leds[] = {
	404	{ "dm365evm::ds2", },
	405	{ "dm365evm::ds3", },
	406	{ "dm365evm::ds4", },
	407	{ "dm365evm::ds5", },
	408	{ "dm365evm::ds6", "nand-disk", },
	409	{ "dm365evm::ds7", "mmc1", },
	410	{ "dm365evm::ds8", "mmc0", },
	411	{ "dm365evm::ds9", "heartbeat", },
	412	};
	413
	414	static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b)
	415	{
	416	struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
	417	u8 reg = __raw_readb(cpld + CPLD_LEDS);
	418
	419	if (b != LED_OFF)
	420	reg &= ~led->mask;
	421	else
	422	reg \|= led->mask;
	423	__raw_writeb(reg, cpld + CPLD_LEDS);
	424	}
	425
	426	static enum led_brightness cpld_led_get(struct led_classdev *cdev)
	427	{
	428	struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
	429	u8 reg = __raw_readb(cpld + CPLD_LEDS);
	430
	431	return (reg & led->mask) ? LED_OFF : LED_FULL;
	432	}
	433
	434	static int __init cpld_leds_init(void)
	435	{
	436	int i;
	437
	438	if (!have_leds() \|\| !cpld)
	439	return 0;
	440
	441	/* setup LEDs */
	442	__raw_writeb(0xff, cpld + CPLD_LEDS);
	443	for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) {
	444	struct cpld_led *led;
	445
	446	led = kzalloc(sizeof(*led), GFP_KERNEL);
	447	if (!led)
	448	break;
	449
450	led->cdev.name = cpld_leds[i].name;
451	led->cdev.brightness_set = cpld_led_set;
452	led->cdev.brightness_get = cpld_led_get;
453	led->cdev.default_trigger = cpld_leds[i].trigger;
454	led->mask = BIT(i);
455
456	if (led_classdev_register(NULL, &led->cdev) < 0) {
457	kfree(led);
458	break;
459	}
460	}
461
462	return 0;
463	}
464	/* run after subsys_initcall() for LEDs */
465	fs_initcall(cpld_leds_init);
466
467
468	static void __init evm_init_cpld(void)
469	{
470	u8 mux, resets;
471	const char *label;
472	struct clk *aemif_clk;
473
474	/* Make sure we can configure the CPLD through CS1. Then
475	* leave it on for later access to MMC and LED registers.
476	*/
477	aemif_clk = clk_get(NULL, "aemif");
478	if (IS_ERR(aemif_clk))
479	return;
480	clk_enable(aemif_clk);
481
482	if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
483	"cpld") == NULL)
484	goto fail;
485	cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE);
486	if (!cpld) {
487	release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE,
488	SECTION_SIZE);
489	fail:
490	pr_err("ERROR: can't map CPLD\n");
491	clk_disable(aemif_clk);
492	return;
493	}
494
495	/* External muxing for some signals */
496	mux = 0;
497
498	/* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read).
499	* NOTE: SW4 bus width setting must match!
500	*/
501	if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) {
502	/* external keypad mux */
503	mux \|= BIT(7);
504
505	platform_add_devices(dm365_evm_nand_devices,
506	ARRAY_SIZE(dm365_evm_nand_devices));
507	} else {
508	/* no OneNAND support yet */
509	}
510
511	/* Leave external chips in reset when unused. */
512	resets = BIT(3) \| BIT(2) \| BIT(1) \| BIT(0);
513
514	/* Static video input config with SN74CBT16214 1-of-3 mux:
515	* - port b1 == tvp7002 (mux lowbits == 1 or 6)
516	* - port b2 == imager (mux lowbits == 2 or 7)
517	* - port b3 == tvp5146 (mux lowbits == 5)
518	*
519	* Runtime switching could work too, with limitations.
520	*/
521	if (have_imager()) {
522	label = "HD imager";
523	mux \|= 1;
524
525	/* externally mux MMC1/ENET/AIC33 to imager */
526	mux \|= BIT(6) \| BIT(5) \| BIT(3);
527	} else {
528	struct davinci_soc_info *soc_info = &davinci_soc_info;
529
530	/* we can use MMC1 ... */
531	dm365evm_mmc_configure();
532	davinci_setup_mmc(1, &dm365evm_mmc_config);
533
534	/* ... and ENET ... */
535	dm365evm_emac_configure();
536	soc_info->emac_pdata->phy_mask = DM365_EVM_PHY_MASK;
537	soc_info->emac_pdata->mdio_max_freq = DM365_EVM_MDIO_FREQUENCY;
538	resets &= ~BIT(3);
539
540	/* ... and AIC33 */
541	resets &= ~BIT(1);
542
543	if (have_tvp7002()) {
544	mux \|= 2;
545	resets &= ~BIT(2);
546	label = "tvp7002 HD";
547	} else {
548	/* default to tvp5146 */
549	mux \|= 5;
550	resets &= ~BIT(0);
551	label = "tvp5146 SD";
552	}
553	}
554	__raw_writeb(mux, cpld + CPLD_MUX);
555	__raw_writeb(resets, cpld + CPLD_RESETS);
556	pr_info("EVM: %s video input\n", label);
557
558	/* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */
559	}
560
37dd0095 SP	561	static struct davinci_uart_config uart_config __initdata = {
	562	.enabled_uarts = (1 << 0),
	563	};
	564
	565	static void __init dm365_evm_map_io(void)
	566	{
f2a4c59d MK	567	/* setup input configuration for VPFE input devices */
f2a4c59d MK	568	dm365_set_vpfe_config(&vpfe_cfg);
37dd0095 SP	569	dm365_init();
	570	}
	571
5f19daa1 SP	572	static struct spi_eeprom at25640 = {
	573	.byte_len = SZ_64K / 8,
	574	.name = "at25640",
	575	.page_size = 32,
	576	.flags = EE_ADDR2,
	577	};
	578
	579	static struct spi_board_info dm365_evm_spi_info[] __initconst = {
	580	{
	581	.modalias = "at25",
	582	.platform_data = &at25640,
	583	.max_speed_hz = 10 * 1000 * 1000,
	584	.bus_num = 0,
	585	.chip_select = 0,
	586	.mode = SPI_MODE_0,
	587	},
	588	};
	589
37dd0095 SP	590	static __init void dm365_evm_init(void)
	591	{
	592	evm_init_i2c();
	593	davinci_serial_init(&uart_config);
8ed0a9d4 SP	594
8ed0a9d4 SP	595	dm365evm_emac_configure();
a45c8ba3 SP	596	dm365evm_mmc_configure();
	597
	598	davinci_setup_mmc(0, &dm365evm_mmc_config);
8ed0a9d4	599
ff255c6c DB	600	/* maybe setup mmc1/etc ... _after_ mmc0 */
ff255c6c DB	601	evm_init_cpld();
e9ab3214 MA	602
e9ab3214 MA	603	dm365_init_asp(&dm365_evm_snd_data);
99381b4f	604	dm365_init_rtc();
990c09d5	605	dm365_init_ks(&dm365evm_ks_data);
5f19daa1 SP	606
	607	dm365_init_spi0(BIT(0), dm365_evm_spi_info,
	608	ARRAY_SIZE(dm365_evm_spi_info));
37dd0095 SP	609	}
	610
	611	static __init void dm365_evm_irq_init(void)
	612	{
	613	davinci_irq_init();
	614	}
	615
	616	MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
	617	.phys_io = IO_PHYS,
	618	.io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
	619	.boot_params = (0x80000100),
	620	.map_io = dm365_evm_map_io,
	621	.init_irq = dm365_evm_irq_init,
	622	.timer = &davinci_timer,
	623	.init_machine = dm365_evm_init,
	624	MACHINE_END
	625