[deliverable/linux.git] / arch / arm / mach-davinci / board-mityomapl138.c

/*
 * Critical Link MityOMAP-L138 SoM
 *
 * Copyright (C) 2010 Critical Link LLC - http://www.criticallink.com
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2. This program is licensed "as is" without any warranty of
 * any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/console.h>
#include <linux/platform_device.h>
#include <linux/mtd/partitions.h>
#include <linux/regulator/machine.h>
#include <linux/i2c.h>
#include <linux/i2c/at24.h>
#include <linux/etherdevice.h>

#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/common.h>
#include <mach/cp_intc.h>
#include <mach/da8xx.h>
#include <mach/nand.h>
#include <mach/mux.h>

#define MITYOMAPL138_PHY_ID		"0:03"

#define FACTORY_CONFIG_MAGIC	0x012C0138
#define FACTORY_CONFIG_VERSION	0x00010001

/* Data Held in On-Board I2C device */
struct factory_config {
	u32	magic;
	u32	version;
	u8	mac[6];
	u32	fpga_type;
	u32	spare;
	u32	serialnumber;
	char	partnum[32];
};

static struct factory_config factory_config;

static void read_factory_config(struct memory_accessor *a, void *context)
{
	int ret;
	struct davinci_soc_info *soc_info = &davinci_soc_info;

	ret = a->read(a, (char *)&factory_config, 0, sizeof(factory_config));
	if (ret != sizeof(struct factory_config)) {
		pr_warning("MityOMAPL138: Read Factory Config Failed: %d\n",
				ret);
		return;
	}

	if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
		pr_warning("MityOMAPL138: Factory Config Magic Wrong (%X)\n",
				factory_config.magic);
		return;
	}

	if (factory_config.version != FACTORY_CONFIG_VERSION) {
		pr_warning("MityOMAPL138: Factory Config Version Wrong (%X)\n",
				factory_config.version);
		return;
	}

	pr_info("MityOMAPL138: Found MAC = %pM\n", factory_config.mac);
	pr_info("MityOMAPL138: Part Number = %s\n", factory_config.partnum);
	if (is_valid_ether_addr(factory_config.mac))
		memcpy(soc_info->emac_pdata->mac_addr,
			factory_config.mac, ETH_ALEN);
	else
		pr_warning("MityOMAPL138: Invalid MAC found "
				"in factory config block\n");
}

static struct at24_platform_data mityomapl138_fd_chip = {
	.byte_len	= 256,
	.page_size	= 8,
	.flags		= AT24_FLAG_READONLY | AT24_FLAG_IRUGO,
	.setup		= read_factory_config,
	.context	= NULL,
};

static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = {
	.bus_freq	= 100,	/* kHz */
	.bus_delay	= 0,	/* usec */
};

/* TPS65023 voltage regulator support */
/* 1.2V Core */
static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = {
	{
		.supply = "cvdd",
	},
};

/* 1.8V */
static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = {
	{
		.supply = "usb0_vdda18",
	},
	{
		.supply = "usb1_vdda18",
	},
	{
		.supply = "ddr_dvdd18",
	},
	{
		.supply = "sata_vddr",
	},
};

/* 1.2V */
static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = {
	{
		.supply = "sata_vdd",
	},
	{
		.supply = "usb_cvdd",
	},
	{
		.supply = "pll0_vdda",
	},
	{
		.supply = "pll1_vdda",
	},
};

/* 1.8V Aux LDO, not used */
static struct regulator_consumer_supply tps65023_ldo1_consumers[] = {
	{
		.supply = "1.8v_aux",
	},
};

/* FPGA VCC Aux (2.5 or 3.3) LDO */
static struct regulator_consumer_supply tps65023_ldo2_consumers[] = {
	{
		.supply = "vccaux",
	},
};

static struct regulator_init_data tps65023_regulator_data[] = {
	/* dcdc1 */
	{
		.constraints = {
			.min_uV = 1150000,
			.max_uV = 1350000,
			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
					  REGULATOR_CHANGE_STATUS,
			.boot_on = 1,
		},
		.num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers),
		.consumer_supplies = tps65023_dcdc1_consumers,
	},
	/* dcdc2 */
	{
		.constraints = {
			.min_uV = 1800000,
			.max_uV = 1800000,
			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
			.boot_on = 1,
		},
		.num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers),
		.consumer_supplies = tps65023_dcdc2_consumers,
	},
	/* dcdc3 */
	{
		.constraints = {
			.min_uV = 1200000,
			.max_uV = 1200000,
			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
			.boot_on = 1,
		},
		.num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers),
		.consumer_supplies = tps65023_dcdc3_consumers,
	},
	/* ldo1 */
	{
		.constraints = {
			.min_uV = 1800000,
			.max_uV = 1800000,
			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
			.boot_on = 1,
		},
		.num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers),
		.consumer_supplies = tps65023_ldo1_consumers,
	},
	/* ldo2 */
	{
		.constraints = {
			.min_uV = 2500000,
			.max_uV = 3300000,
			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
					  REGULATOR_CHANGE_STATUS,
			.boot_on = 1,
		},
		.num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers),
		.consumer_supplies = tps65023_ldo2_consumers,
	},
};

static struct i2c_board_info __initdata mityomap_tps65023_info[] = {
	{
		I2C_BOARD_INFO("tps65023", 0x48),
		.platform_data = &tps65023_regulator_data[0],
	},
	{
		I2C_BOARD_INFO("24c02", 0x50),
		.platform_data = &mityomapl138_fd_chip,
	},
};

static int __init pmic_tps65023_init(void)
{
	return i2c_register_board_info(1, mityomap_tps65023_info,
					ARRAY_SIZE(mityomap_tps65023_info));
}

/*
 * MityDSP-L138 includes a 256 MByte large-page NAND flash
 * (128K blocks).
 */
static struct mtd_partition mityomapl138_nandflash_partition[] = {
	{
		.name		= "rootfs",
		.offset		= 0,
		.size		= SZ_128M,
		.mask_flags	= 0, /* MTD_WRITEABLE, */
	},
	{
		.name		= "homefs",
		.offset		= MTDPART_OFS_APPEND,
		.size		= MTDPART_SIZ_FULL,
		.mask_flags	= 0,
	},
};

static struct davinci_nand_pdata mityomapl138_nandflash_data = {
	.parts		= mityomapl138_nandflash_partition,
	.nr_parts	= ARRAY_SIZE(mityomapl138_nandflash_partition),
	.ecc_mode	= NAND_ECC_HW,
	.options	= NAND_USE_FLASH_BBT | NAND_BUSWIDTH_16,
	.ecc_bits	= 1, /* 4 bit mode is not supported with 16 bit NAND */
};

static struct resource mityomapl138_nandflash_resource[] = {
	{
		.start	= DA8XX_AEMIF_CS3_BASE,
		.end	= DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= DA8XX_AEMIF_CTL_BASE,
		.end	= DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
		.flags	= IORESOURCE_MEM,
	},
};

static struct platform_device mityomapl138_nandflash_device = {
	.name		= "davinci_nand",
	.id		= 0,
	.dev		= {
		.platform_data	= &mityomapl138_nandflash_data,
	},
	.num_resources	= ARRAY_SIZE(mityomapl138_nandflash_resource),
	.resource	= mityomapl138_nandflash_resource,
};

static struct platform_device *mityomapl138_devices[] __initdata = {
	&mityomapl138_nandflash_device,
};

static void __init mityomapl138_setup_nand(void)
{
	platform_add_devices(mityomapl138_devices,
				 ARRAY_SIZE(mityomapl138_devices));
}

static struct davinci_uart_config mityomapl138_uart_config __initdata = {
	.enabled_uarts = 0x7,
};

static const short mityomap_mii_pins[] = {
	DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
	DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
	DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
	DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
	DA850_MDIO_D,
	-1
};

static const short mityomap_rmii_pins[] = {
	DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
	DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
	DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
	DA850_MDIO_D,
	-1
};

static void __init mityomapl138_config_emac(void)
{
	void __iomem *cfg_chip3_base;
	int ret;
	u32 val;
	struct davinci_soc_info *soc_info = &davinci_soc_info;

	soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */

	cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
	val = __raw_readl(cfg_chip3_base);

	if (soc_info->emac_pdata->rmii_en) {
		val |= BIT(8);
		ret = davinci_cfg_reg_list(mityomap_rmii_pins);
		pr_info("RMII PHY configured\n");
	} else {
		val &= ~BIT(8);
		ret = davinci_cfg_reg_list(mityomap_mii_pins);
		pr_info("MII PHY configured\n");
	}

	if (ret) {
		pr_warning("mii/rmii mux setup failed: %d\n", ret);
		return;
	}

	/* configure the CFGCHIP3 register for RMII or MII */
	__raw_writel(val, cfg_chip3_base);

	soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID;

	ret = da8xx_register_emac();
	if (ret)
		pr_warning("emac registration failed: %d\n", ret);
}

static struct davinci_pm_config da850_pm_pdata = {
	.sleepcount = 128,
};

static struct platform_device da850_pm_device = {
	.name	= "pm-davinci",
	.dev = {
		.platform_data  = &da850_pm_pdata,
	},
	.id	= -1,
};

static void __init mityomapl138_init(void)
{
	int ret;

	/* for now, no special EDMA channels are reserved */
	ret = da850_register_edma(NULL);
	if (ret)
		pr_warning("edma registration failed: %d\n", ret);

	ret = da8xx_register_watchdog();
	if (ret)
		pr_warning("watchdog registration failed: %d\n", ret);

	davinci_serial_init(&mityomapl138_uart_config);

	ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
	if (ret)
		pr_warning("i2c0 registration failed: %d\n", ret);

	ret = pmic_tps65023_init();
	if (ret)
		pr_warning("TPS65023 PMIC init failed: %d\n", ret);

	mityomapl138_setup_nand();

	mityomapl138_config_emac();

	ret = da8xx_register_rtc();
	if (ret)
		pr_warning("rtc setup failed: %d\n", ret);

	ret = da850_register_cpufreq("pll0_sysclk3");
	if (ret)
		pr_warning("cpufreq registration failed: %d\n", ret);

	ret = da8xx_register_cpuidle();
	if (ret)
		pr_warning("cpuidle registration failed: %d\n", ret);

	ret = da850_register_pm(&da850_pm_device);
	if (ret)
		pr_warning("da850_evm_init: suspend registration failed: %d\n",
				ret);
}

#ifdef CONFIG_SERIAL_8250_CONSOLE
static int __init mityomapl138_console_init(void)
{
	if (!machine_is_mityomapl138())
		return 0;

	return add_preferred_console("ttyS", 1, "115200");
}
console_initcall(mityomapl138_console_init);
#endif

static void __init mityomapl138_map_io(void)
{
	da850_init();
}

MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
	.phys_io	= IO_PHYS,
	.io_pg_offst	= (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
	.boot_params	= (DA8XX_DDR_BASE + 0x100),
	.map_io		= mityomapl138_map_io,
	.init_irq	= cp_intc_init,
	.timer		= &davinci_timer,
	.init_machine	= mityomapl138_init,
MACHINE_END
Commit	Line	Data
f2dbb6d9 MW	1	/*
	2	* Critical Link MityOMAP-L138 SoM
	3	*
	4	* Copyright (C) 2010 Critical Link LLC - http://www.criticallink.com
	5	*
	6	* This file is licensed under the terms of the GNU General Public License
	7	* version 2. This program is licensed "as is" without any warranty of
	8	* any kind, whether express or implied.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/console.h>
	14	#include <linux/platform_device.h>
	15	#include <linux/mtd/partitions.h>
87748823 MW	16	#include <linux/regulator/machine.h>
87748823 MW	17	#include <linux/i2c.h>
2a7dae04 MW	18	#include <linux/i2c/at24.h>
2a7dae04 MW	19	#include <linux/etherdevice.h>
f2dbb6d9 MW	20
	21	#include <asm/mach-types.h>
	22	#include <asm/mach/arch.h>
	23	#include <mach/common.h>
	24	#include <mach/cp_intc.h>
	25	#include <mach/da8xx.h>
	26	#include <mach/nand.h>
	27	#include <mach/mux.h>
	28
782f2d78	29	#define MITYOMAPL138_PHY_ID "0:03"
2a7dae04 MW	30
	31	#define FACTORY_CONFIG_MAGIC 0x012C0138
	32	#define FACTORY_CONFIG_VERSION 0x00010001
	33
	34	/* Data Held in On-Board I2C device */
	35	struct factory_config {
	36	u32 magic;
	37	u32 version;
	38	u8 mac[6];
	39	u32 fpga_type;
	40	u32 spare;
	41	u32 serialnumber;
	42	char partnum[32];
	43	};
	44
	45	static struct factory_config factory_config;
	46
	47	static void read_factory_config(struct memory_accessor a, void context)
	48	{
	49	int ret;
	50	struct davinci_soc_info *soc_info = &davinci_soc_info;
	51
	52	ret = a->read(a, (char *)&factory_config, 0, sizeof(factory_config));
	53	if (ret != sizeof(struct factory_config)) {
	54	pr_warning("MityOMAPL138: Read Factory Config Failed: %d\n",
	55	ret);
	56	return;
	57	}
	58
	59	if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
	60	pr_warning("MityOMAPL138: Factory Config Magic Wrong (%X)\n",
	61	factory_config.magic);
	62	return;
	63	}
	64
	65	if (factory_config.version != FACTORY_CONFIG_VERSION) {
	66	pr_warning("MityOMAPL138: Factory Config Version Wrong (%X)\n",
	67	factory_config.version);
	68	return;
	69	}
	70
	71	pr_info("MityOMAPL138: Found MAC = %pM\n", factory_config.mac);
	72	pr_info("MityOMAPL138: Part Number = %s\n", factory_config.partnum);
	73	if (is_valid_ether_addr(factory_config.mac))
	74	memcpy(soc_info->emac_pdata->mac_addr,
	75	factory_config.mac, ETH_ALEN);
	76	else
	77	pr_warning("MityOMAPL138: Invalid MAC found "
	78	"in factory config block\n");
	79	}
	80
	81	static struct at24_platform_data mityomapl138_fd_chip = {
	82	.byte_len = 256,
	83	.page_size = 8,
	84	.flags = AT24_FLAG_READONLY \| AT24_FLAG_IRUGO,
	85	.setup = read_factory_config,
	86	.context = NULL,
	87	};
	88
87748823 MW	89	static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = {
	90	.bus_freq = 100, /* kHz */
	91	.bus_delay = 0, /* usec */
	92	};
	93
	94	/* TPS65023 voltage regulator support */
	95	/* 1.2V Core */
8939b350	96	static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = {
87748823 MW	97	{
	98	.supply = "cvdd",
	99	},
	100	};
	101
	102	/* 1.8V */
8939b350	103	static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = {
87748823 MW	104	{
	105	.supply = "usb0_vdda18",
	106	},
	107	{
	108	.supply = "usb1_vdda18",
	109	},
	110	{
	111	.supply = "ddr_dvdd18",
	112	},
	113	{
	114	.supply = "sata_vddr",
	115	},
	116	};
	117
	118	/* 1.2V */
8939b350	119	static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = {
87748823 MW	120	{
	121	.supply = "sata_vdd",
	122	},
	123	{
	124	.supply = "usb_cvdd",
	125	},
	126	{
	127	.supply = "pll0_vdda",
	128	},
	129	{
	130	.supply = "pll1_vdda",
	131	},
	132	};
	133
	134	/* 1.8V Aux LDO, not used */
8939b350	135	static struct regulator_consumer_supply tps65023_ldo1_consumers[] = {
87748823 MW	136	{
	137	.supply = "1.8v_aux",
	138	},
	139	};
	140
	141	/* FPGA VCC Aux (2.5 or 3.3) LDO */
8939b350	142	static struct regulator_consumer_supply tps65023_ldo2_consumers[] = {
87748823 MW	143	{
	144	.supply = "vccaux",
	145	},
	146	};
	147
8939b350	148	static struct regulator_init_data tps65023_regulator_data[] = {
87748823 MW	149	/* dcdc1 */
	150	{
	151	.constraints = {
	152	.min_uV = 1150000,
	153	.max_uV = 1350000,
	154	.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE \|
	155	REGULATOR_CHANGE_STATUS,
	156	.boot_on = 1,
	157	},
	158	.num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers),
	159	.consumer_supplies = tps65023_dcdc1_consumers,
	160	},
	161	/* dcdc2 */
	162	{
	163	.constraints = {
	164	.min_uV = 1800000,
	165	.max_uV = 1800000,
	166	.valid_ops_mask = REGULATOR_CHANGE_STATUS,
	167	.boot_on = 1,
	168	},
	169	.num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers),
	170	.consumer_supplies = tps65023_dcdc2_consumers,
	171	},
	172	/* dcdc3 */
	173	{
	174	.constraints = {
	175	.min_uV = 1200000,
	176	.max_uV = 1200000,
	177	.valid_ops_mask = REGULATOR_CHANGE_STATUS,
	178	.boot_on = 1,
	179	},
	180	.num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers),
	181	.consumer_supplies = tps65023_dcdc3_consumers,
	182	},
	183	/* ldo1 */
	184	{
	185	.constraints = {
	186	.min_uV = 1800000,
	187	.max_uV = 1800000,
	188	.valid_ops_mask = REGULATOR_CHANGE_STATUS,
	189	.boot_on = 1,
	190	},
	191	.num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers),
	192	.consumer_supplies = tps65023_ldo1_consumers,
	193	},
	194	/* ldo2 */
	195	{
	196	.constraints = {
	197	.min_uV = 2500000,
	198	.max_uV = 3300000,
	199	.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE \|
	200	REGULATOR_CHANGE_STATUS,
	201	.boot_on = 1,
	202	},
	203	.num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers),
	204	.consumer_supplies = tps65023_ldo2_consumers,
	205	},
	206	};
	207
	208	static struct i2c_board_info __initdata mityomap_tps65023_info[] = {
	209	{
	210	I2C_BOARD_INFO("tps65023", 0x48),
	211	.platform_data = &tps65023_regulator_data[0],
	212	},
213	{
214	I2C_BOARD_INFO("24c02", 0x50),
2a7dae04	215	.platform_data = &mityomapl138_fd_chip,
87748823 MW	216	},
	217	};
	218
	219	static int __init pmic_tps65023_init(void)
	220	{
	221	return i2c_register_board_info(1, mityomap_tps65023_info,
	222	ARRAY_SIZE(mityomap_tps65023_info));
	223	}
	224
f2dbb6d9 MW	225	/*
	226	* MityDSP-L138 includes a 256 MByte large-page NAND flash
	227	* (128K blocks).
	228	*/
8939b350	229	static struct mtd_partition mityomapl138_nandflash_partition[] = {
f2dbb6d9 MW	230	{
	231	.name = "rootfs",
	232	.offset = 0,
	233	.size = SZ_128M,
	234	.mask_flags = 0, /* MTD_WRITEABLE, */
	235	},
	236	{
	237	.name = "homefs",
	238	.offset = MTDPART_OFS_APPEND,
	239	.size = MTDPART_SIZ_FULL,
	240	.mask_flags = 0,
	241	},
	242	};
	243
	244	static struct davinci_nand_pdata mityomapl138_nandflash_data = {
	245	.parts = mityomapl138_nandflash_partition,
	246	.nr_parts = ARRAY_SIZE(mityomapl138_nandflash_partition),
	247	.ecc_mode = NAND_ECC_HW,
	248	.options = NAND_USE_FLASH_BBT \| NAND_BUSWIDTH_16,
	249	.ecc_bits = 1, /* 4 bit mode is not supported with 16 bit NAND */
	250	};
	251
	252	static struct resource mityomapl138_nandflash_resource[] = {
	253	{
	254	.start = DA8XX_AEMIF_CS3_BASE,
	255	.end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
	256	.flags = IORESOURCE_MEM,
	257	},
	258	{
	259	.start = DA8XX_AEMIF_CTL_BASE,
	260	.end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
	261	.flags = IORESOURCE_MEM,
	262	},
	263	};
	264
	265	static struct platform_device mityomapl138_nandflash_device = {
	266	.name = "davinci_nand",
	267	.id = 0,
	268	.dev = {
	269	.platform_data = &mityomapl138_nandflash_data,
	270	},
	271	.num_resources = ARRAY_SIZE(mityomapl138_nandflash_resource),
	272	.resource = mityomapl138_nandflash_resource,
	273	};
	274
	275	static struct platform_device *mityomapl138_devices[] __initdata = {
	276	&mityomapl138_nandflash_device,
	277	};
	278
	279	static void __init mityomapl138_setup_nand(void)
	280	{
	281	platform_add_devices(mityomapl138_devices,
	282	ARRAY_SIZE(mityomapl138_devices));
	283	}
	284
	285	static struct davinci_uart_config mityomapl138_uart_config __initdata = {
	286	.enabled_uarts = 0x7,
	287	};
	288
	289	static const short mityomap_mii_pins[] = {
	290	DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
	291	DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
	292	DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
	293	DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
294	DA850_MDIO_D,
295	-1
296	};
297
298	static const short mityomap_rmii_pins[] = {
299	DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
300	DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
301	DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
302	DA850_MDIO_D,
303	-1
304	};
305
306	static void __init mityomapl138_config_emac(void)
307	{
308	void __iomem *cfg_chip3_base;
309	int ret;
310	u32 val;
311	struct davinci_soc_info *soc_info = &davinci_soc_info;
312
313	soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */
314
315	cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
316	val = __raw_readl(cfg_chip3_base);
317
318	if (soc_info->emac_pdata->rmii_en) {
319	val \|= BIT(8);
320	ret = davinci_cfg_reg_list(mityomap_rmii_pins);
321	pr_info("RMII PHY configured\n");
322	} else {
323	val &= ~BIT(8);
324	ret = davinci_cfg_reg_list(mityomap_mii_pins);
325	pr_info("MII PHY configured\n");
326	}
327
328	if (ret) {
329	pr_warning("mii/rmii mux setup failed: %d\n", ret);
330	return;
331	}
332
333	/* configure the CFGCHIP3 register for RMII or MII */
334	__raw_writel(val, cfg_chip3_base);
335
782f2d78	336	soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID;
f2dbb6d9 MW	337
	338	ret = da8xx_register_emac();
	339	if (ret)
	340	pr_warning("emac registration failed: %d\n", ret);
	341	}
	342
	343	static struct davinci_pm_config da850_pm_pdata = {
	344	.sleepcount = 128,
	345	};
	346
	347	static struct platform_device da850_pm_device = {
	348	.name = "pm-davinci",
	349	.dev = {
	350	.platform_data = &da850_pm_pdata,
	351	},
	352	.id = -1,
	353	};
	354
	355	static void __init mityomapl138_init(void)
	356	{
	357	int ret;
	358
	359	/* for now, no special EDMA channels are reserved */
	360	ret = da850_register_edma(NULL);
	361	if (ret)
	362	pr_warning("edma registration failed: %d\n", ret);
	363
	364	ret = da8xx_register_watchdog();
	365	if (ret)
	366	pr_warning("watchdog registration failed: %d\n", ret);
	367
	368	davinci_serial_init(&mityomapl138_uart_config);
	369
87748823 MW	370	ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
	371	if (ret)
	372	pr_warning("i2c0 registration failed: %d\n", ret);
	373
	374	ret = pmic_tps65023_init();
	375	if (ret)
	376	pr_warning("TPS65023 PMIC init failed: %d\n", ret);
	377
f2dbb6d9 MW	378	mityomapl138_setup_nand();
	379
	380	mityomapl138_config_emac();
	381
	382	ret = da8xx_register_rtc();
	383	if (ret)
	384	pr_warning("rtc setup failed: %d\n", ret);
	385
	386	ret = da850_register_cpufreq("pll0_sysclk3");
	387	if (ret)
	388	pr_warning("cpufreq registration failed: %d\n", ret);
	389
	390	ret = da8xx_register_cpuidle();
	391	if (ret)
	392	pr_warning("cpuidle registration failed: %d\n", ret);
	393
	394	ret = da850_register_pm(&da850_pm_device);
	395	if (ret)
	396	pr_warning("da850_evm_init: suspend registration failed: %d\n",
	397	ret);
	398	}
	399
	400	#ifdef CONFIG_SERIAL_8250_CONSOLE
	401	static int __init mityomapl138_console_init(void)
	402	{
	403	if (!machine_is_mityomapl138())
	404	return 0;
	405
	406	return add_preferred_console("ttyS", 1, "115200");
	407	}
	408	console_initcall(mityomapl138_console_init);
	409	#endif
	410
	411	static void __init mityomapl138_map_io(void)
	412	{
	413	da850_init();
	414	}
	415
	416	MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
	417	.phys_io = IO_PHYS,
	418	.io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
	419	.boot_params = (DA8XX_DDR_BASE + 0x100),
	420	.map_io = mityomapl138_map_io,
	421	.init_irq = cp_intc_init,
	422	.timer = &davinci_timer,
	423	.init_machine = mityomapl138_init,
	424	MACHINE_END