[deliverable/linux.git] / arch / arm / mach-davinci / board-neuros-osd2.c

/*
 * Neuros Technologies OSD2 board support
 *
 * Modified from original 644X-EVM board support.
 * 2008 (c) Neuros Technology, LLC.
 * 2009 (c) Jorge Luis Zapata Muga <jorgeluis.zapata@gmail.com>
 * 2009 (c) Andrey A. Porodko <Andrey.Porodko@gmail.com>
 *
 * The Neuros OSD 2.0 is the hardware component of the Neuros Open
 * Internet Television Platform. Hardware is very close to TI
 * DM644X-EVM board. It has:
 * 	DM6446M02 module with 256MB NAND, 256MB RAM, TLV320AIC32 AIC,
 * 	USB, Ethernet, SD/MMC, UART, THS8200, TVP7000 for video.
 * 	Additionaly realtime clock, IR remote control receiver,
 * 	IR Blaster based on MSP430 (firmware although is different
 * 	from used in DM644X-EVM), internal ATA-6 3.5” HDD drive
 * 	with PATA interface, two muxed red-green leds.
 *
 * For more information please refer to
 * 		http://wiki.neurostechnology.com/index.php/OSD_2.0_HD
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/mtd/partitions.h>

#include <asm/mach-types.h>
#include <asm/mach/arch.h>

#include <mach/dm644x.h>
#include <mach/i2c.h>
#include <mach/serial.h>
#include <mach/mux.h>
#include <mach/nand.h>
#include <mach/mmc.h>
#include <mach/usb.h>

#define NEUROS_OSD2_PHY_MASK		0x2
#define NEUROS_OSD2_MDIO_FREQUENCY	2200000 /* PHY bus frequency */

#define DAVINCI_CFC_ATA_BASE		 0x01C66000

#define LXT971_PHY_ID			0x001378e2
#define LXT971_PHY_MASK			0xfffffff0

#define	NTOSD2_AUDIOSOC_I2C_ADDR	0x18
#define	NTOSD2_MSP430_I2C_ADDR		0x59
#define	NTOSD2_MSP430_IRQ		2

/* Neuros OSD2 has a Samsung 256 MByte NAND flash (Dev ID of 0xAA,
 * 2048 blocks in the device, 64 pages per block, 2048 bytes per
 * page.
 */

#define NAND_BLOCK_SIZE		SZ_128K

static struct mtd_partition davinci_ntosd2_nandflash_partition[] = {
	{
		/* UBL (a few copies) plus U-Boot */
		.name		= "bootloader",
		.offset		= 0,
		.size		= 15 * NAND_BLOCK_SIZE,
		.mask_flags	= MTD_WRITEABLE, /* force read-only */
	}, {
		/* U-Boot environment */
		.name		= "params",
		.offset		= MTDPART_OFS_APPEND,
		.size		= 1 * NAND_BLOCK_SIZE,
		.mask_flags	= 0,
	}, {
		/* Kernel */
		.name		= "kernel",
		.offset		= MTDPART_OFS_APPEND,
		.size		= SZ_4M,
		.mask_flags	= 0,
	}, {
		/* File System */
		.name		= "filesystem",
		.offset		= MTDPART_OFS_APPEND,
		.size		= MTDPART_SIZ_FULL,
		.mask_flags	= 0,
	}
	/* A few blocks at end hold a flash Bad Block Table. */
};

static struct davinci_nand_pdata davinci_ntosd2_nandflash_data = {
	.parts		= davinci_ntosd2_nandflash_partition,
	.nr_parts	= ARRAY_SIZE(davinci_ntosd2_nandflash_partition),
	.ecc_mode	= NAND_ECC_HW,
	.options	= NAND_USE_FLASH_BBT,
};

static struct resource davinci_ntosd2_nandflash_resource[] = {
	{
		.start		= DM644X_ASYNC_EMIF_DATA_CE0_BASE,
		.end		= DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
		.flags		= IORESOURCE_MEM,
	}, {
		.start		= DM644X_ASYNC_EMIF_CONTROL_BASE,
		.end		= DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
		.flags		= IORESOURCE_MEM,
	},
};

static struct platform_device davinci_ntosd2_nandflash_device = {
	.name		= "davinci_nand",
	.id		= 0,
	.dev		= {
		.platform_data	= &davinci_ntosd2_nandflash_data,
	},
	.num_resources	= ARRAY_SIZE(davinci_ntosd2_nandflash_resource),
	.resource	= davinci_ntosd2_nandflash_resource,
};

static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32);

static struct platform_device davinci_fb_device = {
	.name		= "davincifb",
	.id		= -1,
	.dev = {
		.dma_mask		= &davinci_fb_dma_mask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
	.num_resources = 0,
};

static struct resource ide_resources[] = {
	{
		.start		= DAVINCI_CFC_ATA_BASE,
		.end		= DAVINCI_CFC_ATA_BASE + 0x7ff,
		.flags		= IORESOURCE_MEM,
	},
	{
		.start		= IRQ_IDE,
		.end		= IRQ_IDE,
		.flags		= IORESOURCE_IRQ,
	},
};

static u64 ide_dma_mask = DMA_BIT_MASK(32);

static struct platform_device ide_dev = {
	.name		= "palm_bk3710",
	.id		= -1,
	.resource	= ide_resources,
	.num_resources	= ARRAY_SIZE(ide_resources),
	.dev = {
		.dma_mask		= &ide_dma_mask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
};

static struct snd_platform_data dm644x_ntosd2_snd_data;

static struct gpio_led ntosd2_leds[] = {
	{ .name = "led1_green", .gpio = GPIO(10), },
	{ .name = "led1_red",   .gpio = GPIO(11), },
	{ .name = "led2_green", .gpio = GPIO(12), },
	{ .name = "led2_red",   .gpio = GPIO(13), },
};

static struct gpio_led_platform_data ntosd2_leds_data = {
	.num_leds	= ARRAY_SIZE(ntosd2_leds),
	.leds		= ntosd2_leds,
};

static struct platform_device ntosd2_leds_dev = {
	.name = "leds-gpio",
	.id   = -1,
	.dev = {
		.platform_data 		= &ntosd2_leds_data,
	},
};


static struct platform_device *davinci_ntosd2_devices[] __initdata = {
	&davinci_fb_device,
	&ntosd2_leds_dev,
};

static struct davinci_uart_config uart_config __initdata = {
	.enabled_uarts = (1 << 0),
};

static void __init davinci_ntosd2_map_io(void)
{
	dm644x_init();
}

/*
 I2C initialization
*/
static struct davinci_i2c_platform_data ntosd2_i2c_pdata = {
	.bus_freq	= 20 /* kHz */,
	.bus_delay	= 100 /* usec */,
};

static struct i2c_board_info __initdata ntosd2_i2c_info[] =  {
};

static	int ntosd2_init_i2c(void)
{
	int	status;

	davinci_init_i2c(&ntosd2_i2c_pdata);
	status = gpio_request(NTOSD2_MSP430_IRQ, ntosd2_i2c_info[0].type);
	if (status == 0) {
		status = gpio_direction_input(NTOSD2_MSP430_IRQ);
		if (status == 0) {
			status = gpio_to_irq(NTOSD2_MSP430_IRQ);
			if (status > 0) {
				ntosd2_i2c_info[0].irq = status;
				i2c_register_board_info(1,
					ntosd2_i2c_info,
					ARRAY_SIZE(ntosd2_i2c_info));
			}
		}
	}
	return status;
}

static struct davinci_mmc_config davinci_ntosd2_mmc_config = {
	.wires		= 4,
	.version	= MMC_CTLR_VERSION_1
};


#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
	defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
#define HAS_ATA 1
#else
#define HAS_ATA 0
#endif

#if defined(CONFIG_MTD_NAND_DAVINCI) || \
	defined(CONFIG_MTD_NAND_DAVINCI_MODULE)
#define HAS_NAND 1
#else
#define HAS_NAND 0
#endif

static __init void davinci_ntosd2_init(void)
{
	struct clk *aemif_clk;
	struct davinci_soc_info *soc_info = &davinci_soc_info;
	int	status;

	aemif_clk = clk_get(NULL, "aemif");
	clk_enable(aemif_clk);

	if (HAS_ATA) {
		if (HAS_NAND)
			pr_warning("WARNING: both IDE and Flash are "
				"enabled, but they share AEMIF pins.\n"
				"\tDisable IDE for NAND/NOR support.\n");
		davinci_cfg_reg(DM644X_HPIEN_DISABLE);
		davinci_cfg_reg(DM644X_ATAEN);
		davinci_cfg_reg(DM644X_HDIREN);
		platform_device_register(&ide_dev);
	} else if (HAS_NAND) {
		davinci_cfg_reg(DM644X_HPIEN_DISABLE);
		davinci_cfg_reg(DM644X_ATAEN_DISABLE);

		/* only one device will be jumpered and detected */
		if (HAS_NAND)
			platform_device_register(
					&davinci_ntosd2_nandflash_device);
	}

	platform_add_devices(davinci_ntosd2_devices,
				ARRAY_SIZE(davinci_ntosd2_devices));

	/* Initialize I2C interface specific for this board */
	status = ntosd2_init_i2c();
	if (status < 0)
		pr_warning("davinci_ntosd2_init: msp430 irq setup failed:"
						"	 %d\n", status);

	davinci_serial_init(&uart_config);
	dm644x_init_asp(&dm644x_ntosd2_snd_data);

	soc_info->emac_pdata->phy_mask = NEUROS_OSD2_PHY_MASK;
	soc_info->emac_pdata->mdio_max_freq = NEUROS_OSD2_MDIO_FREQUENCY;

	davinci_setup_usb(1000, 8);
	/*
	 * Mux the pins to be GPIOs, VLYNQEN is already done at startup.
	 * The AEAWx are five new AEAW pins that can be muxed by separately.
	 * They are a bitmask for GPIO management. According TI
	 * documentation (http://www.ti.com/lit/gpn/tms320dm6446) to employ
	 * gpio(10,11,12,13) for leds any combination of bits works except
	 * four last. So we are to reset all five.
	 */
	davinci_cfg_reg(DM644X_AEAW0);
	davinci_cfg_reg(DM644X_AEAW1);
	davinci_cfg_reg(DM644X_AEAW2);
	davinci_cfg_reg(DM644X_AEAW3);
	davinci_cfg_reg(DM644X_AEAW4);

	davinci_setup_mmc(0, &davinci_ntosd2_mmc_config);
}

static __init void davinci_ntosd2_irq_init(void)
{
	davinci_irq_init();
}

MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
	/* Maintainer: Neuros Technologies <neuros@groups.google.com> */
	.phys_io	= IO_PHYS,
	.io_pg_offst	= (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
	.boot_params	= (DAVINCI_DDR_BASE + 0x100),
	.map_io		 = davinci_ntosd2_map_io,
	.init_irq	= davinci_ntosd2_irq_init,
	.timer		= &davinci_timer,
	.init_machine = davinci_ntosd2_init,
MACHINE_END
Commit	Line	Data
c16fe267 AP	1	/*
	2	* Neuros Technologies OSD2 board support
	3	*
	4	* Modified from original 644X-EVM board support.
	5	* 2008 (c) Neuros Technology, LLC.
	6	* 2009 (c) Jorge Luis Zapata Muga <jorgeluis.zapata@gmail.com>
	7	* 2009 (c) Andrey A. Porodko <Andrey.Porodko@gmail.com>
	8	*
	9	* The Neuros OSD 2.0 is the hardware component of the Neuros Open
	10	* Internet Television Platform. Hardware is very close to TI
	11	* DM644X-EVM board. It has:
	12	* DM6446M02 module with 256MB NAND, 256MB RAM, TLV320AIC32 AIC,
	13	* USB, Ethernet, SD/MMC, UART, THS8200, TVP7000 for video.
	14	* Additionaly realtime clock, IR remote control receiver,
	15	* IR Blaster based on MSP430 (firmware although is different
	16	* from used in DM644X-EVM), internal ATA-6 3.5” HDD drive
	17	* with PATA interface, two muxed red-green leds.
	18	*
	19	* For more information please refer to
	20	* http://wiki.neurostechnology.com/index.php/OSD_2.0_HD
	21	*
	22	* This file is licensed under the terms of the GNU General Public
	23	* License version 2. This program is licensed "as is" without any
	24	* warranty of any kind, whether express or implied.
	25	*/
	26	#include <linux/platform_device.h>
	27	#include <linux/gpio.h>
	28	#include <linux/mtd/partitions.h>
	29
	30	#include <asm/mach-types.h>
	31	#include <asm/mach/arch.h>
	32
	33	#include <mach/dm644x.h>
	34	#include <mach/i2c.h>
	35	#include <mach/serial.h>
	36	#include <mach/mux.h>
	37	#include <mach/nand.h>
	38	#include <mach/mmc.h>
	39	#include <mach/usb.h>
	40
	41	#define NEUROS_OSD2_PHY_MASK 0x2
	42	#define NEUROS_OSD2_MDIO_FREQUENCY 2200000 /* PHY bus frequency */
	43
	44	#define DAVINCI_CFC_ATA_BASE 0x01C66000
	45
c16fe267 AP	46	#define LXT971_PHY_ID 0x001378e2
	47	#define LXT971_PHY_MASK 0xfffffff0
	48
	49	#define NTOSD2_AUDIOSOC_I2C_ADDR 0x18
	50	#define NTOSD2_MSP430_I2C_ADDR 0x59
	51	#define NTOSD2_MSP430_IRQ 2
	52
	53	/* Neuros OSD2 has a Samsung 256 MByte NAND flash (Dev ID of 0xAA,
	54	* 2048 blocks in the device, 64 pages per block, 2048 bytes per
	55	* page.
	56	*/
	57
	58	#define NAND_BLOCK_SIZE SZ_128K
	59
28552c2e	60	static struct mtd_partition davinci_ntosd2_nandflash_partition[] = {
c16fe267 AP	61	{
	62	/* UBL (a few copies) plus U-Boot */
	63	.name = "bootloader",
	64	.offset = 0,
	65	.size = 15 * NAND_BLOCK_SIZE,
	66	.mask_flags = MTD_WRITEABLE, /* force read-only */
	67	}, {
	68	/* U-Boot environment */
	69	.name = "params",
	70	.offset = MTDPART_OFS_APPEND,
	71	.size = 1 * NAND_BLOCK_SIZE,
	72	.mask_flags = 0,
	73	}, {
	74	/* Kernel */
	75	.name = "kernel",
	76	.offset = MTDPART_OFS_APPEND,
	77	.size = SZ_4M,
	78	.mask_flags = 0,
	79	}, {
	80	/* File System */
	81	.name = "filesystem",
	82	.offset = MTDPART_OFS_APPEND,
	83	.size = MTDPART_SIZ_FULL,
	84	.mask_flags = 0,
	85	}
	86	/* A few blocks at end hold a flash Bad Block Table. */
	87	};
	88
	89	static struct davinci_nand_pdata davinci_ntosd2_nandflash_data = {
	90	.parts = davinci_ntosd2_nandflash_partition,
	91	.nr_parts = ARRAY_SIZE(davinci_ntosd2_nandflash_partition),
	92	.ecc_mode = NAND_ECC_HW,
	93	.options = NAND_USE_FLASH_BBT,
	94	};
	95
	96	static struct resource davinci_ntosd2_nandflash_resource[] = {
	97	{
70342174 SS	98	.start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
70342174 SS	99	.end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
c16fe267 AP	100	.flags = IORESOURCE_MEM,
c16fe267 AP	101	}, {
70342174 SS	102	.start = DM644X_ASYNC_EMIF_CONTROL_BASE,
70342174 SS	103	.end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
c16fe267 AP	104	.flags = IORESOURCE_MEM,
	105	},
	106	};
	107
	108	static struct platform_device davinci_ntosd2_nandflash_device = {
	109	.name = "davinci_nand",
	110	.id = 0,
	111	.dev = {
	112	.platform_data = &davinci_ntosd2_nandflash_data,
	113	},
	114	.num_resources = ARRAY_SIZE(davinci_ntosd2_nandflash_resource),
	115	.resource = davinci_ntosd2_nandflash_resource,
	116	};
	117
	118	static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32);
	119
	120	static struct platform_device davinci_fb_device = {
	121	.name = "davincifb",
	122	.id = -1,
	123	.dev = {
	124	.dma_mask = &davinci_fb_dma_mask,
	125	.coherent_dma_mask = DMA_BIT_MASK(32),
	126	},
	127	.num_resources = 0,
	128	};
	129
	130	static struct resource ide_resources[] = {
	131	{
	132	.start = DAVINCI_CFC_ATA_BASE,
	133	.end = DAVINCI_CFC_ATA_BASE + 0x7ff,
	134	.flags = IORESOURCE_MEM,
	135	},
	136	{
	137	.start = IRQ_IDE,
	138	.end = IRQ_IDE,
	139	.flags = IORESOURCE_IRQ,
	140	},
	141	};
	142
	143	static u64 ide_dma_mask = DMA_BIT_MASK(32);
	144
	145	static struct platform_device ide_dev = {
	146	.name = "palm_bk3710",
	147	.id = -1,
	148	.resource = ide_resources,
	149	.num_resources = ARRAY_SIZE(ide_resources),
	150	.dev = {
	151	.dma_mask = &ide_dma_mask,
	152	.coherent_dma_mask = DMA_BIT_MASK(32),
	153	},
	154	};
	155
	156	static struct snd_platform_data dm644x_ntosd2_snd_data;
	157
	158	static struct gpio_led ntosd2_leds[] = {
	159	{ .name = "led1_green", .gpio = GPIO(10), },
	160	{ .name = "led1_red", .gpio = GPIO(11), },
	161	{ .name = "led2_green", .gpio = GPIO(12), },
	162	{ .name = "led2_red", .gpio = GPIO(13), },
	163	};
	164
	165	static struct gpio_led_platform_data ntosd2_leds_data = {
	166	.num_leds = ARRAY_SIZE(ntosd2_leds),
	167	.leds = ntosd2_leds,
168	};
169
170	static struct platform_device ntosd2_leds_dev = {
171	.name = "leds-gpio",
172	.id = -1,
173	.dev = {
174	.platform_data = &ntosd2_leds_data,
175	},
176	};
177
178
179	static struct platform_device *davinci_ntosd2_devices[] __initdata = {
180	&davinci_fb_device,
181	&ntosd2_leds_dev,
182	};
183
184	static struct davinci_uart_config uart_config __initdata = {
185	.enabled_uarts = (1 << 0),
186	};
187
188	static void __init davinci_ntosd2_map_io(void)
189	{
190	dm644x_init();
191	}
192
193	/*
194	I2C initialization
195	*/
196	static struct davinci_i2c_platform_data ntosd2_i2c_pdata = {
197	.bus_freq = 20 /* kHz */,
198	.bus_delay = 100 /* usec */,
199	};
200
201	static struct i2c_board_info __initdata ntosd2_i2c_info[] = {
202	};
203
204	static int ntosd2_init_i2c(void)
205	{
206	int status;
207
208	davinci_init_i2c(&ntosd2_i2c_pdata);
209	status = gpio_request(NTOSD2_MSP430_IRQ, ntosd2_i2c_info[0].type);
210	if (status == 0) {
211	status = gpio_direction_input(NTOSD2_MSP430_IRQ);
212	if (status == 0) {
213	status = gpio_to_irq(NTOSD2_MSP430_IRQ);
214	if (status > 0) {
215	ntosd2_i2c_info[0].irq = status;
216	i2c_register_board_info(1,
217	ntosd2_i2c_info,
218	ARRAY_SIZE(ntosd2_i2c_info));
219	}
220	}
221	}
222	return status;
223	}
224
225	static struct davinci_mmc_config davinci_ntosd2_mmc_config = {
226	.wires = 4,
227	.version = MMC_CTLR_VERSION_1
228	};
229
230
231	#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) \|\| \
232	defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
233	#define HAS_ATA 1
234	#else
235	#define HAS_ATA 0
236	#endif
237
238	#if defined(CONFIG_MTD_NAND_DAVINCI) \|\| \
239	defined(CONFIG_MTD_NAND_DAVINCI_MODULE)
240	#define HAS_NAND 1
241	#else
242	#define HAS_NAND 0
243	#endif
244
245	static __init void davinci_ntosd2_init(void)
246	{
247	struct clk *aemif_clk;
248	struct davinci_soc_info *soc_info = &davinci_soc_info;
249	int status;
250
251	aemif_clk = clk_get(NULL, "aemif");
252	clk_enable(aemif_clk);
253
254	if (HAS_ATA) {
255	if (HAS_NAND)
256	pr_warning("WARNING: both IDE and Flash are "
257	"enabled, but they share AEMIF pins.\n"
258	"\tDisable IDE for NAND/NOR support.\n");
259	davinci_cfg_reg(DM644X_HPIEN_DISABLE);
260	davinci_cfg_reg(DM644X_ATAEN);
261	davinci_cfg_reg(DM644X_HDIREN);
262	platform_device_register(&ide_dev);
263	} else if (HAS_NAND) {
264	davinci_cfg_reg(DM644X_HPIEN_DISABLE);
265	davinci_cfg_reg(DM644X_ATAEN_DISABLE);
266
267	/* only one device will be jumpered and detected */
268	if (HAS_NAND)
269	platform_device_register(
270	&davinci_ntosd2_nandflash_device);
271	}
272
273	platform_add_devices(davinci_ntosd2_devices,
274	ARRAY_SIZE(davinci_ntosd2_devices));
275
276	/* Initialize I2C interface specific for this board */
277	status = ntosd2_init_i2c();
278	if (status < 0)
279	pr_warning("davinci_ntosd2_init: msp430 irq setup failed:"
280	" %d\n", status);
281
282	davinci_serial_init(&uart_config);
283	dm644x_init_asp(&dm644x_ntosd2_snd_data);
284
285	soc_info->emac_pdata->phy_mask = NEUROS_OSD2_PHY_MASK;
286	soc_info->emac_pdata->mdio_max_freq = NEUROS_OSD2_MDIO_FREQUENCY;
287
288	davinci_setup_usb(1000, 8);
289	/*
290	* Mux the pins to be GPIOs, VLYNQEN is already done at startup.
291	* The AEAWx are five new AEAW pins that can be muxed by separately.
292	* They are a bitmask for GPIO management. According TI
293	* documentation (http://www.ti.com/lit/gpn/tms320dm6446) to employ
294	* gpio(10,11,12,13) for leds any combination of bits works except
295	* four last. So we are to reset all five.
296	*/
297	davinci_cfg_reg(DM644X_AEAW0);
298	davinci_cfg_reg(DM644X_AEAW1);
299	davinci_cfg_reg(DM644X_AEAW2);
300	davinci_cfg_reg(DM644X_AEAW3);
301	davinci_cfg_reg(DM644X_AEAW4);
302
303	davinci_setup_mmc(0, &davinci_ntosd2_mmc_config);
304	}
305
306	static __init void davinci_ntosd2_irq_init(void)
307	{
308	davinci_irq_init();
309	}
310
311	MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
312	/* Maintainer: Neuros Technologies <neuros@groups.google.com> */
313	.phys_io = IO_PHYS,
314	.io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
315	.boot_params = (DAVINCI_DDR_BASE + 0x100),
316	.map_io = davinci_ntosd2_map_io,
317	.init_irq = davinci_ntosd2_irq_init,
318	.timer = &davinci_timer,
319	.init_machine = davinci_ntosd2_init,
320	MACHINE_END