Commit | Line | Data |
---|---|---|
3e062b07 | 1 | /* |
c5b736d0 | 2 | * Clock and PLL control for DaVinci devices |
3e062b07 | 3 | * |
c5b736d0 KH |
4 | * Copyright (C) 2006-2007 Texas Instruments. |
5 | * Copyright (C) 2008-2009 Deep Root Systems, LLC | |
3e062b07 VB |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/errno.h> | |
c5b736d0 | 17 | #include <linux/clk.h> |
3e062b07 VB |
18 | #include <linux/err.h> |
19 | #include <linux/mutex.h> | |
fced80c7 | 20 | #include <linux/io.h> |
d6a61563 | 21 | #include <linux/delay.h> |
3e062b07 | 22 | |
a09e64fb | 23 | #include <mach/hardware.h> |
3e062b07 | 24 | |
28552c2e | 25 | #include <mach/clock.h> |
3acf731c | 26 | #include "psc.h" |
c5b736d0 | 27 | #include <mach/cputype.h> |
3e062b07 VB |
28 | #include "clock.h" |
29 | ||
3e062b07 VB |
30 | static LIST_HEAD(clocks); |
31 | static DEFINE_MUTEX(clocks_mutex); | |
32 | static DEFINE_SPINLOCK(clockfw_lock); | |
33 | ||
c5b736d0 | 34 | static void __clk_enable(struct clk *clk) |
3e062b07 | 35 | { |
c5b736d0 KH |
36 | if (clk->parent) |
37 | __clk_enable(clk->parent); | |
c6007ffe PA |
38 | if (clk->usecount++ == 0) { |
39 | if (clk->flags & CLK_PSC) | |
40 | davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc, | |
41 | true, clk->flags); | |
42 | else if (clk->clk_enable) | |
43 | clk->clk_enable(clk); | |
44 | } | |
3e062b07 VB |
45 | } |
46 | ||
47 | static void __clk_disable(struct clk *clk) | |
48 | { | |
c5b736d0 | 49 | if (WARN_ON(clk->usecount == 0)) |
3e062b07 | 50 | return; |
c6007ffe PA |
51 | if (--clk->usecount == 0) { |
52 | if (!(clk->flags & CLK_PLL) && (clk->flags & CLK_PSC)) | |
53 | davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc, | |
54 | false, clk->flags); | |
55 | else if (clk->clk_disable) | |
56 | clk->clk_disable(clk); | |
57 | } | |
c5b736d0 KH |
58 | if (clk->parent) |
59 | __clk_disable(clk->parent); | |
3e062b07 VB |
60 | } |
61 | ||
af47e6bb RT |
62 | int davinci_clk_reset(struct clk *clk, bool reset) |
63 | { | |
64 | unsigned long flags; | |
65 | ||
66 | if (clk == NULL || IS_ERR(clk)) | |
67 | return -EINVAL; | |
68 | ||
69 | spin_lock_irqsave(&clockfw_lock, flags); | |
70 | if (clk->flags & CLK_PSC) | |
71 | davinci_psc_reset(clk->gpsc, clk->lpsc, reset); | |
72 | spin_unlock_irqrestore(&clockfw_lock, flags); | |
73 | ||
74 | return 0; | |
75 | } | |
76 | EXPORT_SYMBOL(davinci_clk_reset); | |
77 | ||
78 | int davinci_clk_reset_assert(struct clk *clk) | |
79 | { | |
80 | if (clk == NULL || IS_ERR(clk) || !clk->reset) | |
81 | return -EINVAL; | |
82 | ||
83 | return clk->reset(clk, true); | |
84 | } | |
85 | EXPORT_SYMBOL(davinci_clk_reset_assert); | |
86 | ||
87 | int davinci_clk_reset_deassert(struct clk *clk) | |
88 | { | |
89 | if (clk == NULL || IS_ERR(clk) || !clk->reset) | |
90 | return -EINVAL; | |
91 | ||
92 | return clk->reset(clk, false); | |
93 | } | |
94 | EXPORT_SYMBOL(davinci_clk_reset_deassert); | |
95 | ||
3e062b07 VB |
96 | int clk_enable(struct clk *clk) |
97 | { | |
98 | unsigned long flags; | |
3e062b07 | 99 | |
f6c1a8a6 PU |
100 | if (!clk) |
101 | return 0; | |
102 | else if (IS_ERR(clk)) | |
3e062b07 VB |
103 | return -EINVAL; |
104 | ||
c5b736d0 KH |
105 | spin_lock_irqsave(&clockfw_lock, flags); |
106 | __clk_enable(clk); | |
107 | spin_unlock_irqrestore(&clockfw_lock, flags); | |
3e062b07 | 108 | |
c5b736d0 | 109 | return 0; |
3e062b07 VB |
110 | } |
111 | EXPORT_SYMBOL(clk_enable); | |
112 | ||
113 | void clk_disable(struct clk *clk) | |
114 | { | |
115 | unsigned long flags; | |
116 | ||
117 | if (clk == NULL || IS_ERR(clk)) | |
118 | return; | |
119 | ||
c5b736d0 KH |
120 | spin_lock_irqsave(&clockfw_lock, flags); |
121 | __clk_disable(clk); | |
122 | spin_unlock_irqrestore(&clockfw_lock, flags); | |
3e062b07 VB |
123 | } |
124 | EXPORT_SYMBOL(clk_disable); | |
125 | ||
126 | unsigned long clk_get_rate(struct clk *clk) | |
127 | { | |
128 | if (clk == NULL || IS_ERR(clk)) | |
f6c1a8a6 | 129 | return 0; |
3e062b07 | 130 | |
c5b736d0 | 131 | return clk->rate; |
3e062b07 VB |
132 | } |
133 | EXPORT_SYMBOL(clk_get_rate); | |
134 | ||
135 | long clk_round_rate(struct clk *clk, unsigned long rate) | |
136 | { | |
137 | if (clk == NULL || IS_ERR(clk)) | |
4408c26b | 138 | return 0; |
3e062b07 | 139 | |
d6a61563 SN |
140 | if (clk->round_rate) |
141 | return clk->round_rate(clk, rate); | |
142 | ||
c5b736d0 | 143 | return clk->rate; |
3e062b07 VB |
144 | } |
145 | EXPORT_SYMBOL(clk_round_rate); | |
146 | ||
d6a61563 SN |
147 | /* Propagate rate to children */ |
148 | static void propagate_rate(struct clk *root) | |
149 | { | |
150 | struct clk *clk; | |
151 | ||
152 | list_for_each_entry(clk, &root->children, childnode) { | |
153 | if (clk->recalc) | |
154 | clk->rate = clk->recalc(clk); | |
155 | propagate_rate(clk); | |
156 | } | |
157 | } | |
158 | ||
3e062b07 VB |
159 | int clk_set_rate(struct clk *clk, unsigned long rate) |
160 | { | |
d6a61563 SN |
161 | unsigned long flags; |
162 | int ret = -EINVAL; | |
163 | ||
f6c1a8a6 PU |
164 | if (!clk) |
165 | return 0; | |
166 | else if (IS_ERR(clk)) | |
167 | return -EINVAL; | |
d6a61563 | 168 | |
d6a61563 SN |
169 | if (clk->set_rate) |
170 | ret = clk->set_rate(clk, rate); | |
3b43cd6f SN |
171 | |
172 | spin_lock_irqsave(&clockfw_lock, flags); | |
d6a61563 SN |
173 | if (ret == 0) { |
174 | if (clk->recalc) | |
175 | clk->rate = clk->recalc(clk); | |
176 | propagate_rate(clk); | |
177 | } | |
178 | spin_unlock_irqrestore(&clockfw_lock, flags); | |
3e062b07 | 179 | |
d6a61563 | 180 | return ret; |
3e062b07 VB |
181 | } |
182 | EXPORT_SYMBOL(clk_set_rate); | |
183 | ||
b82a51e8 SN |
184 | int clk_set_parent(struct clk *clk, struct clk *parent) |
185 | { | |
186 | unsigned long flags; | |
187 | ||
f6c1a8a6 PU |
188 | if (!clk) |
189 | return 0; | |
190 | else if (IS_ERR(clk)) | |
b82a51e8 SN |
191 | return -EINVAL; |
192 | ||
193 | /* Cannot change parent on enabled clock */ | |
194 | if (WARN_ON(clk->usecount)) | |
195 | return -EINVAL; | |
196 | ||
197 | mutex_lock(&clocks_mutex); | |
198 | clk->parent = parent; | |
199 | list_del_init(&clk->childnode); | |
200 | list_add(&clk->childnode, &clk->parent->children); | |
201 | mutex_unlock(&clocks_mutex); | |
202 | ||
203 | spin_lock_irqsave(&clockfw_lock, flags); | |
204 | if (clk->recalc) | |
205 | clk->rate = clk->recalc(clk); | |
206 | propagate_rate(clk); | |
207 | spin_unlock_irqrestore(&clockfw_lock, flags); | |
208 | ||
209 | return 0; | |
210 | } | |
211 | EXPORT_SYMBOL(clk_set_parent); | |
212 | ||
3e062b07 VB |
213 | int clk_register(struct clk *clk) |
214 | { | |
215 | if (clk == NULL || IS_ERR(clk)) | |
216 | return -EINVAL; | |
217 | ||
c5b736d0 KH |
218 | if (WARN(clk->parent && !clk->parent->rate, |
219 | "CLK: %s parent %s has no rate!\n", | |
220 | clk->name, clk->parent->name)) | |
221 | return -EINVAL; | |
222 | ||
f02bf3b3 SN |
223 | INIT_LIST_HEAD(&clk->children); |
224 | ||
3e062b07 | 225 | mutex_lock(&clocks_mutex); |
c5b736d0 | 226 | list_add_tail(&clk->node, &clocks); |
f02bf3b3 SN |
227 | if (clk->parent) |
228 | list_add_tail(&clk->childnode, &clk->parent->children); | |
3e062b07 VB |
229 | mutex_unlock(&clocks_mutex); |
230 | ||
c5b736d0 KH |
231 | /* If rate is already set, use it */ |
232 | if (clk->rate) | |
233 | return 0; | |
234 | ||
de381a91 SN |
235 | /* Else, see if there is a way to calculate it */ |
236 | if (clk->recalc) | |
237 | clk->rate = clk->recalc(clk); | |
238 | ||
c5b736d0 | 239 | /* Otherwise, default to parent rate */ |
de381a91 | 240 | else if (clk->parent) |
c5b736d0 KH |
241 | clk->rate = clk->parent->rate; |
242 | ||
3e062b07 VB |
243 | return 0; |
244 | } | |
245 | EXPORT_SYMBOL(clk_register); | |
246 | ||
247 | void clk_unregister(struct clk *clk) | |
248 | { | |
249 | if (clk == NULL || IS_ERR(clk)) | |
250 | return; | |
251 | ||
252 | mutex_lock(&clocks_mutex); | |
253 | list_del(&clk->node); | |
f02bf3b3 | 254 | list_del(&clk->childnode); |
3e062b07 VB |
255 | mutex_unlock(&clocks_mutex); |
256 | } | |
257 | EXPORT_SYMBOL(clk_unregister); | |
258 | ||
c5b736d0 KH |
259 | #ifdef CONFIG_DAVINCI_RESET_CLOCKS |
260 | /* | |
261 | * Disable any unused clocks left on by the bootloader | |
262 | */ | |
3aa3e840 | 263 | int __init davinci_clk_disable_unused(void) |
c5b736d0 KH |
264 | { |
265 | struct clk *ck; | |
266 | ||
267 | spin_lock_irq(&clockfw_lock); | |
268 | list_for_each_entry(ck, &clocks, node) { | |
269 | if (ck->usecount > 0) | |
270 | continue; | |
271 | if (!(ck->flags & CLK_PSC)) | |
272 | continue; | |
273 | ||
274 | /* ignore if in Disabled or SwRstDisable states */ | |
789a785e | 275 | if (!davinci_psc_is_clk_active(ck->gpsc, ck->lpsc)) |
c5b736d0 KH |
276 | continue; |
277 | ||
c89f1681 | 278 | pr_debug("Clocks: disable unused %s\n", ck->name); |
52958be3 | 279 | |
12221d43 | 280 | davinci_psc_config(ck->domain, ck->gpsc, ck->lpsc, |
a51ca38b | 281 | false, ck->flags); |
3e062b07 | 282 | } |
c5b736d0 KH |
283 | spin_unlock_irq(&clockfw_lock); |
284 | ||
285 | return 0; | |
286 | } | |
c5b736d0 | 287 | #endif |
3e062b07 | 288 | |
de381a91 | 289 | static unsigned long clk_sysclk_recalc(struct clk *clk) |
3e062b07 | 290 | { |
c5b736d0 KH |
291 | u32 v, plldiv; |
292 | struct pll_data *pll; | |
de381a91 | 293 | unsigned long rate = clk->rate; |
c5b736d0 KH |
294 | |
295 | /* If this is the PLL base clock, no more calculations needed */ | |
296 | if (clk->pll_data) | |
de381a91 | 297 | return rate; |
c5b736d0 KH |
298 | |
299 | if (WARN_ON(!clk->parent)) | |
de381a91 | 300 | return rate; |
c5b736d0 | 301 | |
de381a91 | 302 | rate = clk->parent->rate; |
c5b736d0 KH |
303 | |
304 | /* Otherwise, the parent must be a PLL */ | |
305 | if (WARN_ON(!clk->parent->pll_data)) | |
de381a91 | 306 | return rate; |
c5b736d0 KH |
307 | |
308 | pll = clk->parent->pll_data; | |
309 | ||
310 | /* If pre-PLL, source clock is before the multiplier and divider(s) */ | |
311 | if (clk->flags & PRE_PLL) | |
de381a91 | 312 | rate = pll->input_rate; |
c5b736d0 KH |
313 | |
314 | if (!clk->div_reg) | |
de381a91 | 315 | return rate; |
c5b736d0 KH |
316 | |
317 | v = __raw_readl(pll->base + clk->div_reg); | |
318 | if (v & PLLDIV_EN) { | |
d6961e68 | 319 | plldiv = (v & pll->div_ratio_mask) + 1; |
c5b736d0 | 320 | if (plldiv) |
de381a91 | 321 | rate /= plldiv; |
c5b736d0 | 322 | } |
de381a91 SN |
323 | |
324 | return rate; | |
325 | } | |
326 | ||
b39639b8 SN |
327 | int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate) |
328 | { | |
329 | unsigned v; | |
330 | struct pll_data *pll; | |
331 | unsigned long input; | |
332 | unsigned ratio = 0; | |
333 | ||
334 | /* If this is the PLL base clock, wrong function to call */ | |
335 | if (clk->pll_data) | |
336 | return -EINVAL; | |
337 | ||
338 | /* There must be a parent... */ | |
339 | if (WARN_ON(!clk->parent)) | |
340 | return -EINVAL; | |
341 | ||
342 | /* ... the parent must be a PLL... */ | |
343 | if (WARN_ON(!clk->parent->pll_data)) | |
344 | return -EINVAL; | |
345 | ||
346 | /* ... and this clock must have a divider. */ | |
347 | if (WARN_ON(!clk->div_reg)) | |
348 | return -EINVAL; | |
349 | ||
350 | pll = clk->parent->pll_data; | |
351 | ||
352 | input = clk->parent->rate; | |
353 | ||
354 | /* If pre-PLL, source clock is before the multiplier and divider(s) */ | |
355 | if (clk->flags & PRE_PLL) | |
356 | input = pll->input_rate; | |
357 | ||
358 | if (input > rate) { | |
359 | /* | |
360 | * Can afford to provide an output little higher than requested | |
361 | * only if maximum rate supported by hardware on this sysclk | |
362 | * is known. | |
363 | */ | |
364 | if (clk->maxrate) { | |
365 | ratio = DIV_ROUND_CLOSEST(input, rate); | |
366 | if (input / ratio > clk->maxrate) | |
367 | ratio = 0; | |
368 | } | |
369 | ||
370 | if (ratio == 0) | |
371 | ratio = DIV_ROUND_UP(input, rate); | |
372 | ||
373 | ratio--; | |
374 | } | |
375 | ||
b1d05be6 | 376 | if (ratio > pll->div_ratio_mask) |
b39639b8 SN |
377 | return -EINVAL; |
378 | ||
379 | do { | |
380 | v = __raw_readl(pll->base + PLLSTAT); | |
381 | } while (v & PLLSTAT_GOSTAT); | |
382 | ||
383 | v = __raw_readl(pll->base + clk->div_reg); | |
b1d05be6 | 384 | v &= ~pll->div_ratio_mask; |
b39639b8 SN |
385 | v |= ratio | PLLDIV_EN; |
386 | __raw_writel(v, pll->base + clk->div_reg); | |
387 | ||
388 | v = __raw_readl(pll->base + PLLCMD); | |
389 | v |= PLLCMD_GOSET; | |
390 | __raw_writel(v, pll->base + PLLCMD); | |
391 | ||
392 | do { | |
393 | v = __raw_readl(pll->base + PLLSTAT); | |
394 | } while (v & PLLSTAT_GOSTAT); | |
395 | ||
396 | return 0; | |
397 | } | |
398 | EXPORT_SYMBOL(davinci_set_sysclk_rate); | |
399 | ||
de381a91 SN |
400 | static unsigned long clk_leafclk_recalc(struct clk *clk) |
401 | { | |
402 | if (WARN_ON(!clk->parent)) | |
403 | return clk->rate; | |
404 | ||
405 | return clk->parent->rate; | |
c5b736d0 KH |
406 | } |
407 | ||
56e580d7 SN |
408 | int davinci_simple_set_rate(struct clk *clk, unsigned long rate) |
409 | { | |
410 | clk->rate = rate; | |
411 | return 0; | |
412 | } | |
413 | ||
de381a91 | 414 | static unsigned long clk_pllclk_recalc(struct clk *clk) |
c5b736d0 KH |
415 | { |
416 | u32 ctrl, mult = 1, prediv = 1, postdiv = 1; | |
417 | u8 bypass; | |
418 | struct pll_data *pll = clk->pll_data; | |
de381a91 | 419 | unsigned long rate = clk->rate; |
c5b736d0 | 420 | |
c5b736d0 | 421 | ctrl = __raw_readl(pll->base + PLLCTL); |
de381a91 | 422 | rate = pll->input_rate = clk->parent->rate; |
c5b736d0 KH |
423 | |
424 | if (ctrl & PLLCTL_PLLEN) { | |
425 | bypass = 0; | |
426 | mult = __raw_readl(pll->base + PLLM); | |
fb8fcb89 SP |
427 | if (cpu_is_davinci_dm365()) |
428 | mult = 2 * (mult & PLLM_PLLM_MASK); | |
429 | else | |
430 | mult = (mult & PLLM_PLLM_MASK) + 1; | |
c5b736d0 KH |
431 | } else |
432 | bypass = 1; | |
433 | ||
434 | if (pll->flags & PLL_HAS_PREDIV) { | |
435 | prediv = __raw_readl(pll->base + PREDIV); | |
436 | if (prediv & PLLDIV_EN) | |
d6961e68 | 437 | prediv = (prediv & pll->div_ratio_mask) + 1; |
c5b736d0 KH |
438 | else |
439 | prediv = 1; | |
440 | } | |
441 | ||
442 | /* pre-divider is fixed, but (some?) chips won't report that */ | |
443 | if (cpu_is_davinci_dm355() && pll->num == 1) | |
444 | prediv = 8; | |
445 | ||
446 | if (pll->flags & PLL_HAS_POSTDIV) { | |
447 | postdiv = __raw_readl(pll->base + POSTDIV); | |
448 | if (postdiv & PLLDIV_EN) | |
d6961e68 | 449 | postdiv = (postdiv & pll->div_ratio_mask) + 1; |
c5b736d0 KH |
450 | else |
451 | postdiv = 1; | |
452 | } | |
453 | ||
454 | if (!bypass) { | |
de381a91 SN |
455 | rate /= prediv; |
456 | rate *= mult; | |
457 | rate /= postdiv; | |
c5b736d0 KH |
458 | } |
459 | ||
460 | pr_debug("PLL%d: input = %lu MHz [ ", | |
461 | pll->num, clk->parent->rate / 1000000); | |
462 | if (bypass) | |
463 | pr_debug("bypass "); | |
464 | if (prediv > 1) | |
465 | pr_debug("/ %d ", prediv); | |
466 | if (mult > 1) | |
467 | pr_debug("* %d ", mult); | |
468 | if (postdiv > 1) | |
469 | pr_debug("/ %d ", postdiv); | |
de381a91 SN |
470 | pr_debug("] --> %lu MHz output.\n", rate / 1000000); |
471 | ||
472 | return rate; | |
c5b736d0 KH |
473 | } |
474 | ||
d6a61563 SN |
475 | /** |
476 | * davinci_set_pllrate - set the output rate of a given PLL. | |
477 | * | |
478 | * Note: Currently tested to work with OMAP-L138 only. | |
479 | * | |
480 | * @pll: pll whose rate needs to be changed. | |
481 | * @prediv: The pre divider value. Passing 0 disables the pre-divider. | |
482 | * @pllm: The multiplier value. Passing 0 leads to multiply-by-one. | |
483 | * @postdiv: The post divider value. Passing 0 disables the post-divider. | |
484 | */ | |
485 | int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, | |
486 | unsigned int mult, unsigned int postdiv) | |
487 | { | |
488 | u32 ctrl; | |
489 | unsigned int locktime; | |
3b43cd6f | 490 | unsigned long flags; |
d6a61563 SN |
491 | |
492 | if (pll->base == NULL) | |
493 | return -EINVAL; | |
494 | ||
495 | /* | |
496 | * PLL lock time required per OMAP-L138 datasheet is | |
497 | * (2000 * prediv)/sqrt(pllm) OSCIN cycles. We approximate sqrt(pllm) | |
498 | * as 4 and OSCIN cycle as 25 MHz. | |
499 | */ | |
500 | if (prediv) { | |
501 | locktime = ((2000 * prediv) / 100); | |
502 | prediv = (prediv - 1) | PLLDIV_EN; | |
503 | } else { | |
9a219a9e | 504 | locktime = PLL_LOCK_TIME; |
d6a61563 SN |
505 | } |
506 | if (postdiv) | |
507 | postdiv = (postdiv - 1) | PLLDIV_EN; | |
508 | if (mult) | |
509 | mult = mult - 1; | |
510 | ||
3b43cd6f SN |
511 | /* Protect against simultaneous calls to PLL setting seqeunce */ |
512 | spin_lock_irqsave(&clockfw_lock, flags); | |
513 | ||
d6a61563 SN |
514 | ctrl = __raw_readl(pll->base + PLLCTL); |
515 | ||
516 | /* Switch the PLL to bypass mode */ | |
517 | ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN); | |
518 | __raw_writel(ctrl, pll->base + PLLCTL); | |
519 | ||
9a219a9e | 520 | udelay(PLL_BYPASS_TIME); |
d6a61563 SN |
521 | |
522 | /* Reset and enable PLL */ | |
523 | ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS); | |
524 | __raw_writel(ctrl, pll->base + PLLCTL); | |
525 | ||
526 | if (pll->flags & PLL_HAS_PREDIV) | |
527 | __raw_writel(prediv, pll->base + PREDIV); | |
528 | ||
529 | __raw_writel(mult, pll->base + PLLM); | |
530 | ||
531 | if (pll->flags & PLL_HAS_POSTDIV) | |
532 | __raw_writel(postdiv, pll->base + POSTDIV); | |
533 | ||
9a219a9e | 534 | udelay(PLL_RESET_TIME); |
d6a61563 SN |
535 | |
536 | /* Bring PLL out of reset */ | |
537 | ctrl |= PLLCTL_PLLRST; | |
538 | __raw_writel(ctrl, pll->base + PLLCTL); | |
539 | ||
540 | udelay(locktime); | |
541 | ||
542 | /* Remove PLL from bypass mode */ | |
543 | ctrl |= PLLCTL_PLLEN; | |
544 | __raw_writel(ctrl, pll->base + PLLCTL); | |
545 | ||
3b43cd6f SN |
546 | spin_unlock_irqrestore(&clockfw_lock, flags); |
547 | ||
d6a61563 SN |
548 | return 0; |
549 | } | |
550 | EXPORT_SYMBOL(davinci_set_pllrate); | |
551 | ||
56e580d7 SN |
552 | /** |
553 | * davinci_set_refclk_rate() - Set the reference clock rate | |
554 | * @rate: The new rate. | |
555 | * | |
556 | * Sets the reference clock rate to a given value. This will most likely | |
557 | * result in the entire clock tree getting updated. | |
558 | * | |
559 | * This is used to support boards which use a reference clock different | |
560 | * than that used by default in <soc>.c file. The reference clock rate | |
561 | * should be updated early in the boot process; ideally soon after the | |
562 | * clock tree has been initialized once with the default reference clock | |
563 | * rate (davinci_common_init()). | |
564 | * | |
565 | * Returns 0 on success, error otherwise. | |
566 | */ | |
567 | int davinci_set_refclk_rate(unsigned long rate) | |
568 | { | |
569 | struct clk *refclk; | |
570 | ||
571 | refclk = clk_get(NULL, "ref"); | |
572 | if (IS_ERR(refclk)) { | |
a7ca2bcf | 573 | pr_err("%s: failed to get reference clock\n", __func__); |
56e580d7 SN |
574 | return PTR_ERR(refclk); |
575 | } | |
576 | ||
577 | clk_set_rate(refclk, rate); | |
578 | ||
579 | clk_put(refclk); | |
580 | ||
581 | return 0; | |
582 | } | |
583 | ||
08aca087 | 584 | int __init davinci_clk_init(struct clk_lookup *clocks) |
af47e6bb | 585 | { |
08aca087 | 586 | struct clk_lookup *c; |
c5b736d0 | 587 | struct clk *clk; |
08aca087 | 588 | size_t num_clocks = 0; |
c5b736d0 | 589 | |
08aca087 KH |
590 | for (c = clocks; c->clk; c++) { |
591 | clk = c->clk; | |
c5b736d0 | 592 | |
de381a91 SN |
593 | if (!clk->recalc) { |
594 | ||
595 | /* Check if clock is a PLL */ | |
596 | if (clk->pll_data) | |
597 | clk->recalc = clk_pllclk_recalc; | |
598 | ||
599 | /* Else, if it is a PLL-derived clock */ | |
600 | else if (clk->flags & CLK_PLL) | |
601 | clk->recalc = clk_sysclk_recalc; | |
602 | ||
603 | /* Otherwise, it is a leaf clock (PSC clock) */ | |
604 | else if (clk->parent) | |
605 | clk->recalc = clk_leafclk_recalc; | |
606 | } | |
c5b736d0 | 607 | |
e4c822c7 CC |
608 | if (clk->pll_data) { |
609 | struct pll_data *pll = clk->pll_data; | |
610 | ||
611 | if (!pll->div_ratio_mask) | |
612 | pll->div_ratio_mask = PLLDIV_RATIO_MASK; | |
613 | ||
614 | if (pll->phys_base && !pll->base) { | |
615 | pll->base = ioremap(pll->phys_base, SZ_4K); | |
616 | WARN_ON(!pll->base); | |
617 | } | |
618 | } | |
d6961e68 | 619 | |
de381a91 SN |
620 | if (clk->recalc) |
621 | clk->rate = clk->recalc(clk); | |
c5b736d0 KH |
622 | |
623 | if (clk->lpsc) | |
624 | clk->flags |= CLK_PSC; | |
625 | ||
af47e6bb RT |
626 | if (clk->flags & PSC_LRST) |
627 | clk->reset = davinci_clk_reset; | |
628 | ||
c5b736d0 | 629 | clk_register(clk); |
08aca087 | 630 | num_clocks++; |
c5b736d0 KH |
631 | |
632 | /* Turn on clocks that Linux doesn't otherwise manage */ | |
633 | if (clk->flags & ALWAYS_ENABLED) | |
634 | clk_enable(clk); | |
3e062b07 VB |
635 | } |
636 | ||
08aca087 KH |
637 | clkdev_add_table(clocks, num_clocks); |
638 | ||
3e062b07 VB |
639 | return 0; |
640 | } | |
641 | ||
2f72e8dc | 642 | #ifdef CONFIG_DEBUG_FS |
3e062b07 | 643 | |
2f72e8dc SN |
644 | #include <linux/debugfs.h> |
645 | #include <linux/seq_file.h> | |
3e062b07 | 646 | |
c5b736d0 KH |
647 | #define CLKNAME_MAX 10 /* longest clock name */ |
648 | #define NEST_DELTA 2 | |
649 | #define NEST_MAX 4 | |
650 | ||
651 | static void | |
652 | dump_clock(struct seq_file *s, unsigned nest, struct clk *parent) | |
3e062b07 | 653 | { |
c5b736d0 KH |
654 | char *state; |
655 | char buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX]; | |
656 | struct clk *clk; | |
657 | unsigned i; | |
658 | ||
659 | if (parent->flags & CLK_PLL) | |
660 | state = "pll"; | |
661 | else if (parent->flags & CLK_PSC) | |
662 | state = "psc"; | |
663 | else | |
664 | state = ""; | |
665 | ||
666 | /* <nest spaces> name <pad to end> */ | |
667 | memset(buf, ' ', sizeof(buf) - 1); | |
668 | buf[sizeof(buf) - 1] = 0; | |
669 | i = strlen(parent->name); | |
670 | memcpy(buf + nest, parent->name, | |
671 | min(i, (unsigned)(sizeof(buf) - 1 - nest))); | |
672 | ||
673 | seq_printf(s, "%s users=%2d %-3s %9ld Hz\n", | |
674 | buf, parent->usecount, state, clk_get_rate(parent)); | |
675 | /* REVISIT show device associations too */ | |
676 | ||
677 | /* cost is now small, but not linear... */ | |
f02bf3b3 SN |
678 | list_for_each_entry(clk, &parent->children, childnode) { |
679 | dump_clock(s, nest + NEST_DELTA, clk); | |
c5b736d0 KH |
680 | } |
681 | } | |
3e062b07 | 682 | |
c5b736d0 KH |
683 | static int davinci_ck_show(struct seq_file *m, void *v) |
684 | { | |
f979aa6e SN |
685 | struct clk *clk; |
686 | ||
687 | /* | |
688 | * Show clock tree; We trust nonzero usecounts equate to PSC enables... | |
c5b736d0 KH |
689 | */ |
690 | mutex_lock(&clocks_mutex); | |
f979aa6e SN |
691 | list_for_each_entry(clk, &clocks, node) |
692 | if (!clk->parent) | |
693 | dump_clock(m, 0, clk); | |
c5b736d0 | 694 | mutex_unlock(&clocks_mutex); |
3e062b07 VB |
695 | |
696 | return 0; | |
697 | } | |
698 | ||
3e062b07 VB |
699 | static int davinci_ck_open(struct inode *inode, struct file *file) |
700 | { | |
2f72e8dc | 701 | return single_open(file, davinci_ck_show, NULL); |
3e062b07 VB |
702 | } |
703 | ||
2f72e8dc | 704 | static const struct file_operations davinci_ck_operations = { |
3e062b07 VB |
705 | .open = davinci_ck_open, |
706 | .read = seq_read, | |
707 | .llseek = seq_lseek, | |
2f72e8dc | 708 | .release = single_release, |
3e062b07 VB |
709 | }; |
710 | ||
2f72e8dc | 711 | static int __init davinci_clk_debugfs_init(void) |
3e062b07 | 712 | { |
2f72e8dc SN |
713 | debugfs_create_file("davinci_clocks", S_IFREG | S_IRUGO, NULL, NULL, |
714 | &davinci_ck_operations); | |
3e062b07 VB |
715 | return 0; |
716 | ||
717 | } | |
2f72e8dc SN |
718 | device_initcall(davinci_clk_debugfs_init); |
719 | #endif /* CONFIG_DEBUG_FS */ |