Commit | Line | Data |
---|---|---|
3e062b07 | 1 | /* |
c5b736d0 | 2 | * Clock and PLL control for DaVinci devices |
3e062b07 | 3 | * |
c5b736d0 KH |
4 | * Copyright (C) 2006-2007 Texas Instruments. |
5 | * Copyright (C) 2008-2009 Deep Root Systems, LLC | |
3e062b07 VB |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/errno.h> | |
c5b736d0 | 17 | #include <linux/clk.h> |
3e062b07 VB |
18 | #include <linux/err.h> |
19 | #include <linux/mutex.h> | |
fced80c7 | 20 | #include <linux/io.h> |
d6a61563 | 21 | #include <linux/delay.h> |
3e062b07 | 22 | |
a09e64fb | 23 | #include <mach/hardware.h> |
3e062b07 | 24 | |
a09e64fb | 25 | #include <mach/psc.h> |
c5b736d0 | 26 | #include <mach/cputype.h> |
3e062b07 VB |
27 | #include "clock.h" |
28 | ||
3e062b07 VB |
29 | static LIST_HEAD(clocks); |
30 | static DEFINE_MUTEX(clocks_mutex); | |
31 | static DEFINE_SPINLOCK(clockfw_lock); | |
32 | ||
c5b736d0 | 33 | static unsigned psc_domain(struct clk *clk) |
3e062b07 | 34 | { |
c5b736d0 KH |
35 | return (clk->flags & PSC_DSP) |
36 | ? DAVINCI_GPSC_DSPDOMAIN | |
37 | : DAVINCI_GPSC_ARMDOMAIN; | |
3e062b07 | 38 | } |
3e062b07 | 39 | |
c5b736d0 | 40 | static void __clk_enable(struct clk *clk) |
3e062b07 | 41 | { |
c5b736d0 KH |
42 | if (clk->parent) |
43 | __clk_enable(clk->parent); | |
44 | if (clk->usecount++ == 0 && (clk->flags & CLK_PSC)) | |
789a785e | 45 | davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, 1); |
3e062b07 VB |
46 | } |
47 | ||
48 | static void __clk_disable(struct clk *clk) | |
49 | { | |
c5b736d0 | 50 | if (WARN_ON(clk->usecount == 0)) |
3e062b07 | 51 | return; |
679f9218 C |
52 | if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) && |
53 | (clk->flags & CLK_PSC)) | |
789a785e | 54 | davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, 0); |
c5b736d0 KH |
55 | if (clk->parent) |
56 | __clk_disable(clk->parent); | |
3e062b07 VB |
57 | } |
58 | ||
59 | int clk_enable(struct clk *clk) | |
60 | { | |
61 | unsigned long flags; | |
3e062b07 VB |
62 | |
63 | if (clk == NULL || IS_ERR(clk)) | |
64 | return -EINVAL; | |
65 | ||
c5b736d0 KH |
66 | spin_lock_irqsave(&clockfw_lock, flags); |
67 | __clk_enable(clk); | |
68 | spin_unlock_irqrestore(&clockfw_lock, flags); | |
3e062b07 | 69 | |
c5b736d0 | 70 | return 0; |
3e062b07 VB |
71 | } |
72 | EXPORT_SYMBOL(clk_enable); | |
73 | ||
74 | void clk_disable(struct clk *clk) | |
75 | { | |
76 | unsigned long flags; | |
77 | ||
78 | if (clk == NULL || IS_ERR(clk)) | |
79 | return; | |
80 | ||
c5b736d0 KH |
81 | spin_lock_irqsave(&clockfw_lock, flags); |
82 | __clk_disable(clk); | |
83 | spin_unlock_irqrestore(&clockfw_lock, flags); | |
3e062b07 VB |
84 | } |
85 | EXPORT_SYMBOL(clk_disable); | |
86 | ||
87 | unsigned long clk_get_rate(struct clk *clk) | |
88 | { | |
89 | if (clk == NULL || IS_ERR(clk)) | |
90 | return -EINVAL; | |
91 | ||
c5b736d0 | 92 | return clk->rate; |
3e062b07 VB |
93 | } |
94 | EXPORT_SYMBOL(clk_get_rate); | |
95 | ||
96 | long clk_round_rate(struct clk *clk, unsigned long rate) | |
97 | { | |
98 | if (clk == NULL || IS_ERR(clk)) | |
99 | return -EINVAL; | |
100 | ||
d6a61563 SN |
101 | if (clk->round_rate) |
102 | return clk->round_rate(clk, rate); | |
103 | ||
c5b736d0 | 104 | return clk->rate; |
3e062b07 VB |
105 | } |
106 | EXPORT_SYMBOL(clk_round_rate); | |
107 | ||
d6a61563 SN |
108 | /* Propagate rate to children */ |
109 | static void propagate_rate(struct clk *root) | |
110 | { | |
111 | struct clk *clk; | |
112 | ||
113 | list_for_each_entry(clk, &root->children, childnode) { | |
114 | if (clk->recalc) | |
115 | clk->rate = clk->recalc(clk); | |
116 | propagate_rate(clk); | |
117 | } | |
118 | } | |
119 | ||
3e062b07 VB |
120 | int clk_set_rate(struct clk *clk, unsigned long rate) |
121 | { | |
d6a61563 SN |
122 | unsigned long flags; |
123 | int ret = -EINVAL; | |
124 | ||
3e062b07 | 125 | if (clk == NULL || IS_ERR(clk)) |
d6a61563 SN |
126 | return ret; |
127 | ||
128 | spin_lock_irqsave(&clockfw_lock, flags); | |
129 | if (clk->set_rate) | |
130 | ret = clk->set_rate(clk, rate); | |
131 | if (ret == 0) { | |
132 | if (clk->recalc) | |
133 | clk->rate = clk->recalc(clk); | |
134 | propagate_rate(clk); | |
135 | } | |
136 | spin_unlock_irqrestore(&clockfw_lock, flags); | |
3e062b07 | 137 | |
d6a61563 | 138 | return ret; |
3e062b07 VB |
139 | } |
140 | EXPORT_SYMBOL(clk_set_rate); | |
141 | ||
b82a51e8 SN |
142 | int clk_set_parent(struct clk *clk, struct clk *parent) |
143 | { | |
144 | unsigned long flags; | |
145 | ||
146 | if (clk == NULL || IS_ERR(clk)) | |
147 | return -EINVAL; | |
148 | ||
149 | /* Cannot change parent on enabled clock */ | |
150 | if (WARN_ON(clk->usecount)) | |
151 | return -EINVAL; | |
152 | ||
153 | mutex_lock(&clocks_mutex); | |
154 | clk->parent = parent; | |
155 | list_del_init(&clk->childnode); | |
156 | list_add(&clk->childnode, &clk->parent->children); | |
157 | mutex_unlock(&clocks_mutex); | |
158 | ||
159 | spin_lock_irqsave(&clockfw_lock, flags); | |
160 | if (clk->recalc) | |
161 | clk->rate = clk->recalc(clk); | |
162 | propagate_rate(clk); | |
163 | spin_unlock_irqrestore(&clockfw_lock, flags); | |
164 | ||
165 | return 0; | |
166 | } | |
167 | EXPORT_SYMBOL(clk_set_parent); | |
168 | ||
3e062b07 VB |
169 | int clk_register(struct clk *clk) |
170 | { | |
171 | if (clk == NULL || IS_ERR(clk)) | |
172 | return -EINVAL; | |
173 | ||
c5b736d0 KH |
174 | if (WARN(clk->parent && !clk->parent->rate, |
175 | "CLK: %s parent %s has no rate!\n", | |
176 | clk->name, clk->parent->name)) | |
177 | return -EINVAL; | |
178 | ||
f02bf3b3 SN |
179 | INIT_LIST_HEAD(&clk->children); |
180 | ||
3e062b07 | 181 | mutex_lock(&clocks_mutex); |
c5b736d0 | 182 | list_add_tail(&clk->node, &clocks); |
f02bf3b3 SN |
183 | if (clk->parent) |
184 | list_add_tail(&clk->childnode, &clk->parent->children); | |
3e062b07 VB |
185 | mutex_unlock(&clocks_mutex); |
186 | ||
c5b736d0 KH |
187 | /* If rate is already set, use it */ |
188 | if (clk->rate) | |
189 | return 0; | |
190 | ||
de381a91 SN |
191 | /* Else, see if there is a way to calculate it */ |
192 | if (clk->recalc) | |
193 | clk->rate = clk->recalc(clk); | |
194 | ||
c5b736d0 | 195 | /* Otherwise, default to parent rate */ |
de381a91 | 196 | else if (clk->parent) |
c5b736d0 KH |
197 | clk->rate = clk->parent->rate; |
198 | ||
3e062b07 VB |
199 | return 0; |
200 | } | |
201 | EXPORT_SYMBOL(clk_register); | |
202 | ||
203 | void clk_unregister(struct clk *clk) | |
204 | { | |
205 | if (clk == NULL || IS_ERR(clk)) | |
206 | return; | |
207 | ||
208 | mutex_lock(&clocks_mutex); | |
209 | list_del(&clk->node); | |
f02bf3b3 | 210 | list_del(&clk->childnode); |
3e062b07 VB |
211 | mutex_unlock(&clocks_mutex); |
212 | } | |
213 | EXPORT_SYMBOL(clk_unregister); | |
214 | ||
c5b736d0 KH |
215 | #ifdef CONFIG_DAVINCI_RESET_CLOCKS |
216 | /* | |
217 | * Disable any unused clocks left on by the bootloader | |
218 | */ | |
219 | static int __init clk_disable_unused(void) | |
220 | { | |
221 | struct clk *ck; | |
222 | ||
223 | spin_lock_irq(&clockfw_lock); | |
224 | list_for_each_entry(ck, &clocks, node) { | |
225 | if (ck->usecount > 0) | |
226 | continue; | |
227 | if (!(ck->flags & CLK_PSC)) | |
228 | continue; | |
229 | ||
230 | /* ignore if in Disabled or SwRstDisable states */ | |
789a785e | 231 | if (!davinci_psc_is_clk_active(ck->gpsc, ck->lpsc)) |
c5b736d0 KH |
232 | continue; |
233 | ||
234 | pr_info("Clocks: disable unused %s\n", ck->name); | |
789a785e | 235 | davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc, 0); |
3e062b07 | 236 | } |
c5b736d0 KH |
237 | spin_unlock_irq(&clockfw_lock); |
238 | ||
239 | return 0; | |
240 | } | |
241 | late_initcall(clk_disable_unused); | |
242 | #endif | |
3e062b07 | 243 | |
de381a91 | 244 | static unsigned long clk_sysclk_recalc(struct clk *clk) |
3e062b07 | 245 | { |
c5b736d0 KH |
246 | u32 v, plldiv; |
247 | struct pll_data *pll; | |
de381a91 | 248 | unsigned long rate = clk->rate; |
c5b736d0 KH |
249 | |
250 | /* If this is the PLL base clock, no more calculations needed */ | |
251 | if (clk->pll_data) | |
de381a91 | 252 | return rate; |
c5b736d0 KH |
253 | |
254 | if (WARN_ON(!clk->parent)) | |
de381a91 | 255 | return rate; |
c5b736d0 | 256 | |
de381a91 | 257 | rate = clk->parent->rate; |
c5b736d0 KH |
258 | |
259 | /* Otherwise, the parent must be a PLL */ | |
260 | if (WARN_ON(!clk->parent->pll_data)) | |
de381a91 | 261 | return rate; |
c5b736d0 KH |
262 | |
263 | pll = clk->parent->pll_data; | |
264 | ||
265 | /* If pre-PLL, source clock is before the multiplier and divider(s) */ | |
266 | if (clk->flags & PRE_PLL) | |
de381a91 | 267 | rate = pll->input_rate; |
c5b736d0 KH |
268 | |
269 | if (!clk->div_reg) | |
de381a91 | 270 | return rate; |
c5b736d0 KH |
271 | |
272 | v = __raw_readl(pll->base + clk->div_reg); | |
273 | if (v & PLLDIV_EN) { | |
274 | plldiv = (v & PLLDIV_RATIO_MASK) + 1; | |
275 | if (plldiv) | |
de381a91 | 276 | rate /= plldiv; |
c5b736d0 | 277 | } |
de381a91 SN |
278 | |
279 | return rate; | |
280 | } | |
281 | ||
282 | static unsigned long clk_leafclk_recalc(struct clk *clk) | |
283 | { | |
284 | if (WARN_ON(!clk->parent)) | |
285 | return clk->rate; | |
286 | ||
287 | return clk->parent->rate; | |
c5b736d0 KH |
288 | } |
289 | ||
de381a91 | 290 | static unsigned long clk_pllclk_recalc(struct clk *clk) |
c5b736d0 KH |
291 | { |
292 | u32 ctrl, mult = 1, prediv = 1, postdiv = 1; | |
293 | u8 bypass; | |
294 | struct pll_data *pll = clk->pll_data; | |
de381a91 | 295 | unsigned long rate = clk->rate; |
c5b736d0 KH |
296 | |
297 | pll->base = IO_ADDRESS(pll->phys_base); | |
298 | ctrl = __raw_readl(pll->base + PLLCTL); | |
de381a91 | 299 | rate = pll->input_rate = clk->parent->rate; |
c5b736d0 KH |
300 | |
301 | if (ctrl & PLLCTL_PLLEN) { | |
302 | bypass = 0; | |
303 | mult = __raw_readl(pll->base + PLLM); | |
fb8fcb89 SP |
304 | if (cpu_is_davinci_dm365()) |
305 | mult = 2 * (mult & PLLM_PLLM_MASK); | |
306 | else | |
307 | mult = (mult & PLLM_PLLM_MASK) + 1; | |
c5b736d0 KH |
308 | } else |
309 | bypass = 1; | |
310 | ||
311 | if (pll->flags & PLL_HAS_PREDIV) { | |
312 | prediv = __raw_readl(pll->base + PREDIV); | |
313 | if (prediv & PLLDIV_EN) | |
314 | prediv = (prediv & PLLDIV_RATIO_MASK) + 1; | |
315 | else | |
316 | prediv = 1; | |
317 | } | |
318 | ||
319 | /* pre-divider is fixed, but (some?) chips won't report that */ | |
320 | if (cpu_is_davinci_dm355() && pll->num == 1) | |
321 | prediv = 8; | |
322 | ||
323 | if (pll->flags & PLL_HAS_POSTDIV) { | |
324 | postdiv = __raw_readl(pll->base + POSTDIV); | |
325 | if (postdiv & PLLDIV_EN) | |
326 | postdiv = (postdiv & PLLDIV_RATIO_MASK) + 1; | |
327 | else | |
328 | postdiv = 1; | |
329 | } | |
330 | ||
331 | if (!bypass) { | |
de381a91 SN |
332 | rate /= prediv; |
333 | rate *= mult; | |
334 | rate /= postdiv; | |
c5b736d0 KH |
335 | } |
336 | ||
337 | pr_debug("PLL%d: input = %lu MHz [ ", | |
338 | pll->num, clk->parent->rate / 1000000); | |
339 | if (bypass) | |
340 | pr_debug("bypass "); | |
341 | if (prediv > 1) | |
342 | pr_debug("/ %d ", prediv); | |
343 | if (mult > 1) | |
344 | pr_debug("* %d ", mult); | |
345 | if (postdiv > 1) | |
346 | pr_debug("/ %d ", postdiv); | |
de381a91 SN |
347 | pr_debug("] --> %lu MHz output.\n", rate / 1000000); |
348 | ||
349 | return rate; | |
c5b736d0 KH |
350 | } |
351 | ||
d6a61563 SN |
352 | /** |
353 | * davinci_set_pllrate - set the output rate of a given PLL. | |
354 | * | |
355 | * Note: Currently tested to work with OMAP-L138 only. | |
356 | * | |
357 | * @pll: pll whose rate needs to be changed. | |
358 | * @prediv: The pre divider value. Passing 0 disables the pre-divider. | |
359 | * @pllm: The multiplier value. Passing 0 leads to multiply-by-one. | |
360 | * @postdiv: The post divider value. Passing 0 disables the post-divider. | |
361 | */ | |
362 | int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, | |
363 | unsigned int mult, unsigned int postdiv) | |
364 | { | |
365 | u32 ctrl; | |
366 | unsigned int locktime; | |
367 | ||
368 | if (pll->base == NULL) | |
369 | return -EINVAL; | |
370 | ||
371 | /* | |
372 | * PLL lock time required per OMAP-L138 datasheet is | |
373 | * (2000 * prediv)/sqrt(pllm) OSCIN cycles. We approximate sqrt(pllm) | |
374 | * as 4 and OSCIN cycle as 25 MHz. | |
375 | */ | |
376 | if (prediv) { | |
377 | locktime = ((2000 * prediv) / 100); | |
378 | prediv = (prediv - 1) | PLLDIV_EN; | |
379 | } else { | |
9a219a9e | 380 | locktime = PLL_LOCK_TIME; |
d6a61563 SN |
381 | } |
382 | if (postdiv) | |
383 | postdiv = (postdiv - 1) | PLLDIV_EN; | |
384 | if (mult) | |
385 | mult = mult - 1; | |
386 | ||
387 | ctrl = __raw_readl(pll->base + PLLCTL); | |
388 | ||
389 | /* Switch the PLL to bypass mode */ | |
390 | ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN); | |
391 | __raw_writel(ctrl, pll->base + PLLCTL); | |
392 | ||
9a219a9e | 393 | udelay(PLL_BYPASS_TIME); |
d6a61563 SN |
394 | |
395 | /* Reset and enable PLL */ | |
396 | ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS); | |
397 | __raw_writel(ctrl, pll->base + PLLCTL); | |
398 | ||
399 | if (pll->flags & PLL_HAS_PREDIV) | |
400 | __raw_writel(prediv, pll->base + PREDIV); | |
401 | ||
402 | __raw_writel(mult, pll->base + PLLM); | |
403 | ||
404 | if (pll->flags & PLL_HAS_POSTDIV) | |
405 | __raw_writel(postdiv, pll->base + POSTDIV); | |
406 | ||
9a219a9e | 407 | udelay(PLL_RESET_TIME); |
d6a61563 SN |
408 | |
409 | /* Bring PLL out of reset */ | |
410 | ctrl |= PLLCTL_PLLRST; | |
411 | __raw_writel(ctrl, pll->base + PLLCTL); | |
412 | ||
413 | udelay(locktime); | |
414 | ||
415 | /* Remove PLL from bypass mode */ | |
416 | ctrl |= PLLCTL_PLLEN; | |
417 | __raw_writel(ctrl, pll->base + PLLCTL); | |
418 | ||
419 | return 0; | |
420 | } | |
421 | EXPORT_SYMBOL(davinci_set_pllrate); | |
422 | ||
c5b736d0 KH |
423 | int __init davinci_clk_init(struct davinci_clk *clocks) |
424 | { | |
425 | struct davinci_clk *c; | |
426 | struct clk *clk; | |
427 | ||
428 | for (c = clocks; c->lk.clk; c++) { | |
429 | clk = c->lk.clk; | |
430 | ||
de381a91 SN |
431 | if (!clk->recalc) { |
432 | ||
433 | /* Check if clock is a PLL */ | |
434 | if (clk->pll_data) | |
435 | clk->recalc = clk_pllclk_recalc; | |
436 | ||
437 | /* Else, if it is a PLL-derived clock */ | |
438 | else if (clk->flags & CLK_PLL) | |
439 | clk->recalc = clk_sysclk_recalc; | |
440 | ||
441 | /* Otherwise, it is a leaf clock (PSC clock) */ | |
442 | else if (clk->parent) | |
443 | clk->recalc = clk_leafclk_recalc; | |
444 | } | |
c5b736d0 | 445 | |
de381a91 SN |
446 | if (clk->recalc) |
447 | clk->rate = clk->recalc(clk); | |
c5b736d0 KH |
448 | |
449 | if (clk->lpsc) | |
450 | clk->flags |= CLK_PSC; | |
451 | ||
452 | clkdev_add(&c->lk); | |
453 | clk_register(clk); | |
454 | ||
455 | /* Turn on clocks that Linux doesn't otherwise manage */ | |
456 | if (clk->flags & ALWAYS_ENABLED) | |
457 | clk_enable(clk); | |
3e062b07 VB |
458 | } |
459 | ||
460 | return 0; | |
461 | } | |
462 | ||
2f72e8dc | 463 | #ifdef CONFIG_DEBUG_FS |
3e062b07 | 464 | |
2f72e8dc SN |
465 | #include <linux/debugfs.h> |
466 | #include <linux/seq_file.h> | |
3e062b07 | 467 | |
c5b736d0 KH |
468 | #define CLKNAME_MAX 10 /* longest clock name */ |
469 | #define NEST_DELTA 2 | |
470 | #define NEST_MAX 4 | |
471 | ||
472 | static void | |
473 | dump_clock(struct seq_file *s, unsigned nest, struct clk *parent) | |
3e062b07 | 474 | { |
c5b736d0 KH |
475 | char *state; |
476 | char buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX]; | |
477 | struct clk *clk; | |
478 | unsigned i; | |
479 | ||
480 | if (parent->flags & CLK_PLL) | |
481 | state = "pll"; | |
482 | else if (parent->flags & CLK_PSC) | |
483 | state = "psc"; | |
484 | else | |
485 | state = ""; | |
486 | ||
487 | /* <nest spaces> name <pad to end> */ | |
488 | memset(buf, ' ', sizeof(buf) - 1); | |
489 | buf[sizeof(buf) - 1] = 0; | |
490 | i = strlen(parent->name); | |
491 | memcpy(buf + nest, parent->name, | |
492 | min(i, (unsigned)(sizeof(buf) - 1 - nest))); | |
493 | ||
494 | seq_printf(s, "%s users=%2d %-3s %9ld Hz\n", | |
495 | buf, parent->usecount, state, clk_get_rate(parent)); | |
496 | /* REVISIT show device associations too */ | |
497 | ||
498 | /* cost is now small, but not linear... */ | |
f02bf3b3 SN |
499 | list_for_each_entry(clk, &parent->children, childnode) { |
500 | dump_clock(s, nest + NEST_DELTA, clk); | |
c5b736d0 KH |
501 | } |
502 | } | |
3e062b07 | 503 | |
c5b736d0 KH |
504 | static int davinci_ck_show(struct seq_file *m, void *v) |
505 | { | |
f979aa6e SN |
506 | struct clk *clk; |
507 | ||
508 | /* | |
509 | * Show clock tree; We trust nonzero usecounts equate to PSC enables... | |
c5b736d0 KH |
510 | */ |
511 | mutex_lock(&clocks_mutex); | |
f979aa6e SN |
512 | list_for_each_entry(clk, &clocks, node) |
513 | if (!clk->parent) | |
514 | dump_clock(m, 0, clk); | |
c5b736d0 | 515 | mutex_unlock(&clocks_mutex); |
3e062b07 VB |
516 | |
517 | return 0; | |
518 | } | |
519 | ||
3e062b07 VB |
520 | static int davinci_ck_open(struct inode *inode, struct file *file) |
521 | { | |
2f72e8dc | 522 | return single_open(file, davinci_ck_show, NULL); |
3e062b07 VB |
523 | } |
524 | ||
2f72e8dc | 525 | static const struct file_operations davinci_ck_operations = { |
3e062b07 VB |
526 | .open = davinci_ck_open, |
527 | .read = seq_read, | |
528 | .llseek = seq_lseek, | |
2f72e8dc | 529 | .release = single_release, |
3e062b07 VB |
530 | }; |
531 | ||
2f72e8dc | 532 | static int __init davinci_clk_debugfs_init(void) |
3e062b07 | 533 | { |
2f72e8dc SN |
534 | debugfs_create_file("davinci_clocks", S_IFREG | S_IRUGO, NULL, NULL, |
535 | &davinci_ck_operations); | |
3e062b07 VB |
536 | return 0; |
537 | ||
538 | } | |
2f72e8dc SN |
539 | device_initcall(davinci_clk_debugfs_init); |
540 | #endif /* CONFIG_DEBUG_FS */ |