Commit | Line | Data |
---|---|---|
3e062b07 | 1 | /* |
c5b736d0 | 2 | * Clock and PLL control for DaVinci devices |
3e062b07 | 3 | * |
c5b736d0 KH |
4 | * Copyright (C) 2006-2007 Texas Instruments. |
5 | * Copyright (C) 2008-2009 Deep Root Systems, LLC | |
3e062b07 VB |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/errno.h> | |
c5b736d0 | 17 | #include <linux/clk.h> |
3e062b07 VB |
18 | #include <linux/err.h> |
19 | #include <linux/mutex.h> | |
fced80c7 | 20 | #include <linux/io.h> |
d6a61563 | 21 | #include <linux/delay.h> |
3e062b07 | 22 | |
a09e64fb | 23 | #include <mach/hardware.h> |
3e062b07 | 24 | |
28552c2e | 25 | #include <mach/clock.h> |
a09e64fb | 26 | #include <mach/psc.h> |
c5b736d0 | 27 | #include <mach/cputype.h> |
3e062b07 VB |
28 | #include "clock.h" |
29 | ||
3e062b07 VB |
30 | static LIST_HEAD(clocks); |
31 | static DEFINE_MUTEX(clocks_mutex); | |
32 | static DEFINE_SPINLOCK(clockfw_lock); | |
33 | ||
c5b736d0 | 34 | static void __clk_enable(struct clk *clk) |
3e062b07 | 35 | { |
c5b736d0 KH |
36 | if (clk->parent) |
37 | __clk_enable(clk->parent); | |
38 | if (clk->usecount++ == 0 && (clk->flags & CLK_PSC)) | |
12221d43 | 39 | davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc, |
a51ca38b | 40 | true, clk->flags); |
3e062b07 VB |
41 | } |
42 | ||
43 | static void __clk_disable(struct clk *clk) | |
44 | { | |
c5b736d0 | 45 | if (WARN_ON(clk->usecount == 0)) |
3e062b07 | 46 | return; |
679f9218 C |
47 | if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) && |
48 | (clk->flags & CLK_PSC)) | |
12221d43 | 49 | davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc, |
a51ca38b | 50 | false, clk->flags); |
c5b736d0 KH |
51 | if (clk->parent) |
52 | __clk_disable(clk->parent); | |
3e062b07 VB |
53 | } |
54 | ||
af47e6bb RT |
55 | int davinci_clk_reset(struct clk *clk, bool reset) |
56 | { | |
57 | unsigned long flags; | |
58 | ||
59 | if (clk == NULL || IS_ERR(clk)) | |
60 | return -EINVAL; | |
61 | ||
62 | spin_lock_irqsave(&clockfw_lock, flags); | |
63 | if (clk->flags & CLK_PSC) | |
64 | davinci_psc_reset(clk->gpsc, clk->lpsc, reset); | |
65 | spin_unlock_irqrestore(&clockfw_lock, flags); | |
66 | ||
67 | return 0; | |
68 | } | |
69 | EXPORT_SYMBOL(davinci_clk_reset); | |
70 | ||
71 | int davinci_clk_reset_assert(struct clk *clk) | |
72 | { | |
73 | if (clk == NULL || IS_ERR(clk) || !clk->reset) | |
74 | return -EINVAL; | |
75 | ||
76 | return clk->reset(clk, true); | |
77 | } | |
78 | EXPORT_SYMBOL(davinci_clk_reset_assert); | |
79 | ||
80 | int davinci_clk_reset_deassert(struct clk *clk) | |
81 | { | |
82 | if (clk == NULL || IS_ERR(clk) || !clk->reset) | |
83 | return -EINVAL; | |
84 | ||
85 | return clk->reset(clk, false); | |
86 | } | |
87 | EXPORT_SYMBOL(davinci_clk_reset_deassert); | |
88 | ||
3e062b07 VB |
89 | int clk_enable(struct clk *clk) |
90 | { | |
91 | unsigned long flags; | |
3e062b07 VB |
92 | |
93 | if (clk == NULL || IS_ERR(clk)) | |
94 | return -EINVAL; | |
95 | ||
c5b736d0 KH |
96 | spin_lock_irqsave(&clockfw_lock, flags); |
97 | __clk_enable(clk); | |
98 | spin_unlock_irqrestore(&clockfw_lock, flags); | |
3e062b07 | 99 | |
c5b736d0 | 100 | return 0; |
3e062b07 VB |
101 | } |
102 | EXPORT_SYMBOL(clk_enable); | |
103 | ||
104 | void clk_disable(struct clk *clk) | |
105 | { | |
106 | unsigned long flags; | |
107 | ||
108 | if (clk == NULL || IS_ERR(clk)) | |
109 | return; | |
110 | ||
c5b736d0 KH |
111 | spin_lock_irqsave(&clockfw_lock, flags); |
112 | __clk_disable(clk); | |
113 | spin_unlock_irqrestore(&clockfw_lock, flags); | |
3e062b07 VB |
114 | } |
115 | EXPORT_SYMBOL(clk_disable); | |
116 | ||
117 | unsigned long clk_get_rate(struct clk *clk) | |
118 | { | |
119 | if (clk == NULL || IS_ERR(clk)) | |
120 | return -EINVAL; | |
121 | ||
c5b736d0 | 122 | return clk->rate; |
3e062b07 VB |
123 | } |
124 | EXPORT_SYMBOL(clk_get_rate); | |
125 | ||
126 | long clk_round_rate(struct clk *clk, unsigned long rate) | |
127 | { | |
128 | if (clk == NULL || IS_ERR(clk)) | |
129 | return -EINVAL; | |
130 | ||
d6a61563 SN |
131 | if (clk->round_rate) |
132 | return clk->round_rate(clk, rate); | |
133 | ||
c5b736d0 | 134 | return clk->rate; |
3e062b07 VB |
135 | } |
136 | EXPORT_SYMBOL(clk_round_rate); | |
137 | ||
d6a61563 SN |
138 | /* Propagate rate to children */ |
139 | static void propagate_rate(struct clk *root) | |
140 | { | |
141 | struct clk *clk; | |
142 | ||
143 | list_for_each_entry(clk, &root->children, childnode) { | |
144 | if (clk->recalc) | |
145 | clk->rate = clk->recalc(clk); | |
146 | propagate_rate(clk); | |
147 | } | |
148 | } | |
149 | ||
3e062b07 VB |
150 | int clk_set_rate(struct clk *clk, unsigned long rate) |
151 | { | |
d6a61563 SN |
152 | unsigned long flags; |
153 | int ret = -EINVAL; | |
154 | ||
3e062b07 | 155 | if (clk == NULL || IS_ERR(clk)) |
d6a61563 SN |
156 | return ret; |
157 | ||
d6a61563 SN |
158 | if (clk->set_rate) |
159 | ret = clk->set_rate(clk, rate); | |
3b43cd6f SN |
160 | |
161 | spin_lock_irqsave(&clockfw_lock, flags); | |
d6a61563 SN |
162 | if (ret == 0) { |
163 | if (clk->recalc) | |
164 | clk->rate = clk->recalc(clk); | |
165 | propagate_rate(clk); | |
166 | } | |
167 | spin_unlock_irqrestore(&clockfw_lock, flags); | |
3e062b07 | 168 | |
d6a61563 | 169 | return ret; |
3e062b07 VB |
170 | } |
171 | EXPORT_SYMBOL(clk_set_rate); | |
172 | ||
b82a51e8 SN |
173 | int clk_set_parent(struct clk *clk, struct clk *parent) |
174 | { | |
175 | unsigned long flags; | |
176 | ||
177 | if (clk == NULL || IS_ERR(clk)) | |
178 | return -EINVAL; | |
179 | ||
180 | /* Cannot change parent on enabled clock */ | |
181 | if (WARN_ON(clk->usecount)) | |
182 | return -EINVAL; | |
183 | ||
184 | mutex_lock(&clocks_mutex); | |
185 | clk->parent = parent; | |
186 | list_del_init(&clk->childnode); | |
187 | list_add(&clk->childnode, &clk->parent->children); | |
188 | mutex_unlock(&clocks_mutex); | |
189 | ||
190 | spin_lock_irqsave(&clockfw_lock, flags); | |
191 | if (clk->recalc) | |
192 | clk->rate = clk->recalc(clk); | |
193 | propagate_rate(clk); | |
194 | spin_unlock_irqrestore(&clockfw_lock, flags); | |
195 | ||
196 | return 0; | |
197 | } | |
198 | EXPORT_SYMBOL(clk_set_parent); | |
199 | ||
3e062b07 VB |
200 | int clk_register(struct clk *clk) |
201 | { | |
202 | if (clk == NULL || IS_ERR(clk)) | |
203 | return -EINVAL; | |
204 | ||
c5b736d0 KH |
205 | if (WARN(clk->parent && !clk->parent->rate, |
206 | "CLK: %s parent %s has no rate!\n", | |
207 | clk->name, clk->parent->name)) | |
208 | return -EINVAL; | |
209 | ||
f02bf3b3 SN |
210 | INIT_LIST_HEAD(&clk->children); |
211 | ||
3e062b07 | 212 | mutex_lock(&clocks_mutex); |
c5b736d0 | 213 | list_add_tail(&clk->node, &clocks); |
f02bf3b3 SN |
214 | if (clk->parent) |
215 | list_add_tail(&clk->childnode, &clk->parent->children); | |
3e062b07 VB |
216 | mutex_unlock(&clocks_mutex); |
217 | ||
c5b736d0 KH |
218 | /* If rate is already set, use it */ |
219 | if (clk->rate) | |
220 | return 0; | |
221 | ||
de381a91 SN |
222 | /* Else, see if there is a way to calculate it */ |
223 | if (clk->recalc) | |
224 | clk->rate = clk->recalc(clk); | |
225 | ||
c5b736d0 | 226 | /* Otherwise, default to parent rate */ |
de381a91 | 227 | else if (clk->parent) |
c5b736d0 KH |
228 | clk->rate = clk->parent->rate; |
229 | ||
3e062b07 VB |
230 | return 0; |
231 | } | |
232 | EXPORT_SYMBOL(clk_register); | |
233 | ||
234 | void clk_unregister(struct clk *clk) | |
235 | { | |
236 | if (clk == NULL || IS_ERR(clk)) | |
237 | return; | |
238 | ||
239 | mutex_lock(&clocks_mutex); | |
240 | list_del(&clk->node); | |
f02bf3b3 | 241 | list_del(&clk->childnode); |
3e062b07 VB |
242 | mutex_unlock(&clocks_mutex); |
243 | } | |
244 | EXPORT_SYMBOL(clk_unregister); | |
245 | ||
c5b736d0 KH |
246 | #ifdef CONFIG_DAVINCI_RESET_CLOCKS |
247 | /* | |
248 | * Disable any unused clocks left on by the bootloader | |
249 | */ | |
3aa3e840 | 250 | int __init davinci_clk_disable_unused(void) |
c5b736d0 KH |
251 | { |
252 | struct clk *ck; | |
253 | ||
254 | spin_lock_irq(&clockfw_lock); | |
255 | list_for_each_entry(ck, &clocks, node) { | |
256 | if (ck->usecount > 0) | |
257 | continue; | |
258 | if (!(ck->flags & CLK_PSC)) | |
259 | continue; | |
260 | ||
261 | /* ignore if in Disabled or SwRstDisable states */ | |
789a785e | 262 | if (!davinci_psc_is_clk_active(ck->gpsc, ck->lpsc)) |
c5b736d0 KH |
263 | continue; |
264 | ||
c89f1681 | 265 | pr_debug("Clocks: disable unused %s\n", ck->name); |
52958be3 | 266 | |
12221d43 | 267 | davinci_psc_config(ck->domain, ck->gpsc, ck->lpsc, |
a51ca38b | 268 | false, ck->flags); |
3e062b07 | 269 | } |
c5b736d0 KH |
270 | spin_unlock_irq(&clockfw_lock); |
271 | ||
272 | return 0; | |
273 | } | |
c5b736d0 | 274 | #endif |
3e062b07 | 275 | |
de381a91 | 276 | static unsigned long clk_sysclk_recalc(struct clk *clk) |
3e062b07 | 277 | { |
c5b736d0 KH |
278 | u32 v, plldiv; |
279 | struct pll_data *pll; | |
de381a91 | 280 | unsigned long rate = clk->rate; |
c5b736d0 KH |
281 | |
282 | /* If this is the PLL base clock, no more calculations needed */ | |
283 | if (clk->pll_data) | |
de381a91 | 284 | return rate; |
c5b736d0 KH |
285 | |
286 | if (WARN_ON(!clk->parent)) | |
de381a91 | 287 | return rate; |
c5b736d0 | 288 | |
de381a91 | 289 | rate = clk->parent->rate; |
c5b736d0 KH |
290 | |
291 | /* Otherwise, the parent must be a PLL */ | |
292 | if (WARN_ON(!clk->parent->pll_data)) | |
de381a91 | 293 | return rate; |
c5b736d0 KH |
294 | |
295 | pll = clk->parent->pll_data; | |
296 | ||
297 | /* If pre-PLL, source clock is before the multiplier and divider(s) */ | |
298 | if (clk->flags & PRE_PLL) | |
de381a91 | 299 | rate = pll->input_rate; |
c5b736d0 KH |
300 | |
301 | if (!clk->div_reg) | |
de381a91 | 302 | return rate; |
c5b736d0 KH |
303 | |
304 | v = __raw_readl(pll->base + clk->div_reg); | |
305 | if (v & PLLDIV_EN) { | |
d6961e68 | 306 | plldiv = (v & pll->div_ratio_mask) + 1; |
c5b736d0 | 307 | if (plldiv) |
de381a91 | 308 | rate /= plldiv; |
c5b736d0 | 309 | } |
de381a91 SN |
310 | |
311 | return rate; | |
312 | } | |
313 | ||
b39639b8 SN |
314 | int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate) |
315 | { | |
316 | unsigned v; | |
317 | struct pll_data *pll; | |
318 | unsigned long input; | |
319 | unsigned ratio = 0; | |
320 | ||
321 | /* If this is the PLL base clock, wrong function to call */ | |
322 | if (clk->pll_data) | |
323 | return -EINVAL; | |
324 | ||
325 | /* There must be a parent... */ | |
326 | if (WARN_ON(!clk->parent)) | |
327 | return -EINVAL; | |
328 | ||
329 | /* ... the parent must be a PLL... */ | |
330 | if (WARN_ON(!clk->parent->pll_data)) | |
331 | return -EINVAL; | |
332 | ||
333 | /* ... and this clock must have a divider. */ | |
334 | if (WARN_ON(!clk->div_reg)) | |
335 | return -EINVAL; | |
336 | ||
337 | pll = clk->parent->pll_data; | |
338 | ||
339 | input = clk->parent->rate; | |
340 | ||
341 | /* If pre-PLL, source clock is before the multiplier and divider(s) */ | |
342 | if (clk->flags & PRE_PLL) | |
343 | input = pll->input_rate; | |
344 | ||
345 | if (input > rate) { | |
346 | /* | |
347 | * Can afford to provide an output little higher than requested | |
348 | * only if maximum rate supported by hardware on this sysclk | |
349 | * is known. | |
350 | */ | |
351 | if (clk->maxrate) { | |
352 | ratio = DIV_ROUND_CLOSEST(input, rate); | |
353 | if (input / ratio > clk->maxrate) | |
354 | ratio = 0; | |
355 | } | |
356 | ||
357 | if (ratio == 0) | |
358 | ratio = DIV_ROUND_UP(input, rate); | |
359 | ||
360 | ratio--; | |
361 | } | |
362 | ||
b1d05be6 | 363 | if (ratio > pll->div_ratio_mask) |
b39639b8 SN |
364 | return -EINVAL; |
365 | ||
366 | do { | |
367 | v = __raw_readl(pll->base + PLLSTAT); | |
368 | } while (v & PLLSTAT_GOSTAT); | |
369 | ||
370 | v = __raw_readl(pll->base + clk->div_reg); | |
b1d05be6 | 371 | v &= ~pll->div_ratio_mask; |
b39639b8 SN |
372 | v |= ratio | PLLDIV_EN; |
373 | __raw_writel(v, pll->base + clk->div_reg); | |
374 | ||
375 | v = __raw_readl(pll->base + PLLCMD); | |
376 | v |= PLLCMD_GOSET; | |
377 | __raw_writel(v, pll->base + PLLCMD); | |
378 | ||
379 | do { | |
380 | v = __raw_readl(pll->base + PLLSTAT); | |
381 | } while (v & PLLSTAT_GOSTAT); | |
382 | ||
383 | return 0; | |
384 | } | |
385 | EXPORT_SYMBOL(davinci_set_sysclk_rate); | |
386 | ||
de381a91 SN |
387 | static unsigned long clk_leafclk_recalc(struct clk *clk) |
388 | { | |
389 | if (WARN_ON(!clk->parent)) | |
390 | return clk->rate; | |
391 | ||
392 | return clk->parent->rate; | |
c5b736d0 KH |
393 | } |
394 | ||
56e580d7 SN |
395 | int davinci_simple_set_rate(struct clk *clk, unsigned long rate) |
396 | { | |
397 | clk->rate = rate; | |
398 | return 0; | |
399 | } | |
400 | ||
de381a91 | 401 | static unsigned long clk_pllclk_recalc(struct clk *clk) |
c5b736d0 KH |
402 | { |
403 | u32 ctrl, mult = 1, prediv = 1, postdiv = 1; | |
404 | u8 bypass; | |
405 | struct pll_data *pll = clk->pll_data; | |
de381a91 | 406 | unsigned long rate = clk->rate; |
c5b736d0 | 407 | |
c5b736d0 | 408 | ctrl = __raw_readl(pll->base + PLLCTL); |
de381a91 | 409 | rate = pll->input_rate = clk->parent->rate; |
c5b736d0 KH |
410 | |
411 | if (ctrl & PLLCTL_PLLEN) { | |
412 | bypass = 0; | |
413 | mult = __raw_readl(pll->base + PLLM); | |
fb8fcb89 SP |
414 | if (cpu_is_davinci_dm365()) |
415 | mult = 2 * (mult & PLLM_PLLM_MASK); | |
416 | else | |
417 | mult = (mult & PLLM_PLLM_MASK) + 1; | |
c5b736d0 KH |
418 | } else |
419 | bypass = 1; | |
420 | ||
421 | if (pll->flags & PLL_HAS_PREDIV) { | |
422 | prediv = __raw_readl(pll->base + PREDIV); | |
423 | if (prediv & PLLDIV_EN) | |
d6961e68 | 424 | prediv = (prediv & pll->div_ratio_mask) + 1; |
c5b736d0 KH |
425 | else |
426 | prediv = 1; | |
427 | } | |
428 | ||
429 | /* pre-divider is fixed, but (some?) chips won't report that */ | |
430 | if (cpu_is_davinci_dm355() && pll->num == 1) | |
431 | prediv = 8; | |
432 | ||
433 | if (pll->flags & PLL_HAS_POSTDIV) { | |
434 | postdiv = __raw_readl(pll->base + POSTDIV); | |
435 | if (postdiv & PLLDIV_EN) | |
d6961e68 | 436 | postdiv = (postdiv & pll->div_ratio_mask) + 1; |
c5b736d0 KH |
437 | else |
438 | postdiv = 1; | |
439 | } | |
440 | ||
441 | if (!bypass) { | |
de381a91 SN |
442 | rate /= prediv; |
443 | rate *= mult; | |
444 | rate /= postdiv; | |
c5b736d0 KH |
445 | } |
446 | ||
447 | pr_debug("PLL%d: input = %lu MHz [ ", | |
448 | pll->num, clk->parent->rate / 1000000); | |
449 | if (bypass) | |
450 | pr_debug("bypass "); | |
451 | if (prediv > 1) | |
452 | pr_debug("/ %d ", prediv); | |
453 | if (mult > 1) | |
454 | pr_debug("* %d ", mult); | |
455 | if (postdiv > 1) | |
456 | pr_debug("/ %d ", postdiv); | |
de381a91 SN |
457 | pr_debug("] --> %lu MHz output.\n", rate / 1000000); |
458 | ||
459 | return rate; | |
c5b736d0 KH |
460 | } |
461 | ||
d6a61563 SN |
462 | /** |
463 | * davinci_set_pllrate - set the output rate of a given PLL. | |
464 | * | |
465 | * Note: Currently tested to work with OMAP-L138 only. | |
466 | * | |
467 | * @pll: pll whose rate needs to be changed. | |
468 | * @prediv: The pre divider value. Passing 0 disables the pre-divider. | |
469 | * @pllm: The multiplier value. Passing 0 leads to multiply-by-one. | |
470 | * @postdiv: The post divider value. Passing 0 disables the post-divider. | |
471 | */ | |
472 | int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, | |
473 | unsigned int mult, unsigned int postdiv) | |
474 | { | |
475 | u32 ctrl; | |
476 | unsigned int locktime; | |
3b43cd6f | 477 | unsigned long flags; |
d6a61563 SN |
478 | |
479 | if (pll->base == NULL) | |
480 | return -EINVAL; | |
481 | ||
482 | /* | |
483 | * PLL lock time required per OMAP-L138 datasheet is | |
484 | * (2000 * prediv)/sqrt(pllm) OSCIN cycles. We approximate sqrt(pllm) | |
485 | * as 4 and OSCIN cycle as 25 MHz. | |
486 | */ | |
487 | if (prediv) { | |
488 | locktime = ((2000 * prediv) / 100); | |
489 | prediv = (prediv - 1) | PLLDIV_EN; | |
490 | } else { | |
9a219a9e | 491 | locktime = PLL_LOCK_TIME; |
d6a61563 SN |
492 | } |
493 | if (postdiv) | |
494 | postdiv = (postdiv - 1) | PLLDIV_EN; | |
495 | if (mult) | |
496 | mult = mult - 1; | |
497 | ||
3b43cd6f SN |
498 | /* Protect against simultaneous calls to PLL setting seqeunce */ |
499 | spin_lock_irqsave(&clockfw_lock, flags); | |
500 | ||
d6a61563 SN |
501 | ctrl = __raw_readl(pll->base + PLLCTL); |
502 | ||
503 | /* Switch the PLL to bypass mode */ | |
504 | ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN); | |
505 | __raw_writel(ctrl, pll->base + PLLCTL); | |
506 | ||
9a219a9e | 507 | udelay(PLL_BYPASS_TIME); |
d6a61563 SN |
508 | |
509 | /* Reset and enable PLL */ | |
510 | ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS); | |
511 | __raw_writel(ctrl, pll->base + PLLCTL); | |
512 | ||
513 | if (pll->flags & PLL_HAS_PREDIV) | |
514 | __raw_writel(prediv, pll->base + PREDIV); | |
515 | ||
516 | __raw_writel(mult, pll->base + PLLM); | |
517 | ||
518 | if (pll->flags & PLL_HAS_POSTDIV) | |
519 | __raw_writel(postdiv, pll->base + POSTDIV); | |
520 | ||
9a219a9e | 521 | udelay(PLL_RESET_TIME); |
d6a61563 SN |
522 | |
523 | /* Bring PLL out of reset */ | |
524 | ctrl |= PLLCTL_PLLRST; | |
525 | __raw_writel(ctrl, pll->base + PLLCTL); | |
526 | ||
527 | udelay(locktime); | |
528 | ||
529 | /* Remove PLL from bypass mode */ | |
530 | ctrl |= PLLCTL_PLLEN; | |
531 | __raw_writel(ctrl, pll->base + PLLCTL); | |
532 | ||
3b43cd6f SN |
533 | spin_unlock_irqrestore(&clockfw_lock, flags); |
534 | ||
d6a61563 SN |
535 | return 0; |
536 | } | |
537 | EXPORT_SYMBOL(davinci_set_pllrate); | |
538 | ||
56e580d7 SN |
539 | /** |
540 | * davinci_set_refclk_rate() - Set the reference clock rate | |
541 | * @rate: The new rate. | |
542 | * | |
543 | * Sets the reference clock rate to a given value. This will most likely | |
544 | * result in the entire clock tree getting updated. | |
545 | * | |
546 | * This is used to support boards which use a reference clock different | |
547 | * than that used by default in <soc>.c file. The reference clock rate | |
548 | * should be updated early in the boot process; ideally soon after the | |
549 | * clock tree has been initialized once with the default reference clock | |
550 | * rate (davinci_common_init()). | |
551 | * | |
552 | * Returns 0 on success, error otherwise. | |
553 | */ | |
554 | int davinci_set_refclk_rate(unsigned long rate) | |
555 | { | |
556 | struct clk *refclk; | |
557 | ||
558 | refclk = clk_get(NULL, "ref"); | |
559 | if (IS_ERR(refclk)) { | |
560 | pr_err("%s: failed to get reference clock.\n", __func__); | |
561 | return PTR_ERR(refclk); | |
562 | } | |
563 | ||
564 | clk_set_rate(refclk, rate); | |
565 | ||
566 | clk_put(refclk); | |
567 | ||
568 | return 0; | |
569 | } | |
570 | ||
08aca087 | 571 | int __init davinci_clk_init(struct clk_lookup *clocks) |
af47e6bb | 572 | { |
08aca087 | 573 | struct clk_lookup *c; |
c5b736d0 | 574 | struct clk *clk; |
08aca087 | 575 | size_t num_clocks = 0; |
c5b736d0 | 576 | |
08aca087 KH |
577 | for (c = clocks; c->clk; c++) { |
578 | clk = c->clk; | |
c5b736d0 | 579 | |
de381a91 SN |
580 | if (!clk->recalc) { |
581 | ||
582 | /* Check if clock is a PLL */ | |
583 | if (clk->pll_data) | |
584 | clk->recalc = clk_pllclk_recalc; | |
585 | ||
586 | /* Else, if it is a PLL-derived clock */ | |
587 | else if (clk->flags & CLK_PLL) | |
588 | clk->recalc = clk_sysclk_recalc; | |
589 | ||
590 | /* Otherwise, it is a leaf clock (PSC clock) */ | |
591 | else if (clk->parent) | |
592 | clk->recalc = clk_leafclk_recalc; | |
593 | } | |
c5b736d0 | 594 | |
e4c822c7 CC |
595 | if (clk->pll_data) { |
596 | struct pll_data *pll = clk->pll_data; | |
597 | ||
598 | if (!pll->div_ratio_mask) | |
599 | pll->div_ratio_mask = PLLDIV_RATIO_MASK; | |
600 | ||
601 | if (pll->phys_base && !pll->base) { | |
602 | pll->base = ioremap(pll->phys_base, SZ_4K); | |
603 | WARN_ON(!pll->base); | |
604 | } | |
605 | } | |
d6961e68 | 606 | |
de381a91 SN |
607 | if (clk->recalc) |
608 | clk->rate = clk->recalc(clk); | |
c5b736d0 KH |
609 | |
610 | if (clk->lpsc) | |
611 | clk->flags |= CLK_PSC; | |
612 | ||
af47e6bb RT |
613 | if (clk->flags & PSC_LRST) |
614 | clk->reset = davinci_clk_reset; | |
615 | ||
c5b736d0 | 616 | clk_register(clk); |
08aca087 | 617 | num_clocks++; |
c5b736d0 KH |
618 | |
619 | /* Turn on clocks that Linux doesn't otherwise manage */ | |
620 | if (clk->flags & ALWAYS_ENABLED) | |
621 | clk_enable(clk); | |
3e062b07 VB |
622 | } |
623 | ||
08aca087 KH |
624 | clkdev_add_table(clocks, num_clocks); |
625 | ||
3e062b07 VB |
626 | return 0; |
627 | } | |
628 | ||
2f72e8dc | 629 | #ifdef CONFIG_DEBUG_FS |
3e062b07 | 630 | |
2f72e8dc SN |
631 | #include <linux/debugfs.h> |
632 | #include <linux/seq_file.h> | |
3e062b07 | 633 | |
c5b736d0 KH |
634 | #define CLKNAME_MAX 10 /* longest clock name */ |
635 | #define NEST_DELTA 2 | |
636 | #define NEST_MAX 4 | |
637 | ||
638 | static void | |
639 | dump_clock(struct seq_file *s, unsigned nest, struct clk *parent) | |
3e062b07 | 640 | { |
c5b736d0 KH |
641 | char *state; |
642 | char buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX]; | |
643 | struct clk *clk; | |
644 | unsigned i; | |
645 | ||
646 | if (parent->flags & CLK_PLL) | |
647 | state = "pll"; | |
648 | else if (parent->flags & CLK_PSC) | |
649 | state = "psc"; | |
650 | else | |
651 | state = ""; | |
652 | ||
653 | /* <nest spaces> name <pad to end> */ | |
654 | memset(buf, ' ', sizeof(buf) - 1); | |
655 | buf[sizeof(buf) - 1] = 0; | |
656 | i = strlen(parent->name); | |
657 | memcpy(buf + nest, parent->name, | |
658 | min(i, (unsigned)(sizeof(buf) - 1 - nest))); | |
659 | ||
660 | seq_printf(s, "%s users=%2d %-3s %9ld Hz\n", | |
661 | buf, parent->usecount, state, clk_get_rate(parent)); | |
662 | /* REVISIT show device associations too */ | |
663 | ||
664 | /* cost is now small, but not linear... */ | |
f02bf3b3 SN |
665 | list_for_each_entry(clk, &parent->children, childnode) { |
666 | dump_clock(s, nest + NEST_DELTA, clk); | |
c5b736d0 KH |
667 | } |
668 | } | |
3e062b07 | 669 | |
c5b736d0 KH |
670 | static int davinci_ck_show(struct seq_file *m, void *v) |
671 | { | |
f979aa6e SN |
672 | struct clk *clk; |
673 | ||
674 | /* | |
675 | * Show clock tree; We trust nonzero usecounts equate to PSC enables... | |
c5b736d0 KH |
676 | */ |
677 | mutex_lock(&clocks_mutex); | |
f979aa6e SN |
678 | list_for_each_entry(clk, &clocks, node) |
679 | if (!clk->parent) | |
680 | dump_clock(m, 0, clk); | |
c5b736d0 | 681 | mutex_unlock(&clocks_mutex); |
3e062b07 VB |
682 | |
683 | return 0; | |
684 | } | |
685 | ||
3e062b07 VB |
686 | static int davinci_ck_open(struct inode *inode, struct file *file) |
687 | { | |
2f72e8dc | 688 | return single_open(file, davinci_ck_show, NULL); |
3e062b07 VB |
689 | } |
690 | ||
2f72e8dc | 691 | static const struct file_operations davinci_ck_operations = { |
3e062b07 VB |
692 | .open = davinci_ck_open, |
693 | .read = seq_read, | |
694 | .llseek = seq_lseek, | |
2f72e8dc | 695 | .release = single_release, |
3e062b07 VB |
696 | }; |
697 | ||
2f72e8dc | 698 | static int __init davinci_clk_debugfs_init(void) |
3e062b07 | 699 | { |
2f72e8dc SN |
700 | debugfs_create_file("davinci_clocks", S_IFREG | S_IRUGO, NULL, NULL, |
701 | &davinci_ck_operations); | |
3e062b07 VB |
702 | return 0; |
703 | ||
704 | } | |
2f72e8dc SN |
705 | device_initcall(davinci_clk_debugfs_init); |
706 | #endif /* CONFIG_DEBUG_FS */ |