Commit | Line | Data |
---|---|---|
3e062b07 | 1 | /* |
c5b736d0 | 2 | * Clock and PLL control for DaVinci devices |
3e062b07 | 3 | * |
c5b736d0 KH |
4 | * Copyright (C) 2006-2007 Texas Instruments. |
5 | * Copyright (C) 2008-2009 Deep Root Systems, LLC | |
3e062b07 VB |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/errno.h> | |
c5b736d0 | 17 | #include <linux/clk.h> |
3e062b07 VB |
18 | #include <linux/err.h> |
19 | #include <linux/mutex.h> | |
20 | #include <linux/platform_device.h> | |
fced80c7 | 21 | #include <linux/io.h> |
d6a61563 | 22 | #include <linux/delay.h> |
3e062b07 | 23 | |
a09e64fb | 24 | #include <mach/hardware.h> |
3e062b07 | 25 | |
a09e64fb | 26 | #include <mach/psc.h> |
c5b736d0 | 27 | #include <mach/cputype.h> |
3e062b07 VB |
28 | #include "clock.h" |
29 | ||
3e062b07 VB |
30 | static LIST_HEAD(clocks); |
31 | static DEFINE_MUTEX(clocks_mutex); | |
32 | static DEFINE_SPINLOCK(clockfw_lock); | |
33 | ||
c5b736d0 | 34 | static unsigned psc_domain(struct clk *clk) |
3e062b07 | 35 | { |
c5b736d0 KH |
36 | return (clk->flags & PSC_DSP) |
37 | ? DAVINCI_GPSC_DSPDOMAIN | |
38 | : DAVINCI_GPSC_ARMDOMAIN; | |
3e062b07 | 39 | } |
3e062b07 | 40 | |
c5b736d0 | 41 | static void __clk_enable(struct clk *clk) |
3e062b07 | 42 | { |
c5b736d0 KH |
43 | if (clk->parent) |
44 | __clk_enable(clk->parent); | |
45 | if (clk->usecount++ == 0 && (clk->flags & CLK_PSC)) | |
d81d188c MG |
46 | davinci_psc_config(psc_domain(clk), clk->psc_ctlr, |
47 | clk->lpsc, 1); | |
3e062b07 VB |
48 | } |
49 | ||
50 | static void __clk_disable(struct clk *clk) | |
51 | { | |
c5b736d0 | 52 | if (WARN_ON(clk->usecount == 0)) |
3e062b07 | 53 | return; |
c5b736d0 | 54 | if (--clk->usecount == 0 && !(clk->flags & CLK_PLL)) |
d81d188c MG |
55 | davinci_psc_config(psc_domain(clk), clk->psc_ctlr, |
56 | clk->lpsc, 0); | |
c5b736d0 KH |
57 | if (clk->parent) |
58 | __clk_disable(clk->parent); | |
3e062b07 VB |
59 | } |
60 | ||
61 | int clk_enable(struct clk *clk) | |
62 | { | |
63 | unsigned long flags; | |
3e062b07 VB |
64 | |
65 | if (clk == NULL || IS_ERR(clk)) | |
66 | return -EINVAL; | |
67 | ||
c5b736d0 KH |
68 | spin_lock_irqsave(&clockfw_lock, flags); |
69 | __clk_enable(clk); | |
70 | spin_unlock_irqrestore(&clockfw_lock, flags); | |
3e062b07 | 71 | |
c5b736d0 | 72 | return 0; |
3e062b07 VB |
73 | } |
74 | EXPORT_SYMBOL(clk_enable); | |
75 | ||
76 | void clk_disable(struct clk *clk) | |
77 | { | |
78 | unsigned long flags; | |
79 | ||
80 | if (clk == NULL || IS_ERR(clk)) | |
81 | return; | |
82 | ||
c5b736d0 KH |
83 | spin_lock_irqsave(&clockfw_lock, flags); |
84 | __clk_disable(clk); | |
85 | spin_unlock_irqrestore(&clockfw_lock, flags); | |
3e062b07 VB |
86 | } |
87 | EXPORT_SYMBOL(clk_disable); | |
88 | ||
89 | unsigned long clk_get_rate(struct clk *clk) | |
90 | { | |
91 | if (clk == NULL || IS_ERR(clk)) | |
92 | return -EINVAL; | |
93 | ||
c5b736d0 | 94 | return clk->rate; |
3e062b07 VB |
95 | } |
96 | EXPORT_SYMBOL(clk_get_rate); | |
97 | ||
98 | long clk_round_rate(struct clk *clk, unsigned long rate) | |
99 | { | |
100 | if (clk == NULL || IS_ERR(clk)) | |
101 | return -EINVAL; | |
102 | ||
d6a61563 SN |
103 | if (clk->round_rate) |
104 | return clk->round_rate(clk, rate); | |
105 | ||
c5b736d0 | 106 | return clk->rate; |
3e062b07 VB |
107 | } |
108 | EXPORT_SYMBOL(clk_round_rate); | |
109 | ||
d6a61563 SN |
110 | /* Propagate rate to children */ |
111 | static void propagate_rate(struct clk *root) | |
112 | { | |
113 | struct clk *clk; | |
114 | ||
115 | list_for_each_entry(clk, &root->children, childnode) { | |
116 | if (clk->recalc) | |
117 | clk->rate = clk->recalc(clk); | |
118 | propagate_rate(clk); | |
119 | } | |
120 | } | |
121 | ||
3e062b07 VB |
122 | int clk_set_rate(struct clk *clk, unsigned long rate) |
123 | { | |
d6a61563 SN |
124 | unsigned long flags; |
125 | int ret = -EINVAL; | |
126 | ||
3e062b07 | 127 | if (clk == NULL || IS_ERR(clk)) |
d6a61563 SN |
128 | return ret; |
129 | ||
130 | spin_lock_irqsave(&clockfw_lock, flags); | |
131 | if (clk->set_rate) | |
132 | ret = clk->set_rate(clk, rate); | |
133 | if (ret == 0) { | |
134 | if (clk->recalc) | |
135 | clk->rate = clk->recalc(clk); | |
136 | propagate_rate(clk); | |
137 | } | |
138 | spin_unlock_irqrestore(&clockfw_lock, flags); | |
3e062b07 | 139 | |
d6a61563 | 140 | return ret; |
3e062b07 VB |
141 | } |
142 | EXPORT_SYMBOL(clk_set_rate); | |
143 | ||
b82a51e8 SN |
144 | int clk_set_parent(struct clk *clk, struct clk *parent) |
145 | { | |
146 | unsigned long flags; | |
147 | ||
148 | if (clk == NULL || IS_ERR(clk)) | |
149 | return -EINVAL; | |
150 | ||
151 | /* Cannot change parent on enabled clock */ | |
152 | if (WARN_ON(clk->usecount)) | |
153 | return -EINVAL; | |
154 | ||
155 | mutex_lock(&clocks_mutex); | |
156 | clk->parent = parent; | |
157 | list_del_init(&clk->childnode); | |
158 | list_add(&clk->childnode, &clk->parent->children); | |
159 | mutex_unlock(&clocks_mutex); | |
160 | ||
161 | spin_lock_irqsave(&clockfw_lock, flags); | |
162 | if (clk->recalc) | |
163 | clk->rate = clk->recalc(clk); | |
164 | propagate_rate(clk); | |
165 | spin_unlock_irqrestore(&clockfw_lock, flags); | |
166 | ||
167 | return 0; | |
168 | } | |
169 | EXPORT_SYMBOL(clk_set_parent); | |
170 | ||
3e062b07 VB |
171 | int clk_register(struct clk *clk) |
172 | { | |
173 | if (clk == NULL || IS_ERR(clk)) | |
174 | return -EINVAL; | |
175 | ||
c5b736d0 KH |
176 | if (WARN(clk->parent && !clk->parent->rate, |
177 | "CLK: %s parent %s has no rate!\n", | |
178 | clk->name, clk->parent->name)) | |
179 | return -EINVAL; | |
180 | ||
f02bf3b3 SN |
181 | INIT_LIST_HEAD(&clk->children); |
182 | ||
3e062b07 | 183 | mutex_lock(&clocks_mutex); |
c5b736d0 | 184 | list_add_tail(&clk->node, &clocks); |
f02bf3b3 SN |
185 | if (clk->parent) |
186 | list_add_tail(&clk->childnode, &clk->parent->children); | |
3e062b07 VB |
187 | mutex_unlock(&clocks_mutex); |
188 | ||
c5b736d0 KH |
189 | /* If rate is already set, use it */ |
190 | if (clk->rate) | |
191 | return 0; | |
192 | ||
de381a91 SN |
193 | /* Else, see if there is a way to calculate it */ |
194 | if (clk->recalc) | |
195 | clk->rate = clk->recalc(clk); | |
196 | ||
c5b736d0 | 197 | /* Otherwise, default to parent rate */ |
de381a91 | 198 | else if (clk->parent) |
c5b736d0 KH |
199 | clk->rate = clk->parent->rate; |
200 | ||
3e062b07 VB |
201 | return 0; |
202 | } | |
203 | EXPORT_SYMBOL(clk_register); | |
204 | ||
205 | void clk_unregister(struct clk *clk) | |
206 | { | |
207 | if (clk == NULL || IS_ERR(clk)) | |
208 | return; | |
209 | ||
210 | mutex_lock(&clocks_mutex); | |
211 | list_del(&clk->node); | |
f02bf3b3 | 212 | list_del(&clk->childnode); |
3e062b07 VB |
213 | mutex_unlock(&clocks_mutex); |
214 | } | |
215 | EXPORT_SYMBOL(clk_unregister); | |
216 | ||
c5b736d0 KH |
217 | #ifdef CONFIG_DAVINCI_RESET_CLOCKS |
218 | /* | |
219 | * Disable any unused clocks left on by the bootloader | |
220 | */ | |
221 | static int __init clk_disable_unused(void) | |
222 | { | |
223 | struct clk *ck; | |
224 | ||
225 | spin_lock_irq(&clockfw_lock); | |
226 | list_for_each_entry(ck, &clocks, node) { | |
227 | if (ck->usecount > 0) | |
228 | continue; | |
229 | if (!(ck->flags & CLK_PSC)) | |
230 | continue; | |
231 | ||
232 | /* ignore if in Disabled or SwRstDisable states */ | |
d81d188c | 233 | if (!davinci_psc_is_clk_active(ck->psc_ctlr, ck->lpsc)) |
c5b736d0 KH |
234 | continue; |
235 | ||
236 | pr_info("Clocks: disable unused %s\n", ck->name); | |
d81d188c | 237 | davinci_psc_config(psc_domain(ck), ck->psc_ctlr, ck->lpsc, 0); |
3e062b07 | 238 | } |
c5b736d0 KH |
239 | spin_unlock_irq(&clockfw_lock); |
240 | ||
241 | return 0; | |
242 | } | |
243 | late_initcall(clk_disable_unused); | |
244 | #endif | |
3e062b07 | 245 | |
de381a91 | 246 | static unsigned long clk_sysclk_recalc(struct clk *clk) |
3e062b07 | 247 | { |
c5b736d0 KH |
248 | u32 v, plldiv; |
249 | struct pll_data *pll; | |
de381a91 | 250 | unsigned long rate = clk->rate; |
c5b736d0 KH |
251 | |
252 | /* If this is the PLL base clock, no more calculations needed */ | |
253 | if (clk->pll_data) | |
de381a91 | 254 | return rate; |
c5b736d0 KH |
255 | |
256 | if (WARN_ON(!clk->parent)) | |
de381a91 | 257 | return rate; |
c5b736d0 | 258 | |
de381a91 | 259 | rate = clk->parent->rate; |
c5b736d0 KH |
260 | |
261 | /* Otherwise, the parent must be a PLL */ | |
262 | if (WARN_ON(!clk->parent->pll_data)) | |
de381a91 | 263 | return rate; |
c5b736d0 KH |
264 | |
265 | pll = clk->parent->pll_data; | |
266 | ||
267 | /* If pre-PLL, source clock is before the multiplier and divider(s) */ | |
268 | if (clk->flags & PRE_PLL) | |
de381a91 | 269 | rate = pll->input_rate; |
c5b736d0 KH |
270 | |
271 | if (!clk->div_reg) | |
de381a91 | 272 | return rate; |
c5b736d0 KH |
273 | |
274 | v = __raw_readl(pll->base + clk->div_reg); | |
275 | if (v & PLLDIV_EN) { | |
276 | plldiv = (v & PLLDIV_RATIO_MASK) + 1; | |
277 | if (plldiv) | |
de381a91 | 278 | rate /= plldiv; |
c5b736d0 | 279 | } |
de381a91 SN |
280 | |
281 | return rate; | |
282 | } | |
283 | ||
284 | static unsigned long clk_leafclk_recalc(struct clk *clk) | |
285 | { | |
286 | if (WARN_ON(!clk->parent)) | |
287 | return clk->rate; | |
288 | ||
289 | return clk->parent->rate; | |
c5b736d0 KH |
290 | } |
291 | ||
de381a91 | 292 | static unsigned long clk_pllclk_recalc(struct clk *clk) |
c5b736d0 KH |
293 | { |
294 | u32 ctrl, mult = 1, prediv = 1, postdiv = 1; | |
295 | u8 bypass; | |
296 | struct pll_data *pll = clk->pll_data; | |
de381a91 | 297 | unsigned long rate = clk->rate; |
c5b736d0 KH |
298 | |
299 | pll->base = IO_ADDRESS(pll->phys_base); | |
300 | ctrl = __raw_readl(pll->base + PLLCTL); | |
de381a91 | 301 | rate = pll->input_rate = clk->parent->rate; |
c5b736d0 KH |
302 | |
303 | if (ctrl & PLLCTL_PLLEN) { | |
304 | bypass = 0; | |
305 | mult = __raw_readl(pll->base + PLLM); | |
fb8fcb89 SP |
306 | if (cpu_is_davinci_dm365()) |
307 | mult = 2 * (mult & PLLM_PLLM_MASK); | |
308 | else | |
309 | mult = (mult & PLLM_PLLM_MASK) + 1; | |
c5b736d0 KH |
310 | } else |
311 | bypass = 1; | |
312 | ||
313 | if (pll->flags & PLL_HAS_PREDIV) { | |
314 | prediv = __raw_readl(pll->base + PREDIV); | |
315 | if (prediv & PLLDIV_EN) | |
316 | prediv = (prediv & PLLDIV_RATIO_MASK) + 1; | |
317 | else | |
318 | prediv = 1; | |
319 | } | |
320 | ||
321 | /* pre-divider is fixed, but (some?) chips won't report that */ | |
322 | if (cpu_is_davinci_dm355() && pll->num == 1) | |
323 | prediv = 8; | |
324 | ||
325 | if (pll->flags & PLL_HAS_POSTDIV) { | |
326 | postdiv = __raw_readl(pll->base + POSTDIV); | |
327 | if (postdiv & PLLDIV_EN) | |
328 | postdiv = (postdiv & PLLDIV_RATIO_MASK) + 1; | |
329 | else | |
330 | postdiv = 1; | |
331 | } | |
332 | ||
333 | if (!bypass) { | |
de381a91 SN |
334 | rate /= prediv; |
335 | rate *= mult; | |
336 | rate /= postdiv; | |
c5b736d0 KH |
337 | } |
338 | ||
339 | pr_debug("PLL%d: input = %lu MHz [ ", | |
340 | pll->num, clk->parent->rate / 1000000); | |
341 | if (bypass) | |
342 | pr_debug("bypass "); | |
343 | if (prediv > 1) | |
344 | pr_debug("/ %d ", prediv); | |
345 | if (mult > 1) | |
346 | pr_debug("* %d ", mult); | |
347 | if (postdiv > 1) | |
348 | pr_debug("/ %d ", postdiv); | |
de381a91 SN |
349 | pr_debug("] --> %lu MHz output.\n", rate / 1000000); |
350 | ||
351 | return rate; | |
c5b736d0 KH |
352 | } |
353 | ||
d6a61563 SN |
354 | /** |
355 | * davinci_set_pllrate - set the output rate of a given PLL. | |
356 | * | |
357 | * Note: Currently tested to work with OMAP-L138 only. | |
358 | * | |
359 | * @pll: pll whose rate needs to be changed. | |
360 | * @prediv: The pre divider value. Passing 0 disables the pre-divider. | |
361 | * @pllm: The multiplier value. Passing 0 leads to multiply-by-one. | |
362 | * @postdiv: The post divider value. Passing 0 disables the post-divider. | |
363 | */ | |
364 | int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, | |
365 | unsigned int mult, unsigned int postdiv) | |
366 | { | |
367 | u32 ctrl; | |
368 | unsigned int locktime; | |
369 | ||
370 | if (pll->base == NULL) | |
371 | return -EINVAL; | |
372 | ||
373 | /* | |
374 | * PLL lock time required per OMAP-L138 datasheet is | |
375 | * (2000 * prediv)/sqrt(pllm) OSCIN cycles. We approximate sqrt(pllm) | |
376 | * as 4 and OSCIN cycle as 25 MHz. | |
377 | */ | |
378 | if (prediv) { | |
379 | locktime = ((2000 * prediv) / 100); | |
380 | prediv = (prediv - 1) | PLLDIV_EN; | |
381 | } else { | |
382 | locktime = 20; | |
383 | } | |
384 | if (postdiv) | |
385 | postdiv = (postdiv - 1) | PLLDIV_EN; | |
386 | if (mult) | |
387 | mult = mult - 1; | |
388 | ||
389 | ctrl = __raw_readl(pll->base + PLLCTL); | |
390 | ||
391 | /* Switch the PLL to bypass mode */ | |
392 | ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN); | |
393 | __raw_writel(ctrl, pll->base + PLLCTL); | |
394 | ||
395 | /* | |
396 | * Wait for 4 OSCIN/CLKIN cycles to ensure that the PLLC has switched | |
397 | * to bypass mode. Delay of 1us ensures we are good for all > 4MHz | |
398 | * OSCIN/CLKIN inputs. Typically the input is ~25MHz. | |
399 | */ | |
400 | udelay(1); | |
401 | ||
402 | /* Reset and enable PLL */ | |
403 | ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS); | |
404 | __raw_writel(ctrl, pll->base + PLLCTL); | |
405 | ||
406 | if (pll->flags & PLL_HAS_PREDIV) | |
407 | __raw_writel(prediv, pll->base + PREDIV); | |
408 | ||
409 | __raw_writel(mult, pll->base + PLLM); | |
410 | ||
411 | if (pll->flags & PLL_HAS_POSTDIV) | |
412 | __raw_writel(postdiv, pll->base + POSTDIV); | |
413 | ||
414 | /* | |
415 | * Wait for PLL to reset properly, OMAP-L138 datasheet says | |
416 | * 'min' time = 125ns | |
417 | */ | |
418 | udelay(1); | |
419 | ||
420 | /* Bring PLL out of reset */ | |
421 | ctrl |= PLLCTL_PLLRST; | |
422 | __raw_writel(ctrl, pll->base + PLLCTL); | |
423 | ||
424 | udelay(locktime); | |
425 | ||
426 | /* Remove PLL from bypass mode */ | |
427 | ctrl |= PLLCTL_PLLEN; | |
428 | __raw_writel(ctrl, pll->base + PLLCTL); | |
429 | ||
430 | return 0; | |
431 | } | |
432 | EXPORT_SYMBOL(davinci_set_pllrate); | |
433 | ||
c5b736d0 KH |
434 | int __init davinci_clk_init(struct davinci_clk *clocks) |
435 | { | |
436 | struct davinci_clk *c; | |
437 | struct clk *clk; | |
438 | ||
439 | for (c = clocks; c->lk.clk; c++) { | |
440 | clk = c->lk.clk; | |
441 | ||
de381a91 SN |
442 | if (!clk->recalc) { |
443 | ||
444 | /* Check if clock is a PLL */ | |
445 | if (clk->pll_data) | |
446 | clk->recalc = clk_pllclk_recalc; | |
447 | ||
448 | /* Else, if it is a PLL-derived clock */ | |
449 | else if (clk->flags & CLK_PLL) | |
450 | clk->recalc = clk_sysclk_recalc; | |
451 | ||
452 | /* Otherwise, it is a leaf clock (PSC clock) */ | |
453 | else if (clk->parent) | |
454 | clk->recalc = clk_leafclk_recalc; | |
455 | } | |
c5b736d0 | 456 | |
de381a91 SN |
457 | if (clk->recalc) |
458 | clk->rate = clk->recalc(clk); | |
c5b736d0 KH |
459 | |
460 | if (clk->lpsc) | |
461 | clk->flags |= CLK_PSC; | |
462 | ||
463 | clkdev_add(&c->lk); | |
464 | clk_register(clk); | |
465 | ||
466 | /* Turn on clocks that Linux doesn't otherwise manage */ | |
467 | if (clk->flags & ALWAYS_ENABLED) | |
468 | clk_enable(clk); | |
3e062b07 VB |
469 | } |
470 | ||
471 | return 0; | |
472 | } | |
473 | ||
474 | #ifdef CONFIG_PROC_FS | |
475 | #include <linux/proc_fs.h> | |
476 | #include <linux/seq_file.h> | |
477 | ||
478 | static void *davinci_ck_start(struct seq_file *m, loff_t *pos) | |
479 | { | |
480 | return *pos < 1 ? (void *)1 : NULL; | |
481 | } | |
482 | ||
483 | static void *davinci_ck_next(struct seq_file *m, void *v, loff_t *pos) | |
484 | { | |
485 | ++*pos; | |
486 | return NULL; | |
487 | } | |
488 | ||
489 | static void davinci_ck_stop(struct seq_file *m, void *v) | |
490 | { | |
491 | } | |
492 | ||
c5b736d0 KH |
493 | #define CLKNAME_MAX 10 /* longest clock name */ |
494 | #define NEST_DELTA 2 | |
495 | #define NEST_MAX 4 | |
496 | ||
497 | static void | |
498 | dump_clock(struct seq_file *s, unsigned nest, struct clk *parent) | |
3e062b07 | 499 | { |
c5b736d0 KH |
500 | char *state; |
501 | char buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX]; | |
502 | struct clk *clk; | |
503 | unsigned i; | |
504 | ||
505 | if (parent->flags & CLK_PLL) | |
506 | state = "pll"; | |
507 | else if (parent->flags & CLK_PSC) | |
508 | state = "psc"; | |
509 | else | |
510 | state = ""; | |
511 | ||
512 | /* <nest spaces> name <pad to end> */ | |
513 | memset(buf, ' ', sizeof(buf) - 1); | |
514 | buf[sizeof(buf) - 1] = 0; | |
515 | i = strlen(parent->name); | |
516 | memcpy(buf + nest, parent->name, | |
517 | min(i, (unsigned)(sizeof(buf) - 1 - nest))); | |
518 | ||
519 | seq_printf(s, "%s users=%2d %-3s %9ld Hz\n", | |
520 | buf, parent->usecount, state, clk_get_rate(parent)); | |
521 | /* REVISIT show device associations too */ | |
522 | ||
523 | /* cost is now small, but not linear... */ | |
f02bf3b3 SN |
524 | list_for_each_entry(clk, &parent->children, childnode) { |
525 | dump_clock(s, nest + NEST_DELTA, clk); | |
c5b736d0 KH |
526 | } |
527 | } | |
3e062b07 | 528 | |
c5b736d0 KH |
529 | static int davinci_ck_show(struct seq_file *m, void *v) |
530 | { | |
531 | /* Show clock tree; we know the main oscillator is first. | |
532 | * We trust nonzero usecounts equate to PSC enables... | |
533 | */ | |
534 | mutex_lock(&clocks_mutex); | |
535 | if (!list_empty(&clocks)) | |
536 | dump_clock(m, 0, list_first_entry(&clocks, struct clk, node)); | |
537 | mutex_unlock(&clocks_mutex); | |
3e062b07 VB |
538 | |
539 | return 0; | |
540 | } | |
541 | ||
2ffd6e18 | 542 | static const struct seq_operations davinci_ck_op = { |
3e062b07 VB |
543 | .start = davinci_ck_start, |
544 | .next = davinci_ck_next, | |
545 | .stop = davinci_ck_stop, | |
546 | .show = davinci_ck_show | |
547 | }; | |
548 | ||
549 | static int davinci_ck_open(struct inode *inode, struct file *file) | |
550 | { | |
551 | return seq_open(file, &davinci_ck_op); | |
552 | } | |
553 | ||
2ffd6e18 | 554 | static const struct file_operations proc_davinci_ck_operations = { |
3e062b07 VB |
555 | .open = davinci_ck_open, |
556 | .read = seq_read, | |
557 | .llseek = seq_lseek, | |
558 | .release = seq_release, | |
559 | }; | |
560 | ||
561 | static int __init davinci_ck_proc_init(void) | |
562 | { | |
40ad35d3 | 563 | proc_create("davinci_clocks", 0, NULL, &proc_davinci_ck_operations); |
3e062b07 VB |
564 | return 0; |
565 | ||
566 | } | |
567 | __initcall(davinci_ck_proc_init); | |
c5b736d0 | 568 | #endif /* CONFIG_DEBUG_PROC_FS */ |