Commit | Line | Data |
---|---|---|
3e062b07 | 1 | /* |
c5b736d0 | 2 | * Clock and PLL control for DaVinci devices |
3e062b07 | 3 | * |
c5b736d0 KH |
4 | * Copyright (C) 2006-2007 Texas Instruments. |
5 | * Copyright (C) 2008-2009 Deep Root Systems, LLC | |
3e062b07 VB |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/errno.h> | |
c5b736d0 | 17 | #include <linux/clk.h> |
3e062b07 VB |
18 | #include <linux/err.h> |
19 | #include <linux/mutex.h> | |
20 | #include <linux/platform_device.h> | |
fced80c7 | 21 | #include <linux/io.h> |
3e062b07 | 22 | |
a09e64fb | 23 | #include <mach/hardware.h> |
3e062b07 | 24 | |
a09e64fb | 25 | #include <mach/psc.h> |
c5b736d0 | 26 | #include <mach/cputype.h> |
3e062b07 VB |
27 | #include "clock.h" |
28 | ||
3e062b07 VB |
29 | static LIST_HEAD(clocks); |
30 | static DEFINE_MUTEX(clocks_mutex); | |
31 | static DEFINE_SPINLOCK(clockfw_lock); | |
32 | ||
c5b736d0 | 33 | static unsigned psc_domain(struct clk *clk) |
3e062b07 | 34 | { |
c5b736d0 KH |
35 | return (clk->flags & PSC_DSP) |
36 | ? DAVINCI_GPSC_DSPDOMAIN | |
37 | : DAVINCI_GPSC_ARMDOMAIN; | |
3e062b07 | 38 | } |
3e062b07 | 39 | |
c5b736d0 | 40 | static void __clk_enable(struct clk *clk) |
3e062b07 | 41 | { |
c5b736d0 KH |
42 | if (clk->parent) |
43 | __clk_enable(clk->parent); | |
44 | if (clk->usecount++ == 0 && (clk->flags & CLK_PSC)) | |
d81d188c MG |
45 | davinci_psc_config(psc_domain(clk), clk->psc_ctlr, |
46 | clk->lpsc, 1); | |
3e062b07 VB |
47 | } |
48 | ||
49 | static void __clk_disable(struct clk *clk) | |
50 | { | |
c5b736d0 | 51 | if (WARN_ON(clk->usecount == 0)) |
3e062b07 | 52 | return; |
c5b736d0 | 53 | if (--clk->usecount == 0 && !(clk->flags & CLK_PLL)) |
d81d188c MG |
54 | davinci_psc_config(psc_domain(clk), clk->psc_ctlr, |
55 | clk->lpsc, 0); | |
c5b736d0 KH |
56 | if (clk->parent) |
57 | __clk_disable(clk->parent); | |
3e062b07 VB |
58 | } |
59 | ||
60 | int clk_enable(struct clk *clk) | |
61 | { | |
62 | unsigned long flags; | |
3e062b07 VB |
63 | |
64 | if (clk == NULL || IS_ERR(clk)) | |
65 | return -EINVAL; | |
66 | ||
c5b736d0 KH |
67 | spin_lock_irqsave(&clockfw_lock, flags); |
68 | __clk_enable(clk); | |
69 | spin_unlock_irqrestore(&clockfw_lock, flags); | |
3e062b07 | 70 | |
c5b736d0 | 71 | return 0; |
3e062b07 VB |
72 | } |
73 | EXPORT_SYMBOL(clk_enable); | |
74 | ||
75 | void clk_disable(struct clk *clk) | |
76 | { | |
77 | unsigned long flags; | |
78 | ||
79 | if (clk == NULL || IS_ERR(clk)) | |
80 | return; | |
81 | ||
c5b736d0 KH |
82 | spin_lock_irqsave(&clockfw_lock, flags); |
83 | __clk_disable(clk); | |
84 | spin_unlock_irqrestore(&clockfw_lock, flags); | |
3e062b07 VB |
85 | } |
86 | EXPORT_SYMBOL(clk_disable); | |
87 | ||
88 | unsigned long clk_get_rate(struct clk *clk) | |
89 | { | |
90 | if (clk == NULL || IS_ERR(clk)) | |
91 | return -EINVAL; | |
92 | ||
c5b736d0 | 93 | return clk->rate; |
3e062b07 VB |
94 | } |
95 | EXPORT_SYMBOL(clk_get_rate); | |
96 | ||
97 | long clk_round_rate(struct clk *clk, unsigned long rate) | |
98 | { | |
99 | if (clk == NULL || IS_ERR(clk)) | |
100 | return -EINVAL; | |
101 | ||
c5b736d0 | 102 | return clk->rate; |
3e062b07 VB |
103 | } |
104 | EXPORT_SYMBOL(clk_round_rate); | |
105 | ||
106 | int clk_set_rate(struct clk *clk, unsigned long rate) | |
107 | { | |
108 | if (clk == NULL || IS_ERR(clk)) | |
109 | return -EINVAL; | |
110 | ||
111 | /* changing the clk rate is not supported */ | |
112 | return -EINVAL; | |
113 | } | |
114 | EXPORT_SYMBOL(clk_set_rate); | |
115 | ||
116 | int clk_register(struct clk *clk) | |
117 | { | |
118 | if (clk == NULL || IS_ERR(clk)) | |
119 | return -EINVAL; | |
120 | ||
c5b736d0 KH |
121 | if (WARN(clk->parent && !clk->parent->rate, |
122 | "CLK: %s parent %s has no rate!\n", | |
123 | clk->name, clk->parent->name)) | |
124 | return -EINVAL; | |
125 | ||
f02bf3b3 SN |
126 | INIT_LIST_HEAD(&clk->children); |
127 | ||
3e062b07 | 128 | mutex_lock(&clocks_mutex); |
c5b736d0 | 129 | list_add_tail(&clk->node, &clocks); |
f02bf3b3 SN |
130 | if (clk->parent) |
131 | list_add_tail(&clk->childnode, &clk->parent->children); | |
3e062b07 VB |
132 | mutex_unlock(&clocks_mutex); |
133 | ||
c5b736d0 KH |
134 | /* If rate is already set, use it */ |
135 | if (clk->rate) | |
136 | return 0; | |
137 | ||
de381a91 SN |
138 | /* Else, see if there is a way to calculate it */ |
139 | if (clk->recalc) | |
140 | clk->rate = clk->recalc(clk); | |
141 | ||
c5b736d0 | 142 | /* Otherwise, default to parent rate */ |
de381a91 | 143 | else if (clk->parent) |
c5b736d0 KH |
144 | clk->rate = clk->parent->rate; |
145 | ||
3e062b07 VB |
146 | return 0; |
147 | } | |
148 | EXPORT_SYMBOL(clk_register); | |
149 | ||
150 | void clk_unregister(struct clk *clk) | |
151 | { | |
152 | if (clk == NULL || IS_ERR(clk)) | |
153 | return; | |
154 | ||
155 | mutex_lock(&clocks_mutex); | |
156 | list_del(&clk->node); | |
f02bf3b3 | 157 | list_del(&clk->childnode); |
3e062b07 VB |
158 | mutex_unlock(&clocks_mutex); |
159 | } | |
160 | EXPORT_SYMBOL(clk_unregister); | |
161 | ||
c5b736d0 KH |
162 | #ifdef CONFIG_DAVINCI_RESET_CLOCKS |
163 | /* | |
164 | * Disable any unused clocks left on by the bootloader | |
165 | */ | |
166 | static int __init clk_disable_unused(void) | |
167 | { | |
168 | struct clk *ck; | |
169 | ||
170 | spin_lock_irq(&clockfw_lock); | |
171 | list_for_each_entry(ck, &clocks, node) { | |
172 | if (ck->usecount > 0) | |
173 | continue; | |
174 | if (!(ck->flags & CLK_PSC)) | |
175 | continue; | |
176 | ||
177 | /* ignore if in Disabled or SwRstDisable states */ | |
d81d188c | 178 | if (!davinci_psc_is_clk_active(ck->psc_ctlr, ck->lpsc)) |
c5b736d0 KH |
179 | continue; |
180 | ||
181 | pr_info("Clocks: disable unused %s\n", ck->name); | |
d81d188c | 182 | davinci_psc_config(psc_domain(ck), ck->psc_ctlr, ck->lpsc, 0); |
3e062b07 | 183 | } |
c5b736d0 KH |
184 | spin_unlock_irq(&clockfw_lock); |
185 | ||
186 | return 0; | |
187 | } | |
188 | late_initcall(clk_disable_unused); | |
189 | #endif | |
3e062b07 | 190 | |
de381a91 | 191 | static unsigned long clk_sysclk_recalc(struct clk *clk) |
3e062b07 | 192 | { |
c5b736d0 KH |
193 | u32 v, plldiv; |
194 | struct pll_data *pll; | |
de381a91 | 195 | unsigned long rate = clk->rate; |
c5b736d0 KH |
196 | |
197 | /* If this is the PLL base clock, no more calculations needed */ | |
198 | if (clk->pll_data) | |
de381a91 | 199 | return rate; |
c5b736d0 KH |
200 | |
201 | if (WARN_ON(!clk->parent)) | |
de381a91 | 202 | return rate; |
c5b736d0 | 203 | |
de381a91 | 204 | rate = clk->parent->rate; |
c5b736d0 KH |
205 | |
206 | /* Otherwise, the parent must be a PLL */ | |
207 | if (WARN_ON(!clk->parent->pll_data)) | |
de381a91 | 208 | return rate; |
c5b736d0 KH |
209 | |
210 | pll = clk->parent->pll_data; | |
211 | ||
212 | /* If pre-PLL, source clock is before the multiplier and divider(s) */ | |
213 | if (clk->flags & PRE_PLL) | |
de381a91 | 214 | rate = pll->input_rate; |
c5b736d0 KH |
215 | |
216 | if (!clk->div_reg) | |
de381a91 | 217 | return rate; |
c5b736d0 KH |
218 | |
219 | v = __raw_readl(pll->base + clk->div_reg); | |
220 | if (v & PLLDIV_EN) { | |
221 | plldiv = (v & PLLDIV_RATIO_MASK) + 1; | |
222 | if (plldiv) | |
de381a91 | 223 | rate /= plldiv; |
c5b736d0 | 224 | } |
de381a91 SN |
225 | |
226 | return rate; | |
227 | } | |
228 | ||
229 | static unsigned long clk_leafclk_recalc(struct clk *clk) | |
230 | { | |
231 | if (WARN_ON(!clk->parent)) | |
232 | return clk->rate; | |
233 | ||
234 | return clk->parent->rate; | |
c5b736d0 KH |
235 | } |
236 | ||
de381a91 | 237 | static unsigned long clk_pllclk_recalc(struct clk *clk) |
c5b736d0 KH |
238 | { |
239 | u32 ctrl, mult = 1, prediv = 1, postdiv = 1; | |
240 | u8 bypass; | |
241 | struct pll_data *pll = clk->pll_data; | |
de381a91 | 242 | unsigned long rate = clk->rate; |
c5b736d0 KH |
243 | |
244 | pll->base = IO_ADDRESS(pll->phys_base); | |
245 | ctrl = __raw_readl(pll->base + PLLCTL); | |
de381a91 | 246 | rate = pll->input_rate = clk->parent->rate; |
c5b736d0 KH |
247 | |
248 | if (ctrl & PLLCTL_PLLEN) { | |
249 | bypass = 0; | |
250 | mult = __raw_readl(pll->base + PLLM); | |
fb8fcb89 SP |
251 | if (cpu_is_davinci_dm365()) |
252 | mult = 2 * (mult & PLLM_PLLM_MASK); | |
253 | else | |
254 | mult = (mult & PLLM_PLLM_MASK) + 1; | |
c5b736d0 KH |
255 | } else |
256 | bypass = 1; | |
257 | ||
258 | if (pll->flags & PLL_HAS_PREDIV) { | |
259 | prediv = __raw_readl(pll->base + PREDIV); | |
260 | if (prediv & PLLDIV_EN) | |
261 | prediv = (prediv & PLLDIV_RATIO_MASK) + 1; | |
262 | else | |
263 | prediv = 1; | |
264 | } | |
265 | ||
266 | /* pre-divider is fixed, but (some?) chips won't report that */ | |
267 | if (cpu_is_davinci_dm355() && pll->num == 1) | |
268 | prediv = 8; | |
269 | ||
270 | if (pll->flags & PLL_HAS_POSTDIV) { | |
271 | postdiv = __raw_readl(pll->base + POSTDIV); | |
272 | if (postdiv & PLLDIV_EN) | |
273 | postdiv = (postdiv & PLLDIV_RATIO_MASK) + 1; | |
274 | else | |
275 | postdiv = 1; | |
276 | } | |
277 | ||
278 | if (!bypass) { | |
de381a91 SN |
279 | rate /= prediv; |
280 | rate *= mult; | |
281 | rate /= postdiv; | |
c5b736d0 KH |
282 | } |
283 | ||
284 | pr_debug("PLL%d: input = %lu MHz [ ", | |
285 | pll->num, clk->parent->rate / 1000000); | |
286 | if (bypass) | |
287 | pr_debug("bypass "); | |
288 | if (prediv > 1) | |
289 | pr_debug("/ %d ", prediv); | |
290 | if (mult > 1) | |
291 | pr_debug("* %d ", mult); | |
292 | if (postdiv > 1) | |
293 | pr_debug("/ %d ", postdiv); | |
de381a91 SN |
294 | pr_debug("] --> %lu MHz output.\n", rate / 1000000); |
295 | ||
296 | return rate; | |
c5b736d0 KH |
297 | } |
298 | ||
299 | int __init davinci_clk_init(struct davinci_clk *clocks) | |
300 | { | |
301 | struct davinci_clk *c; | |
302 | struct clk *clk; | |
303 | ||
304 | for (c = clocks; c->lk.clk; c++) { | |
305 | clk = c->lk.clk; | |
306 | ||
de381a91 SN |
307 | if (!clk->recalc) { |
308 | ||
309 | /* Check if clock is a PLL */ | |
310 | if (clk->pll_data) | |
311 | clk->recalc = clk_pllclk_recalc; | |
312 | ||
313 | /* Else, if it is a PLL-derived clock */ | |
314 | else if (clk->flags & CLK_PLL) | |
315 | clk->recalc = clk_sysclk_recalc; | |
316 | ||
317 | /* Otherwise, it is a leaf clock (PSC clock) */ | |
318 | else if (clk->parent) | |
319 | clk->recalc = clk_leafclk_recalc; | |
320 | } | |
c5b736d0 | 321 | |
de381a91 SN |
322 | if (clk->recalc) |
323 | clk->rate = clk->recalc(clk); | |
c5b736d0 KH |
324 | |
325 | if (clk->lpsc) | |
326 | clk->flags |= CLK_PSC; | |
327 | ||
328 | clkdev_add(&c->lk); | |
329 | clk_register(clk); | |
330 | ||
331 | /* Turn on clocks that Linux doesn't otherwise manage */ | |
332 | if (clk->flags & ALWAYS_ENABLED) | |
333 | clk_enable(clk); | |
3e062b07 VB |
334 | } |
335 | ||
336 | return 0; | |
337 | } | |
338 | ||
339 | #ifdef CONFIG_PROC_FS | |
340 | #include <linux/proc_fs.h> | |
341 | #include <linux/seq_file.h> | |
342 | ||
343 | static void *davinci_ck_start(struct seq_file *m, loff_t *pos) | |
344 | { | |
345 | return *pos < 1 ? (void *)1 : NULL; | |
346 | } | |
347 | ||
348 | static void *davinci_ck_next(struct seq_file *m, void *v, loff_t *pos) | |
349 | { | |
350 | ++*pos; | |
351 | return NULL; | |
352 | } | |
353 | ||
354 | static void davinci_ck_stop(struct seq_file *m, void *v) | |
355 | { | |
356 | } | |
357 | ||
c5b736d0 KH |
358 | #define CLKNAME_MAX 10 /* longest clock name */ |
359 | #define NEST_DELTA 2 | |
360 | #define NEST_MAX 4 | |
361 | ||
362 | static void | |
363 | dump_clock(struct seq_file *s, unsigned nest, struct clk *parent) | |
3e062b07 | 364 | { |
c5b736d0 KH |
365 | char *state; |
366 | char buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX]; | |
367 | struct clk *clk; | |
368 | unsigned i; | |
369 | ||
370 | if (parent->flags & CLK_PLL) | |
371 | state = "pll"; | |
372 | else if (parent->flags & CLK_PSC) | |
373 | state = "psc"; | |
374 | else | |
375 | state = ""; | |
376 | ||
377 | /* <nest spaces> name <pad to end> */ | |
378 | memset(buf, ' ', sizeof(buf) - 1); | |
379 | buf[sizeof(buf) - 1] = 0; | |
380 | i = strlen(parent->name); | |
381 | memcpy(buf + nest, parent->name, | |
382 | min(i, (unsigned)(sizeof(buf) - 1 - nest))); | |
383 | ||
384 | seq_printf(s, "%s users=%2d %-3s %9ld Hz\n", | |
385 | buf, parent->usecount, state, clk_get_rate(parent)); | |
386 | /* REVISIT show device associations too */ | |
387 | ||
388 | /* cost is now small, but not linear... */ | |
f02bf3b3 SN |
389 | list_for_each_entry(clk, &parent->children, childnode) { |
390 | dump_clock(s, nest + NEST_DELTA, clk); | |
c5b736d0 KH |
391 | } |
392 | } | |
3e062b07 | 393 | |
c5b736d0 KH |
394 | static int davinci_ck_show(struct seq_file *m, void *v) |
395 | { | |
396 | /* Show clock tree; we know the main oscillator is first. | |
397 | * We trust nonzero usecounts equate to PSC enables... | |
398 | */ | |
399 | mutex_lock(&clocks_mutex); | |
400 | if (!list_empty(&clocks)) | |
401 | dump_clock(m, 0, list_first_entry(&clocks, struct clk, node)); | |
402 | mutex_unlock(&clocks_mutex); | |
3e062b07 VB |
403 | |
404 | return 0; | |
405 | } | |
406 | ||
2ffd6e18 | 407 | static const struct seq_operations davinci_ck_op = { |
3e062b07 VB |
408 | .start = davinci_ck_start, |
409 | .next = davinci_ck_next, | |
410 | .stop = davinci_ck_stop, | |
411 | .show = davinci_ck_show | |
412 | }; | |
413 | ||
414 | static int davinci_ck_open(struct inode *inode, struct file *file) | |
415 | { | |
416 | return seq_open(file, &davinci_ck_op); | |
417 | } | |
418 | ||
2ffd6e18 | 419 | static const struct file_operations proc_davinci_ck_operations = { |
3e062b07 VB |
420 | .open = davinci_ck_open, |
421 | .read = seq_read, | |
422 | .llseek = seq_lseek, | |
423 | .release = seq_release, | |
424 | }; | |
425 | ||
426 | static int __init davinci_ck_proc_init(void) | |
427 | { | |
40ad35d3 | 428 | proc_create("davinci_clocks", 0, NULL, &proc_davinci_ck_operations); |
3e062b07 VB |
429 | return 0; |
430 | ||
431 | } | |
432 | __initcall(davinci_ck_proc_init); | |
c5b736d0 | 433 | #endif /* CONFIG_DEBUG_PROC_FS */ |