[deliverable/linux.git] / arch / arm / mach-davinci / cp_intc.c

/*
 * TI Common Platform Interrupt Controller (cp_intc) driver
 *
 * Author: Steve Chen <schen@mvista.com>
 * Copyright (C) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2. This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <linux/export.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#include <mach/common.h>
#include "cp_intc.h"

static inline unsigned int cp_intc_read(unsigned offset)
{
	return __raw_readl(davinci_intc_base + offset);
}

static inline void cp_intc_write(unsigned long value, unsigned offset)
{
	__raw_writel(value, davinci_intc_base + offset);
}

static void cp_intc_ack_irq(struct irq_data *d)
{
	cp_intc_write(d->hwirq, CP_INTC_SYS_STAT_IDX_CLR);
}

/* Disable interrupt */
static void cp_intc_mask_irq(struct irq_data *d)
{
	/* XXX don't know why we need to disable nIRQ here... */
	cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_CLR);
	cp_intc_write(d->hwirq, CP_INTC_SYS_ENABLE_IDX_CLR);
	cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET);
}

/* Enable interrupt */
static void cp_intc_unmask_irq(struct irq_data *d)
{
	cp_intc_write(d->hwirq, CP_INTC_SYS_ENABLE_IDX_SET);
}

static int cp_intc_set_irq_type(struct irq_data *d, unsigned int flow_type)
{
	unsigned reg		= BIT_WORD(d->hwirq);
	unsigned mask		= BIT_MASK(d->hwirq);
	unsigned polarity	= cp_intc_read(CP_INTC_SYS_POLARITY(reg));
	unsigned type		= cp_intc_read(CP_INTC_SYS_TYPE(reg));

	switch (flow_type) {
	case IRQ_TYPE_EDGE_RISING:
		polarity |= mask;
		type |= mask;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		polarity &= ~mask;
		type |= mask;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		polarity |= mask;
		type &= ~mask;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		polarity &= ~mask;
		type &= ~mask;
		break;
	default:
		return -EINVAL;
	}

	cp_intc_write(polarity, CP_INTC_SYS_POLARITY(reg));
	cp_intc_write(type, CP_INTC_SYS_TYPE(reg));

	return 0;
}

static struct irq_chip cp_intc_irq_chip = {
	.name		= "cp_intc",
	.irq_ack	= cp_intc_ack_irq,
	.irq_mask	= cp_intc_mask_irq,
	.irq_unmask	= cp_intc_unmask_irq,
	.irq_set_type	= cp_intc_set_irq_type,
	.flags		= IRQCHIP_SKIP_SET_WAKE,
};

static struct irq_domain *cp_intc_domain;

static int cp_intc_host_map(struct irq_domain *h, unsigned int virq,
			  irq_hw_number_t hw)
{
	pr_debug("cp_intc_host_map(%d, 0x%lx)\n", virq, hw);

	irq_set_chip(virq, &cp_intc_irq_chip);
	irq_set_probe(virq);
	irq_set_handler(virq, handle_edge_irq);
	return 0;
}

static const struct irq_domain_ops cp_intc_host_ops = {
	.map = cp_intc_host_map,
	.xlate = irq_domain_xlate_onetwocell,
};

int __init cp_intc_of_init(struct device_node *node, struct device_node *parent)
{
	u32 num_irq		= davinci_soc_info.intc_irq_num;
	u8 *irq_prio		= davinci_soc_info.intc_irq_prios;
	u32 *host_map		= davinci_soc_info.intc_host_map;
	unsigned num_reg	= BITS_TO_LONGS(num_irq);
	int i, irq_base;

	davinci_intc_type = DAVINCI_INTC_TYPE_CP_INTC;
	if (node) {
		davinci_intc_base = of_iomap(node, 0);
		if (of_property_read_u32(node, "ti,intc-size", &num_irq))
			pr_warn("unable to get intc-size, default to %d\n",
				num_irq);
	} else {
		davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K);
	}
	if (WARN_ON(!davinci_intc_base))
		return -EINVAL;

	cp_intc_write(0, CP_INTC_GLOBAL_ENABLE);

	/* Disable all host interrupts */
	cp_intc_write(0, CP_INTC_HOST_ENABLE(0));

	/* Disable system interrupts */
	for (i = 0; i < num_reg; i++)
		cp_intc_write(~0, CP_INTC_SYS_ENABLE_CLR(i));

	/* Set to normal mode, no nesting, no priority hold */
	cp_intc_write(0, CP_INTC_CTRL);
	cp_intc_write(0, CP_INTC_HOST_CTRL);

	/* Clear system interrupt status */
	for (i = 0; i < num_reg; i++)
		cp_intc_write(~0, CP_INTC_SYS_STAT_CLR(i));

	/* Enable nIRQ (what about nFIQ?) */
	cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET);

	/*
	 * Priority is determined by host channel: lower channel number has
	 * higher priority i.e. channel 0 has highest priority and channel 31
	 * had the lowest priority.
	 */
	num_reg = (num_irq + 3) >> 2;	/* 4 channels per register */
	if (irq_prio) {
		unsigned j, k;
		u32 val;

		for (k = i = 0; i < num_reg; i++) {
			for (val = j = 0; j < 4; j++, k++) {
				val >>= 8;
				if (k < num_irq)
					val |= irq_prio[k] << 24;
			}

			cp_intc_write(val, CP_INTC_CHAN_MAP(i));
		}
	} else	{
		/*
		 * Default everything to channel 15 if priority not specified.
		 * Note that channel 0-1 are mapped to nFIQ and channels 2-31
		 * are mapped to nIRQ.
		 */
		for (i = 0; i < num_reg; i++)
			cp_intc_write(0x0f0f0f0f, CP_INTC_CHAN_MAP(i));
	}

	if (host_map)
		for (i = 0; host_map[i] != -1; i++)
			cp_intc_write(host_map[i], CP_INTC_HOST_MAP(i));

	irq_base = irq_alloc_descs(-1, 0, num_irq, 0);
	if (irq_base < 0) {
		pr_warn("Couldn't allocate IRQ numbers\n");
		irq_base = 0;
	}

	/* create a legacy host */
	cp_intc_domain = irq_domain_add_legacy(node, num_irq,
					irq_base, 0, &cp_intc_host_ops, NULL);

	if (!cp_intc_domain) {
		pr_err("cp_intc: failed to allocate irq host!\n");
		return -EINVAL;
	}

	/* Enable global interrupt */
	cp_intc_write(1, CP_INTC_GLOBAL_ENABLE);

	return 0;
}

void __init cp_intc_init(void)
{
	cp_intc_of_init(NULL, NULL);
}

IRQCHIP_DECLARE(cp_intc, "ti,cp-intc", cp_intc_of_init);
Commit	Line	Data
0521444d SS	1	/*
	2	* TI Common Platform Interrupt Controller (cp_intc) driver
	3	*
	4	* Author: Steve Chen <schen@mvista.com>
	5	* Copyright (C) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
	6	*
	7	* This file is licensed under the terms of the GNU General Public License
	8	* version 2. This program is licensed "as is" without any warranty of any
	9	* kind, whether express or implied.
	10	*/
	11
07caba96	12	#include <linux/export.h>
0521444d	13	#include <linux/init.h>
0521444d	14	#include <linux/irq.h>
9a7f2fc8	15	#include <linux/irqchip.h>
07caba96	16	#include <linux/irqdomain.h>
0521444d	17	#include <linux/io.h>
961e657f HS	18	#include <linux/of.h>
	19	#include <linux/of_address.h>
	20	#include <linux/of_irq.h>
0521444d	21
bd808947	22	#include <mach/common.h>
3acf731c	23	#include "cp_intc.h"
0521444d	24
0521444d SS	25	static inline unsigned int cp_intc_read(unsigned offset)
0521444d SS	26	{
bd808947	27	return __raw_readl(davinci_intc_base + offset);
0521444d SS	28	}
	29
	30	static inline void cp_intc_write(unsigned long value, unsigned offset)
	31	{
bd808947	32	__raw_writel(value, davinci_intc_base + offset);
0521444d SS	33	}
0521444d SS	34
23265442	35	static void cp_intc_ack_irq(struct irq_data *d)
0521444d	36	{
07caba96	37	cp_intc_write(d->hwirq, CP_INTC_SYS_STAT_IDX_CLR);
0521444d SS	38	}
	39
	40	/* Disable interrupt */
23265442	41	static void cp_intc_mask_irq(struct irq_data *d)
0521444d SS	42	{
	43	/* XXX don't know why we need to disable nIRQ here... */
	44	cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_CLR);
07caba96	45	cp_intc_write(d->hwirq, CP_INTC_SYS_ENABLE_IDX_CLR);
0521444d SS	46	cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET);
	47	}
	48
	49	/* Enable interrupt */
23265442	50	static void cp_intc_unmask_irq(struct irq_data *d)
0521444d	51	{
07caba96	52	cp_intc_write(d->hwirq, CP_INTC_SYS_ENABLE_IDX_SET);
0521444d SS	53	}
0521444d SS	54
23265442	55	static int cp_intc_set_irq_type(struct irq_data *d, unsigned int flow_type)
0521444d	56	{
07caba96 HS	57	unsigned reg = BIT_WORD(d->hwirq);
07caba96 HS	58	unsigned mask = BIT_MASK(d->hwirq);
0521444d SS	59	unsigned polarity = cp_intc_read(CP_INTC_SYS_POLARITY(reg));
	60	unsigned type = cp_intc_read(CP_INTC_SYS_TYPE(reg));
	61
	62	switch (flow_type) {
	63	case IRQ_TYPE_EDGE_RISING:
	64	polarity \|= mask;
	65	type \|= mask;
	66	break;
	67	case IRQ_TYPE_EDGE_FALLING:
	68	polarity &= ~mask;
	69	type \|= mask;
	70	break;
	71	case IRQ_TYPE_LEVEL_HIGH:
	72	polarity \|= mask;
	73	type &= ~mask;
	74	break;
	75	case IRQ_TYPE_LEVEL_LOW:
	76	polarity &= ~mask;
	77	type &= ~mask;
	78	break;
	79	default:
	80	return -EINVAL;
	81	}
	82
	83	cp_intc_write(polarity, CP_INTC_SYS_POLARITY(reg));
	84	cp_intc_write(type, CP_INTC_SYS_TYPE(reg));
	85
	86	return 0;
	87	}
	88
	89	static struct irq_chip cp_intc_irq_chip = {
	90	.name = "cp_intc",
23265442 LB	91	.irq_ack = cp_intc_ack_irq,
	92	.irq_mask = cp_intc_mask_irq,
	93	.irq_unmask = cp_intc_unmask_irq,
	94	.irq_set_type = cp_intc_set_irq_type,
3f86e570	95	.flags = IRQCHIP_SKIP_SET_WAKE,
0521444d SS	96	};
0521444d SS	97
07caba96 HS	98	static struct irq_domain *cp_intc_domain;
	99
	100	static int cp_intc_host_map(struct irq_domain *h, unsigned int virq,
	101	irq_hw_number_t hw)
	102	{
	103	pr_debug("cp_intc_host_map(%d, 0x%lx)\n", virq, hw);
	104
	105	irq_set_chip(virq, &cp_intc_irq_chip);
e8d36d5d	106	irq_set_probe(virq);
07caba96 HS	107	irq_set_handler(virq, handle_edge_irq);
	108	return 0;
	109	}
	110
	111	static const struct irq_domain_ops cp_intc_host_ops = {
	112	.map = cp_intc_host_map,
	113	.xlate = irq_domain_xlate_onetwocell,
	114	};
	115
961e657f	116	int __init cp_intc_of_init(struct device_node node, struct device_node parent)
0521444d	117	{
07caba96	118	u32 num_irq = davinci_soc_info.intc_irq_num;
bd808947 CC	119	u8 *irq_prio = davinci_soc_info.intc_irq_prios;
bd808947 CC	120	u32 *host_map = davinci_soc_info.intc_host_map;
0521444d	121	unsigned num_reg = BITS_TO_LONGS(num_irq);
07caba96	122	int i, irq_base;
0521444d	123
bd808947	124	davinci_intc_type = DAVINCI_INTC_TYPE_CP_INTC;
961e657f HS	125	if (node) {
	126	davinci_intc_base = of_iomap(node, 0);
	127	if (of_property_read_u32(node, "ti,intc-size", &num_irq))
	128	pr_warn("unable to get intc-size, default to %d\n",
	129	num_irq);
	130	} else {
	131	davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K);
	132	}
bd808947	133	if (WARN_ON(!davinci_intc_base))
07caba96	134	return -EINVAL;
0521444d SS	135
	136	cp_intc_write(0, CP_INTC_GLOBAL_ENABLE);
	137
	138	/* Disable all host interrupts */
	139	cp_intc_write(0, CP_INTC_HOST_ENABLE(0));
	140
	141	/* Disable system interrupts */
	142	for (i = 0; i < num_reg; i++)
	143	cp_intc_write(~0, CP_INTC_SYS_ENABLE_CLR(i));
	144
	145	/* Set to normal mode, no nesting, no priority hold */
	146	cp_intc_write(0, CP_INTC_CTRL);
	147	cp_intc_write(0, CP_INTC_HOST_CTRL);
	148
	149	/* Clear system interrupt status */
	150	for (i = 0; i < num_reg; i++)
	151	cp_intc_write(~0, CP_INTC_SYS_STAT_CLR(i));
	152
	153	/* Enable nIRQ (what about nFIQ?) */
	154	cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET);
	155
	156	/*
	157	* Priority is determined by host channel: lower channel number has
	158	* higher priority i.e. channel 0 has highest priority and channel 31
	159	* had the lowest priority.
	160	*/
	161	num_reg = (num_irq + 3) >> 2; /* 4 channels per register */
	162	if (irq_prio) {
	163	unsigned j, k;
	164	u32 val;
	165
	166	for (k = i = 0; i < num_reg; i++) {
	167	for (val = j = 0; j < 4; j++, k++) {
	168	val >>= 8;
	169	if (k < num_irq)
	170	val \|= irq_prio[k] << 24;
	171	}
	172
	173	cp_intc_write(val, CP_INTC_CHAN_MAP(i));
	174	}
	175	} else {
	176	/*
	177	* Default everything to channel 15 if priority not specified.
	178	* Note that channel 0-1 are mapped to nFIQ and channels 2-31
	179	* are mapped to nIRQ.
	180	*/
	181	for (i = 0; i < num_reg; i++)
	182	cp_intc_write(0x0f0f0f0f, CP_INTC_CHAN_MAP(i));
	183	}
	184
449ef7f6 CC	185	if (host_map)
	186	for (i = 0; host_map[i] != -1; i++)
	187	cp_intc_write(host_map[i], CP_INTC_HOST_MAP(i));
	188
07caba96 HS	189	irq_base = irq_alloc_descs(-1, 0, num_irq, 0);
	190	if (irq_base < 0) {
	191	pr_warn("Couldn't allocate IRQ numbers\n");
	192	irq_base = 0;
	193	}
	194
	195	/* create a legacy host */
	196	cp_intc_domain = irq_domain_add_legacy(node, num_irq,
	197	irq_base, 0, &cp_intc_host_ops, NULL);
	198
	199	if (!cp_intc_domain) {
	200	pr_err("cp_intc: failed to allocate irq host!\n");
	201	return -EINVAL;
0521444d SS	202	}
	203
	204	/* Enable global interrupt */
	205	cp_intc_write(1, CP_INTC_GLOBAL_ENABLE);
07caba96 HS	206
	207	return 0;
	208	}
	209
	210	void __init cp_intc_init(void)
	211	{
961e657f	212	cp_intc_of_init(NULL, NULL);
0521444d	213	}
9a7f2fc8 DL	214
9a7f2fc8 DL	215	IRQCHIP_DECLARE(cp_intc, "ti,cp-intc", cp_intc_of_init);