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a6c0f6ec SN |
1 | /* |
2 | * CPU idle for DaVinci SoCs | |
3 | * | |
4 | * Copyright (C) 2009 Texas Instruments Incorporated. http://www.ti.com/ | |
5 | * | |
6 | * Derived from Marvell Kirkwood CPU idle code | |
7 | * (arch/arm/mach-kirkwood/cpuidle.c) | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/cpuidle.h> | |
18 | #include <linux/io.h> | |
dc28094b | 19 | #include <linux/export.h> |
a6c0f6ec | 20 | #include <asm/proc-fns.h> |
19976c2a | 21 | #include <asm/cpuidle.h> |
a6c0f6ec SN |
22 | |
23 | #include <mach/cpuidle.h> | |
0020afb3 | 24 | #include <mach/ddr2.h> |
a6c0f6ec SN |
25 | |
26 | #define DAVINCI_CPUIDLE_MAX_STATES 2 | |
27 | ||
28 | struct davinci_ops { | |
5af4a21c DL |
29 | void (*enter) (void); |
30 | void (*exit) (void); | |
a6c0f6ec SN |
31 | u32 flags; |
32 | }; | |
33 | ||
19976c2a RL |
34 | /* Actual code that puts the SoC in different idle states */ |
35 | static int davinci_enter_idle(struct cpuidle_device *dev, | |
36 | struct cpuidle_driver *drv, | |
37 | int index) | |
38 | { | |
39 | struct cpuidle_state_usage *state_usage = &dev->states_usage[index]; | |
40 | struct davinci_ops *ops = cpuidle_get_statedata(state_usage); | |
41 | ||
42 | if (ops && ops->enter) | |
5af4a21c | 43 | ops->enter(); |
19976c2a RL |
44 | |
45 | index = cpuidle_wrap_enter(dev, drv, index, | |
46 | arm_cpuidle_simple_enter); | |
47 | ||
48 | if (ops && ops->exit) | |
5af4a21c | 49 | ops->exit(); |
19976c2a RL |
50 | |
51 | return index; | |
52 | } | |
53 | ||
a6c0f6ec | 54 | static struct cpuidle_driver davinci_idle_driver = { |
6a6ea0ac RL |
55 | .name = "cpuidle-davinci", |
56 | .owner = THIS_MODULE, | |
57 | .en_core_tk_irqen = 1, | |
58 | .states[0] = ARM_CPUIDLE_WFI_STATE, | |
59 | .states[1] = { | |
19976c2a RL |
60 | .enter = davinci_enter_idle, |
61 | .exit_latency = 10, | |
62 | .target_residency = 100000, | |
63 | .flags = CPUIDLE_FLAG_TIME_VALID, | |
64 | .name = "DDR SR", | |
65 | .desc = "WFI and DDR Self Refresh", | |
66 | }, | |
67 | .state_count = DAVINCI_CPUIDLE_MAX_STATES, | |
a6c0f6ec SN |
68 | }; |
69 | ||
70 | static DEFINE_PER_CPU(struct cpuidle_device, davinci_cpuidle_device); | |
71 | static void __iomem *ddr2_reg_base; | |
5af4a21c | 72 | static bool ddr2_pdown; |
a6c0f6ec | 73 | |
a6c0f6ec SN |
74 | static void davinci_save_ddr_power(int enter, bool pdown) |
75 | { | |
76 | u32 val; | |
77 | ||
78 | val = __raw_readl(ddr2_reg_base + DDR2_SDRCR_OFFSET); | |
79 | ||
80 | if (enter) { | |
81 | if (pdown) | |
82 | val |= DDR2_SRPD_BIT; | |
83 | else | |
84 | val &= ~DDR2_SRPD_BIT; | |
85 | val |= DDR2_LPMODEN_BIT; | |
86 | } else { | |
87 | val &= ~(DDR2_SRPD_BIT | DDR2_LPMODEN_BIT); | |
88 | } | |
89 | ||
90 | __raw_writel(val, ddr2_reg_base + DDR2_SDRCR_OFFSET); | |
91 | } | |
92 | ||
5af4a21c | 93 | static void davinci_c2state_enter(void) |
a6c0f6ec | 94 | { |
5af4a21c | 95 | davinci_save_ddr_power(1, ddr2_pdown); |
a6c0f6ec SN |
96 | } |
97 | ||
5af4a21c | 98 | static void davinci_c2state_exit(void) |
a6c0f6ec | 99 | { |
5af4a21c | 100 | davinci_save_ddr_power(0, ddr2_pdown); |
a6c0f6ec SN |
101 | } |
102 | ||
103 | static struct davinci_ops davinci_states[DAVINCI_CPUIDLE_MAX_STATES] = { | |
104 | [1] = { | |
105 | .enter = davinci_c2state_enter, | |
106 | .exit = davinci_c2state_exit, | |
107 | }, | |
108 | }; | |
109 | ||
a6c0f6ec SN |
110 | static int __init davinci_cpuidle_probe(struct platform_device *pdev) |
111 | { | |
112 | int ret; | |
113 | struct cpuidle_device *device; | |
114 | struct davinci_cpuidle_config *pdata = pdev->dev.platform_data; | |
a6c0f6ec SN |
115 | |
116 | device = &per_cpu(davinci_cpuidle_device, smp_processor_id()); | |
117 | ||
118 | if (!pdata) { | |
119 | dev_err(&pdev->dev, "cannot get platform data\n"); | |
120 | return -ENOENT; | |
121 | } | |
122 | ||
948c66df | 123 | ddr2_reg_base = pdata->ddr2_ctlr_base; |
a6c0f6ec | 124 | |
5af4a21c | 125 | ddr2_pdown = pdata->ddr2_pdown; |
4202735e | 126 | cpuidle_set_statedata(&device->states_usage[1], &davinci_states[1]); |
a6c0f6ec SN |
127 | |
128 | device->state_count = DAVINCI_CPUIDLE_MAX_STATES; | |
46bcfad7 DD |
129 | |
130 | ret = cpuidle_register_driver(&davinci_idle_driver); | |
131 | if (ret) { | |
132 | dev_err(&pdev->dev, "failed to register driver\n"); | |
133 | return ret; | |
134 | } | |
a6c0f6ec SN |
135 | |
136 | ret = cpuidle_register_device(device); | |
137 | if (ret) { | |
138 | dev_err(&pdev->dev, "failed to register device\n"); | |
948c66df SN |
139 | cpuidle_unregister_driver(&davinci_idle_driver); |
140 | return ret; | |
a6c0f6ec SN |
141 | } |
142 | ||
143 | return 0; | |
a6c0f6ec SN |
144 | } |
145 | ||
146 | static struct platform_driver davinci_cpuidle_driver = { | |
147 | .driver = { | |
148 | .name = "cpuidle-davinci", | |
149 | .owner = THIS_MODULE, | |
150 | }, | |
151 | }; | |
152 | ||
153 | static int __init davinci_cpuidle_init(void) | |
154 | { | |
155 | return platform_driver_probe(&davinci_cpuidle_driver, | |
156 | davinci_cpuidle_probe); | |
157 | } | |
158 | device_initcall(davinci_cpuidle_init); | |
159 |