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a6c0f6ec SN |
1 | /* |
2 | * CPU idle for DaVinci SoCs | |
3 | * | |
4 | * Copyright (C) 2009 Texas Instruments Incorporated. http://www.ti.com/ | |
5 | * | |
6 | * Derived from Marvell Kirkwood CPU idle code | |
7 | * (arch/arm/mach-kirkwood/cpuidle.c) | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/cpuidle.h> | |
18 | #include <linux/io.h> | |
dc28094b | 19 | #include <linux/export.h> |
a6c0f6ec | 20 | #include <asm/proc-fns.h> |
19976c2a | 21 | #include <asm/cpuidle.h> |
a6c0f6ec SN |
22 | |
23 | #include <mach/cpuidle.h> | |
0020afb3 | 24 | #include <mach/ddr2.h> |
a6c0f6ec SN |
25 | |
26 | #define DAVINCI_CPUIDLE_MAX_STATES 2 | |
27 | ||
28 | struct davinci_ops { | |
29 | void (*enter) (u32 flags); | |
30 | void (*exit) (u32 flags); | |
31 | u32 flags; | |
32 | }; | |
33 | ||
19976c2a RL |
34 | /* Actual code that puts the SoC in different idle states */ |
35 | static int davinci_enter_idle(struct cpuidle_device *dev, | |
36 | struct cpuidle_driver *drv, | |
37 | int index) | |
38 | { | |
39 | struct cpuidle_state_usage *state_usage = &dev->states_usage[index]; | |
40 | struct davinci_ops *ops = cpuidle_get_statedata(state_usage); | |
41 | ||
42 | if (ops && ops->enter) | |
43 | ops->enter(ops->flags); | |
44 | ||
45 | index = cpuidle_wrap_enter(dev, drv, index, | |
46 | arm_cpuidle_simple_enter); | |
47 | ||
48 | if (ops && ops->exit) | |
49 | ops->exit(ops->flags); | |
50 | ||
51 | return index; | |
52 | } | |
53 | ||
a6c0f6ec SN |
54 | /* fields in davinci_ops.flags */ |
55 | #define DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN BIT(0) | |
56 | ||
57 | static struct cpuidle_driver davinci_idle_driver = { | |
6a6ea0ac RL |
58 | .name = "cpuidle-davinci", |
59 | .owner = THIS_MODULE, | |
60 | .en_core_tk_irqen = 1, | |
61 | .states[0] = ARM_CPUIDLE_WFI_STATE, | |
62 | .states[1] = { | |
19976c2a RL |
63 | .enter = davinci_enter_idle, |
64 | .exit_latency = 10, | |
65 | .target_residency = 100000, | |
66 | .flags = CPUIDLE_FLAG_TIME_VALID, | |
67 | .name = "DDR SR", | |
68 | .desc = "WFI and DDR Self Refresh", | |
69 | }, | |
70 | .state_count = DAVINCI_CPUIDLE_MAX_STATES, | |
a6c0f6ec SN |
71 | }; |
72 | ||
73 | static DEFINE_PER_CPU(struct cpuidle_device, davinci_cpuidle_device); | |
74 | static void __iomem *ddr2_reg_base; | |
75 | ||
a6c0f6ec SN |
76 | static void davinci_save_ddr_power(int enter, bool pdown) |
77 | { | |
78 | u32 val; | |
79 | ||
80 | val = __raw_readl(ddr2_reg_base + DDR2_SDRCR_OFFSET); | |
81 | ||
82 | if (enter) { | |
83 | if (pdown) | |
84 | val |= DDR2_SRPD_BIT; | |
85 | else | |
86 | val &= ~DDR2_SRPD_BIT; | |
87 | val |= DDR2_LPMODEN_BIT; | |
88 | } else { | |
89 | val &= ~(DDR2_SRPD_BIT | DDR2_LPMODEN_BIT); | |
90 | } | |
91 | ||
92 | __raw_writel(val, ddr2_reg_base + DDR2_SDRCR_OFFSET); | |
93 | } | |
94 | ||
95 | static void davinci_c2state_enter(u32 flags) | |
96 | { | |
97 | davinci_save_ddr_power(1, !!(flags & DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN)); | |
98 | } | |
99 | ||
100 | static void davinci_c2state_exit(u32 flags) | |
101 | { | |
102 | davinci_save_ddr_power(0, !!(flags & DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN)); | |
103 | } | |
104 | ||
105 | static struct davinci_ops davinci_states[DAVINCI_CPUIDLE_MAX_STATES] = { | |
106 | [1] = { | |
107 | .enter = davinci_c2state_enter, | |
108 | .exit = davinci_c2state_exit, | |
109 | }, | |
110 | }; | |
111 | ||
a6c0f6ec SN |
112 | static int __init davinci_cpuidle_probe(struct platform_device *pdev) |
113 | { | |
114 | int ret; | |
115 | struct cpuidle_device *device; | |
116 | struct davinci_cpuidle_config *pdata = pdev->dev.platform_data; | |
a6c0f6ec SN |
117 | |
118 | device = &per_cpu(davinci_cpuidle_device, smp_processor_id()); | |
119 | ||
120 | if (!pdata) { | |
121 | dev_err(&pdev->dev, "cannot get platform data\n"); | |
122 | return -ENOENT; | |
123 | } | |
124 | ||
948c66df | 125 | ddr2_reg_base = pdata->ddr2_ctlr_base; |
a6c0f6ec | 126 | |
a6c0f6ec SN |
127 | if (pdata->ddr2_pdown) |
128 | davinci_states[1].flags |= DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN; | |
4202735e | 129 | cpuidle_set_statedata(&device->states_usage[1], &davinci_states[1]); |
a6c0f6ec SN |
130 | |
131 | device->state_count = DAVINCI_CPUIDLE_MAX_STATES; | |
46bcfad7 DD |
132 | |
133 | ret = cpuidle_register_driver(&davinci_idle_driver); | |
134 | if (ret) { | |
135 | dev_err(&pdev->dev, "failed to register driver\n"); | |
136 | return ret; | |
137 | } | |
a6c0f6ec SN |
138 | |
139 | ret = cpuidle_register_device(device); | |
140 | if (ret) { | |
141 | dev_err(&pdev->dev, "failed to register device\n"); | |
948c66df SN |
142 | cpuidle_unregister_driver(&davinci_idle_driver); |
143 | return ret; | |
a6c0f6ec SN |
144 | } |
145 | ||
146 | return 0; | |
a6c0f6ec SN |
147 | } |
148 | ||
149 | static struct platform_driver davinci_cpuidle_driver = { | |
150 | .driver = { | |
151 | .name = "cpuidle-davinci", | |
152 | .owner = THIS_MODULE, | |
153 | }, | |
154 | }; | |
155 | ||
156 | static int __init davinci_cpuidle_init(void) | |
157 | { | |
158 | return platform_driver_probe(&davinci_cpuidle_driver, | |
159 | davinci_cpuidle_probe); | |
160 | } | |
161 | device_initcall(davinci_cpuidle_init); | |
162 |