ARM: kirkwood: Consolidate time keeping and irq enable
[deliverable/linux.git] / arch / arm / mach-davinci / cpuidle.c
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1/*
2 * CPU idle for DaVinci SoCs
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated. http://www.ti.com/
5 *
6 * Derived from Marvell Kirkwood CPU idle code
7 * (arch/arm/mach-kirkwood/cpuidle.c)
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/platform_device.h>
17#include <linux/cpuidle.h>
18#include <linux/io.h>
dc28094b 19#include <linux/export.h>
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20#include <asm/proc-fns.h>
21
22#include <mach/cpuidle.h>
0020afb3 23#include <mach/ddr2.h>
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24
25#define DAVINCI_CPUIDLE_MAX_STATES 2
26
27struct davinci_ops {
28 void (*enter) (u32 flags);
29 void (*exit) (u32 flags);
30 u32 flags;
31};
32
33/* fields in davinci_ops.flags */
34#define DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN BIT(0)
35
36static struct cpuidle_driver davinci_idle_driver = {
37 .name = "cpuidle-davinci",
38 .owner = THIS_MODULE,
39};
40
41static DEFINE_PER_CPU(struct cpuidle_device, davinci_cpuidle_device);
42static void __iomem *ddr2_reg_base;
43
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44static void davinci_save_ddr_power(int enter, bool pdown)
45{
46 u32 val;
47
48 val = __raw_readl(ddr2_reg_base + DDR2_SDRCR_OFFSET);
49
50 if (enter) {
51 if (pdown)
52 val |= DDR2_SRPD_BIT;
53 else
54 val &= ~DDR2_SRPD_BIT;
55 val |= DDR2_LPMODEN_BIT;
56 } else {
57 val &= ~(DDR2_SRPD_BIT | DDR2_LPMODEN_BIT);
58 }
59
60 __raw_writel(val, ddr2_reg_base + DDR2_SDRCR_OFFSET);
61}
62
63static void davinci_c2state_enter(u32 flags)
64{
65 davinci_save_ddr_power(1, !!(flags & DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN));
66}
67
68static void davinci_c2state_exit(u32 flags)
69{
70 davinci_save_ddr_power(0, !!(flags & DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN));
71}
72
73static struct davinci_ops davinci_states[DAVINCI_CPUIDLE_MAX_STATES] = {
74 [1] = {
75 .enter = davinci_c2state_enter,
76 .exit = davinci_c2state_exit,
77 },
78};
79
80/* Actual code that puts the SoC in different idle states */
81static int davinci_enter_idle(struct cpuidle_device *dev,
46bcfad7 82 struct cpuidle_driver *drv,
e978aa7d 83 int index)
a6c0f6ec 84{
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85 struct cpuidle_state_usage *state_usage = &dev->states_usage[index];
86 struct davinci_ops *ops = cpuidle_get_statedata(state_usage);
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87 struct timeval before, after;
88 int idle_time;
89
90 local_irq_disable();
91 do_gettimeofday(&before);
92
93 if (ops && ops->enter)
94 ops->enter(ops->flags);
95 /* Wait for interrupt state */
96 cpu_do_idle();
97 if (ops && ops->exit)
98 ops->exit(ops->flags);
99
100 do_gettimeofday(&after);
101 local_irq_enable();
102 idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
103 (after.tv_usec - before.tv_usec);
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104
105 dev->last_residency = idle_time;
106
107 return index;
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108}
109
110static int __init davinci_cpuidle_probe(struct platform_device *pdev)
111{
112 int ret;
113 struct cpuidle_device *device;
46bcfad7 114 struct cpuidle_driver *driver = &davinci_idle_driver;
a6c0f6ec 115 struct davinci_cpuidle_config *pdata = pdev->dev.platform_data;
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116
117 device = &per_cpu(davinci_cpuidle_device, smp_processor_id());
118
119 if (!pdata) {
120 dev_err(&pdev->dev, "cannot get platform data\n");
121 return -ENOENT;
122 }
123
948c66df 124 ddr2_reg_base = pdata->ddr2_ctlr_base;
a6c0f6ec 125
a6c0f6ec 126 /* Wait for interrupt state */
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127 driver->states[0].enter = davinci_enter_idle;
128 driver->states[0].exit_latency = 1;
129 driver->states[0].target_residency = 10000;
130 driver->states[0].flags = CPUIDLE_FLAG_TIME_VALID;
131 strcpy(driver->states[0].name, "WFI");
132 strcpy(driver->states[0].desc, "Wait for interrupt");
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133
134 /* Wait for interrupt and DDR self refresh state */
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135 driver->states[1].enter = davinci_enter_idle;
136 driver->states[1].exit_latency = 10;
137 driver->states[1].target_residency = 10000;
138 driver->states[1].flags = CPUIDLE_FLAG_TIME_VALID;
139 strcpy(driver->states[1].name, "DDR SR");
140 strcpy(driver->states[1].desc, "WFI and DDR Self Refresh");
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141 if (pdata->ddr2_pdown)
142 davinci_states[1].flags |= DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN;
4202735e 143 cpuidle_set_statedata(&device->states_usage[1], &davinci_states[1]);
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144
145 device->state_count = DAVINCI_CPUIDLE_MAX_STATES;
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146 driver->state_count = DAVINCI_CPUIDLE_MAX_STATES;
147
148 ret = cpuidle_register_driver(&davinci_idle_driver);
149 if (ret) {
150 dev_err(&pdev->dev, "failed to register driver\n");
151 return ret;
152 }
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153
154 ret = cpuidle_register_device(device);
155 if (ret) {
156 dev_err(&pdev->dev, "failed to register device\n");
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157 cpuidle_unregister_driver(&davinci_idle_driver);
158 return ret;
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159 }
160
161 return 0;
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162}
163
164static struct platform_driver davinci_cpuidle_driver = {
165 .driver = {
166 .name = "cpuidle-davinci",
167 .owner = THIS_MODULE,
168 },
169};
170
171static int __init davinci_cpuidle_init(void)
172{
173 return platform_driver_probe(&davinci_cpuidle_driver,
174 davinci_cpuidle_probe);
175}
176device_initcall(davinci_cpuidle_init);
177
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