davinci: make it possible to include clock.h and psc.h in assembly code
[deliverable/linux.git] / arch / arm / mach-davinci / cpuidle.c
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1/*
2 * CPU idle for DaVinci SoCs
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated. http://www.ti.com/
5 *
6 * Derived from Marvell Kirkwood CPU idle code
7 * (arch/arm/mach-kirkwood/cpuidle.c)
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/platform_device.h>
17#include <linux/cpuidle.h>
18#include <linux/io.h>
19#include <asm/proc-fns.h>
20
21#include <mach/cpuidle.h>
7ec4b243 22#include <mach/memory.h>
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23
24#define DAVINCI_CPUIDLE_MAX_STATES 2
25
26struct davinci_ops {
27 void (*enter) (u32 flags);
28 void (*exit) (u32 flags);
29 u32 flags;
30};
31
32/* fields in davinci_ops.flags */
33#define DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN BIT(0)
34
35static struct cpuidle_driver davinci_idle_driver = {
36 .name = "cpuidle-davinci",
37 .owner = THIS_MODULE,
38};
39
40static DEFINE_PER_CPU(struct cpuidle_device, davinci_cpuidle_device);
41static void __iomem *ddr2_reg_base;
42
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43static void davinci_save_ddr_power(int enter, bool pdown)
44{
45 u32 val;
46
47 val = __raw_readl(ddr2_reg_base + DDR2_SDRCR_OFFSET);
48
49 if (enter) {
50 if (pdown)
51 val |= DDR2_SRPD_BIT;
52 else
53 val &= ~DDR2_SRPD_BIT;
54 val |= DDR2_LPMODEN_BIT;
55 } else {
56 val &= ~(DDR2_SRPD_BIT | DDR2_LPMODEN_BIT);
57 }
58
59 __raw_writel(val, ddr2_reg_base + DDR2_SDRCR_OFFSET);
60}
61
62static void davinci_c2state_enter(u32 flags)
63{
64 davinci_save_ddr_power(1, !!(flags & DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN));
65}
66
67static void davinci_c2state_exit(u32 flags)
68{
69 davinci_save_ddr_power(0, !!(flags & DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN));
70}
71
72static struct davinci_ops davinci_states[DAVINCI_CPUIDLE_MAX_STATES] = {
73 [1] = {
74 .enter = davinci_c2state_enter,
75 .exit = davinci_c2state_exit,
76 },
77};
78
79/* Actual code that puts the SoC in different idle states */
80static int davinci_enter_idle(struct cpuidle_device *dev,
81 struct cpuidle_state *state)
82{
83 struct davinci_ops *ops = cpuidle_get_statedata(state);
84 struct timeval before, after;
85 int idle_time;
86
87 local_irq_disable();
88 do_gettimeofday(&before);
89
90 if (ops && ops->enter)
91 ops->enter(ops->flags);
92 /* Wait for interrupt state */
93 cpu_do_idle();
94 if (ops && ops->exit)
95 ops->exit(ops->flags);
96
97 do_gettimeofday(&after);
98 local_irq_enable();
99 idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
100 (after.tv_usec - before.tv_usec);
101 return idle_time;
102}
103
104static int __init davinci_cpuidle_probe(struct platform_device *pdev)
105{
106 int ret;
107 struct cpuidle_device *device;
108 struct davinci_cpuidle_config *pdata = pdev->dev.platform_data;
109 struct resource *ddr2_regs;
110 resource_size_t len;
111
112 device = &per_cpu(davinci_cpuidle_device, smp_processor_id());
113
114 if (!pdata) {
115 dev_err(&pdev->dev, "cannot get platform data\n");
116 return -ENOENT;
117 }
118
119 ddr2_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
120 if (!ddr2_regs) {
121 dev_err(&pdev->dev, "cannot get DDR2 controller register base");
122 return -ENODEV;
123 }
124
125 len = resource_size(ddr2_regs);
126
127 ddr2_regs = request_mem_region(ddr2_regs->start, len, ddr2_regs->name);
128 if (!ddr2_regs)
129 return -EBUSY;
130
131 ddr2_reg_base = ioremap(ddr2_regs->start, len);
132 if (!ddr2_reg_base) {
133 ret = -ENOMEM;
134 goto ioremap_fail;
135 }
136
137 ret = cpuidle_register_driver(&davinci_idle_driver);
138 if (ret) {
139 dev_err(&pdev->dev, "failed to register driver\n");
140 goto driver_register_fail;
141 }
142
143 /* Wait for interrupt state */
144 device->states[0].enter = davinci_enter_idle;
145 device->states[0].exit_latency = 1;
146 device->states[0].target_residency = 10000;
147 device->states[0].flags = CPUIDLE_FLAG_TIME_VALID;
148 strcpy(device->states[0].name, "WFI");
149 strcpy(device->states[0].desc, "Wait for interrupt");
150
151 /* Wait for interrupt and DDR self refresh state */
152 device->states[1].enter = davinci_enter_idle;
153 device->states[1].exit_latency = 10;
154 device->states[1].target_residency = 10000;
155 device->states[1].flags = CPUIDLE_FLAG_TIME_VALID;
156 strcpy(device->states[1].name, "DDR SR");
157 strcpy(device->states[1].desc, "WFI and DDR Self Refresh");
158 if (pdata->ddr2_pdown)
159 davinci_states[1].flags |= DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN;
160 cpuidle_set_statedata(&device->states[1], &davinci_states[1]);
161
162 device->state_count = DAVINCI_CPUIDLE_MAX_STATES;
163
164 ret = cpuidle_register_device(device);
165 if (ret) {
166 dev_err(&pdev->dev, "failed to register device\n");
167 goto device_register_fail;
168 }
169
170 return 0;
171
172device_register_fail:
173 cpuidle_unregister_driver(&davinci_idle_driver);
174driver_register_fail:
175 iounmap(ddr2_reg_base);
176ioremap_fail:
177 release_mem_region(ddr2_regs->start, len);
178 return ret;
179}
180
181static struct platform_driver davinci_cpuidle_driver = {
182 .driver = {
183 .name = "cpuidle-davinci",
184 .owner = THIS_MODULE,
185 },
186};
187
188static int __init davinci_cpuidle_init(void)
189{
190 return platform_driver_probe(&davinci_cpuidle_driver,
191 davinci_cpuidle_probe);
192}
193device_initcall(davinci_cpuidle_init);
194
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