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55c79a40 MG |
1 | /* |
2 | * TI DA830/OMAP L137 chip specific setup | |
3 | * | |
4 | * Author: Mark A. Greer <mgreer@mvista.com> | |
5 | * | |
6 | * 2009 (c) MontaVista Software, Inc. This file is licensed under | |
7 | * the terms of the GNU General Public License version 2. This program | |
8 | * is licensed "as is" without any warranty of any kind, whether express | |
9 | * or implied. | |
10 | */ | |
2f8163ba | 11 | #include <linux/gpio.h> |
55c79a40 MG |
12 | #include <linux/init.h> |
13 | #include <linux/clk.h> | |
f606d38d | 14 | #include <linux/platform_data/gpio-davinci.h> |
55c79a40 MG |
15 | |
16 | #include <asm/mach/map.h> | |
17 | ||
3acf731c | 18 | #include "psc.h" |
55c79a40 MG |
19 | #include <mach/irqs.h> |
20 | #include <mach/cputype.h> | |
21 | #include <mach/common.h> | |
22 | #include <mach/time.h> | |
23 | #include <mach/da8xx.h> | |
24 | ||
25 | #include "clock.h" | |
26 | #include "mux.h" | |
27 | ||
55c79a40 MG |
28 | /* Offsets of the 8 compare registers on the da830 */ |
29 | #define DA830_CMP12_0 0x60 | |
30 | #define DA830_CMP12_1 0x64 | |
31 | #define DA830_CMP12_2 0x68 | |
32 | #define DA830_CMP12_3 0x6c | |
33 | #define DA830_CMP12_4 0x70 | |
34 | #define DA830_CMP12_5 0x74 | |
35 | #define DA830_CMP12_6 0x78 | |
36 | #define DA830_CMP12_7 0x7c | |
37 | ||
38 | #define DA830_REF_FREQ 24000000 | |
39 | ||
40 | static struct pll_data pll0_data = { | |
41 | .num = 1, | |
bea238f6 | 42 | .phys_base = DA8XX_PLL0_BASE, |
55c79a40 MG |
43 | .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV, |
44 | }; | |
45 | ||
46 | static struct clk ref_clk = { | |
47 | .name = "ref_clk", | |
48 | .rate = DA830_REF_FREQ, | |
49 | }; | |
50 | ||
51 | static struct clk pll0_clk = { | |
52 | .name = "pll0", | |
53 | .parent = &ref_clk, | |
54 | .pll_data = &pll0_data, | |
55 | .flags = CLK_PLL, | |
56 | }; | |
57 | ||
58 | static struct clk pll0_aux_clk = { | |
59 | .name = "pll0_aux_clk", | |
60 | .parent = &pll0_clk, | |
61 | .flags = CLK_PLL | PRE_PLL, | |
62 | }; | |
63 | ||
64 | static struct clk pll0_sysclk2 = { | |
65 | .name = "pll0_sysclk2", | |
66 | .parent = &pll0_clk, | |
67 | .flags = CLK_PLL, | |
68 | .div_reg = PLLDIV2, | |
69 | }; | |
70 | ||
71 | static struct clk pll0_sysclk3 = { | |
72 | .name = "pll0_sysclk3", | |
73 | .parent = &pll0_clk, | |
74 | .flags = CLK_PLL, | |
75 | .div_reg = PLLDIV3, | |
76 | }; | |
77 | ||
78 | static struct clk pll0_sysclk4 = { | |
79 | .name = "pll0_sysclk4", | |
80 | .parent = &pll0_clk, | |
81 | .flags = CLK_PLL, | |
82 | .div_reg = PLLDIV4, | |
83 | }; | |
84 | ||
85 | static struct clk pll0_sysclk5 = { | |
86 | .name = "pll0_sysclk5", | |
87 | .parent = &pll0_clk, | |
88 | .flags = CLK_PLL, | |
89 | .div_reg = PLLDIV5, | |
90 | }; | |
91 | ||
92 | static struct clk pll0_sysclk6 = { | |
93 | .name = "pll0_sysclk6", | |
94 | .parent = &pll0_clk, | |
95 | .flags = CLK_PLL, | |
96 | .div_reg = PLLDIV6, | |
97 | }; | |
98 | ||
99 | static struct clk pll0_sysclk7 = { | |
100 | .name = "pll0_sysclk7", | |
101 | .parent = &pll0_clk, | |
102 | .flags = CLK_PLL, | |
103 | .div_reg = PLLDIV7, | |
104 | }; | |
105 | ||
106 | static struct clk i2c0_clk = { | |
107 | .name = "i2c0", | |
108 | .parent = &pll0_aux_clk, | |
109 | }; | |
110 | ||
111 | static struct clk timerp64_0_clk = { | |
112 | .name = "timer0", | |
113 | .parent = &pll0_aux_clk, | |
114 | }; | |
115 | ||
116 | static struct clk timerp64_1_clk = { | |
117 | .name = "timer1", | |
118 | .parent = &pll0_aux_clk, | |
119 | }; | |
120 | ||
121 | static struct clk arm_rom_clk = { | |
122 | .name = "arm_rom", | |
123 | .parent = &pll0_sysclk2, | |
124 | .lpsc = DA8XX_LPSC0_ARM_RAM_ROM, | |
125 | .flags = ALWAYS_ENABLED, | |
126 | }; | |
127 | ||
128 | static struct clk scr0_ss_clk = { | |
129 | .name = "scr0_ss", | |
130 | .parent = &pll0_sysclk2, | |
131 | .lpsc = DA8XX_LPSC0_SCR0_SS, | |
132 | .flags = ALWAYS_ENABLED, | |
133 | }; | |
134 | ||
135 | static struct clk scr1_ss_clk = { | |
136 | .name = "scr1_ss", | |
137 | .parent = &pll0_sysclk2, | |
138 | .lpsc = DA8XX_LPSC0_SCR1_SS, | |
139 | .flags = ALWAYS_ENABLED, | |
140 | }; | |
141 | ||
142 | static struct clk scr2_ss_clk = { | |
143 | .name = "scr2_ss", | |
144 | .parent = &pll0_sysclk2, | |
145 | .lpsc = DA8XX_LPSC0_SCR2_SS, | |
146 | .flags = ALWAYS_ENABLED, | |
147 | }; | |
148 | ||
149 | static struct clk dmax_clk = { | |
150 | .name = "dmax", | |
151 | .parent = &pll0_sysclk2, | |
9a9fb12a | 152 | .lpsc = DA8XX_LPSC0_PRUSS, |
55c79a40 MG |
153 | .flags = ALWAYS_ENABLED, |
154 | }; | |
155 | ||
156 | static struct clk tpcc_clk = { | |
157 | .name = "tpcc", | |
158 | .parent = &pll0_sysclk2, | |
159 | .lpsc = DA8XX_LPSC0_TPCC, | |
160 | .flags = ALWAYS_ENABLED | CLK_PSC, | |
161 | }; | |
162 | ||
163 | static struct clk tptc0_clk = { | |
164 | .name = "tptc0", | |
165 | .parent = &pll0_sysclk2, | |
166 | .lpsc = DA8XX_LPSC0_TPTC0, | |
167 | .flags = ALWAYS_ENABLED, | |
168 | }; | |
169 | ||
170 | static struct clk tptc1_clk = { | |
171 | .name = "tptc1", | |
172 | .parent = &pll0_sysclk2, | |
173 | .lpsc = DA8XX_LPSC0_TPTC1, | |
174 | .flags = ALWAYS_ENABLED, | |
175 | }; | |
176 | ||
177 | static struct clk mmcsd_clk = { | |
178 | .name = "mmcsd", | |
179 | .parent = &pll0_sysclk2, | |
180 | .lpsc = DA8XX_LPSC0_MMC_SD, | |
181 | }; | |
182 | ||
183 | static struct clk uart0_clk = { | |
184 | .name = "uart0", | |
185 | .parent = &pll0_sysclk2, | |
186 | .lpsc = DA8XX_LPSC0_UART0, | |
187 | }; | |
188 | ||
189 | static struct clk uart1_clk = { | |
190 | .name = "uart1", | |
191 | .parent = &pll0_sysclk2, | |
192 | .lpsc = DA8XX_LPSC1_UART1, | |
789a785e | 193 | .gpsc = 1, |
55c79a40 MG |
194 | }; |
195 | ||
196 | static struct clk uart2_clk = { | |
197 | .name = "uart2", | |
198 | .parent = &pll0_sysclk2, | |
199 | .lpsc = DA8XX_LPSC1_UART2, | |
789a785e | 200 | .gpsc = 1, |
55c79a40 MG |
201 | }; |
202 | ||
203 | static struct clk spi0_clk = { | |
204 | .name = "spi0", | |
205 | .parent = &pll0_sysclk2, | |
206 | .lpsc = DA8XX_LPSC0_SPI0, | |
207 | }; | |
208 | ||
209 | static struct clk spi1_clk = { | |
210 | .name = "spi1", | |
211 | .parent = &pll0_sysclk2, | |
212 | .lpsc = DA8XX_LPSC1_SPI1, | |
789a785e | 213 | .gpsc = 1, |
55c79a40 MG |
214 | }; |
215 | ||
216 | static struct clk ecap0_clk = { | |
217 | .name = "ecap0", | |
218 | .parent = &pll0_sysclk2, | |
219 | .lpsc = DA8XX_LPSC1_ECAP, | |
789a785e | 220 | .gpsc = 1, |
55c79a40 MG |
221 | }; |
222 | ||
223 | static struct clk ecap1_clk = { | |
224 | .name = "ecap1", | |
225 | .parent = &pll0_sysclk2, | |
226 | .lpsc = DA8XX_LPSC1_ECAP, | |
789a785e | 227 | .gpsc = 1, |
55c79a40 MG |
228 | }; |
229 | ||
230 | static struct clk ecap2_clk = { | |
231 | .name = "ecap2", | |
232 | .parent = &pll0_sysclk2, | |
233 | .lpsc = DA8XX_LPSC1_ECAP, | |
789a785e | 234 | .gpsc = 1, |
55c79a40 MG |
235 | }; |
236 | ||
237 | static struct clk pwm0_clk = { | |
238 | .name = "pwm0", | |
239 | .parent = &pll0_sysclk2, | |
240 | .lpsc = DA8XX_LPSC1_PWM, | |
789a785e | 241 | .gpsc = 1, |
55c79a40 MG |
242 | }; |
243 | ||
244 | static struct clk pwm1_clk = { | |
245 | .name = "pwm1", | |
246 | .parent = &pll0_sysclk2, | |
247 | .lpsc = DA8XX_LPSC1_PWM, | |
789a785e | 248 | .gpsc = 1, |
55c79a40 MG |
249 | }; |
250 | ||
251 | static struct clk pwm2_clk = { | |
252 | .name = "pwm2", | |
253 | .parent = &pll0_sysclk2, | |
254 | .lpsc = DA8XX_LPSC1_PWM, | |
789a785e | 255 | .gpsc = 1, |
55c79a40 MG |
256 | }; |
257 | ||
258 | static struct clk eqep0_clk = { | |
259 | .name = "eqep0", | |
260 | .parent = &pll0_sysclk2, | |
261 | .lpsc = DA830_LPSC1_EQEP, | |
789a785e | 262 | .gpsc = 1, |
55c79a40 MG |
263 | }; |
264 | ||
265 | static struct clk eqep1_clk = { | |
266 | .name = "eqep1", | |
267 | .parent = &pll0_sysclk2, | |
268 | .lpsc = DA830_LPSC1_EQEP, | |
789a785e | 269 | .gpsc = 1, |
55c79a40 MG |
270 | }; |
271 | ||
272 | static struct clk lcdc_clk = { | |
273 | .name = "lcdc", | |
274 | .parent = &pll0_sysclk2, | |
275 | .lpsc = DA8XX_LPSC1_LCDC, | |
789a785e | 276 | .gpsc = 1, |
55c79a40 MG |
277 | }; |
278 | ||
279 | static struct clk mcasp0_clk = { | |
280 | .name = "mcasp0", | |
281 | .parent = &pll0_sysclk2, | |
282 | .lpsc = DA8XX_LPSC1_McASP0, | |
789a785e | 283 | .gpsc = 1, |
55c79a40 MG |
284 | }; |
285 | ||
286 | static struct clk mcasp1_clk = { | |
287 | .name = "mcasp1", | |
288 | .parent = &pll0_sysclk2, | |
289 | .lpsc = DA830_LPSC1_McASP1, | |
789a785e | 290 | .gpsc = 1, |
55c79a40 MG |
291 | }; |
292 | ||
293 | static struct clk mcasp2_clk = { | |
294 | .name = "mcasp2", | |
295 | .parent = &pll0_sysclk2, | |
296 | .lpsc = DA830_LPSC1_McASP2, | |
789a785e | 297 | .gpsc = 1, |
55c79a40 MG |
298 | }; |
299 | ||
300 | static struct clk usb20_clk = { | |
301 | .name = "usb20", | |
302 | .parent = &pll0_sysclk2, | |
303 | .lpsc = DA8XX_LPSC1_USB20, | |
789a785e | 304 | .gpsc = 1, |
55c79a40 MG |
305 | }; |
306 | ||
307 | static struct clk aemif_clk = { | |
308 | .name = "aemif", | |
309 | .parent = &pll0_sysclk3, | |
310 | .lpsc = DA8XX_LPSC0_EMIF25, | |
311 | .flags = ALWAYS_ENABLED, | |
312 | }; | |
313 | ||
314 | static struct clk aintc_clk = { | |
315 | .name = "aintc", | |
316 | .parent = &pll0_sysclk4, | |
317 | .lpsc = DA8XX_LPSC0_AINTC, | |
318 | .flags = ALWAYS_ENABLED, | |
319 | }; | |
320 | ||
321 | static struct clk secu_mgr_clk = { | |
322 | .name = "secu_mgr", | |
323 | .parent = &pll0_sysclk4, | |
324 | .lpsc = DA8XX_LPSC0_SECU_MGR, | |
325 | .flags = ALWAYS_ENABLED, | |
326 | }; | |
327 | ||
328 | static struct clk emac_clk = { | |
329 | .name = "emac", | |
330 | .parent = &pll0_sysclk4, | |
331 | .lpsc = DA8XX_LPSC1_CPGMAC, | |
789a785e | 332 | .gpsc = 1, |
55c79a40 MG |
333 | }; |
334 | ||
335 | static struct clk gpio_clk = { | |
336 | .name = "gpio", | |
337 | .parent = &pll0_sysclk4, | |
338 | .lpsc = DA8XX_LPSC1_GPIO, | |
789a785e | 339 | .gpsc = 1, |
55c79a40 MG |
340 | }; |
341 | ||
342 | static struct clk i2c1_clk = { | |
343 | .name = "i2c1", | |
344 | .parent = &pll0_sysclk4, | |
345 | .lpsc = DA8XX_LPSC1_I2C, | |
789a785e | 346 | .gpsc = 1, |
55c79a40 MG |
347 | }; |
348 | ||
349 | static struct clk usb11_clk = { | |
350 | .name = "usb11", | |
351 | .parent = &pll0_sysclk4, | |
352 | .lpsc = DA8XX_LPSC1_USB11, | |
789a785e | 353 | .gpsc = 1, |
55c79a40 MG |
354 | }; |
355 | ||
356 | static struct clk emif3_clk = { | |
357 | .name = "emif3", | |
358 | .parent = &pll0_sysclk5, | |
359 | .lpsc = DA8XX_LPSC1_EMIF3C, | |
789a785e | 360 | .gpsc = 1, |
55c79a40 | 361 | .flags = ALWAYS_ENABLED, |
55c79a40 MG |
362 | }; |
363 | ||
364 | static struct clk arm_clk = { | |
365 | .name = "arm", | |
366 | .parent = &pll0_sysclk6, | |
367 | .lpsc = DA8XX_LPSC0_ARM, | |
368 | .flags = ALWAYS_ENABLED, | |
369 | }; | |
370 | ||
371 | static struct clk rmii_clk = { | |
372 | .name = "rmii", | |
373 | .parent = &pll0_sysclk7, | |
374 | }; | |
375 | ||
08aca087 | 376 | static struct clk_lookup da830_clks[] = { |
55c79a40 MG |
377 | CLK(NULL, "ref", &ref_clk), |
378 | CLK(NULL, "pll0", &pll0_clk), | |
379 | CLK(NULL, "pll0_aux", &pll0_aux_clk), | |
380 | CLK(NULL, "pll0_sysclk2", &pll0_sysclk2), | |
381 | CLK(NULL, "pll0_sysclk3", &pll0_sysclk3), | |
382 | CLK(NULL, "pll0_sysclk4", &pll0_sysclk4), | |
383 | CLK(NULL, "pll0_sysclk5", &pll0_sysclk5), | |
384 | CLK(NULL, "pll0_sysclk6", &pll0_sysclk6), | |
385 | CLK(NULL, "pll0_sysclk7", &pll0_sysclk7), | |
386 | CLK("i2c_davinci.1", NULL, &i2c0_clk), | |
387 | CLK(NULL, "timer0", &timerp64_0_clk), | |
84374812 | 388 | CLK("davinci-wdt", NULL, &timerp64_1_clk), |
55c79a40 MG |
389 | CLK(NULL, "arm_rom", &arm_rom_clk), |
390 | CLK(NULL, "scr0_ss", &scr0_ss_clk), | |
391 | CLK(NULL, "scr1_ss", &scr1_ss_clk), | |
392 | CLK(NULL, "scr2_ss", &scr2_ss_clk), | |
393 | CLK(NULL, "dmax", &dmax_clk), | |
394 | CLK(NULL, "tpcc", &tpcc_clk), | |
395 | CLK(NULL, "tptc0", &tptc0_clk), | |
396 | CLK(NULL, "tptc1", &tptc1_clk), | |
d7ca4c75 | 397 | CLK("da830-mmc.0", NULL, &mmcsd_clk), |
19955c3d MP |
398 | CLK("serial8250.0", NULL, &uart0_clk), |
399 | CLK("serial8250.1", NULL, &uart1_clk), | |
400 | CLK("serial8250.2", NULL, &uart2_clk), | |
4918b40d MW |
401 | CLK("spi_davinci.0", NULL, &spi0_clk), |
402 | CLK("spi_davinci.1", NULL, &spi1_clk), | |
55c79a40 MG |
403 | CLK(NULL, "ecap0", &ecap0_clk), |
404 | CLK(NULL, "ecap1", &ecap1_clk), | |
405 | CLK(NULL, "ecap2", &ecap2_clk), | |
406 | CLK(NULL, "pwm0", &pwm0_clk), | |
407 | CLK(NULL, "pwm1", &pwm1_clk), | |
408 | CLK(NULL, "pwm2", &pwm2_clk), | |
409 | CLK("eqep.0", NULL, &eqep0_clk), | |
410 | CLK("eqep.1", NULL, &eqep1_clk), | |
81cec3c7 | 411 | CLK("da8xx_lcdc.0", "fck", &lcdc_clk), |
e33ef5e3 C |
412 | CLK("davinci-mcasp.0", NULL, &mcasp0_clk), |
413 | CLK("davinci-mcasp.1", NULL, &mcasp1_clk), | |
414 | CLK("davinci-mcasp.2", NULL, &mcasp2_clk), | |
b9af5ddf | 415 | CLK(NULL, "usb20", &usb20_clk), |
55c79a40 MG |
416 | CLK(NULL, "aemif", &aemif_clk), |
417 | CLK(NULL, "aintc", &aintc_clk), | |
418 | CLK(NULL, "secu_mgr", &secu_mgr_clk), | |
419 | CLK("davinci_emac.1", NULL, &emac_clk), | |
46c18334 | 420 | CLK("davinci_mdio.0", "fck", &emac_clk), |
55c79a40 MG |
421 | CLK(NULL, "gpio", &gpio_clk), |
422 | CLK("i2c_davinci.2", NULL, &i2c1_clk), | |
423 | CLK(NULL, "usb11", &usb11_clk), | |
424 | CLK(NULL, "emif3", &emif3_clk), | |
425 | CLK(NULL, "arm", &arm_clk), | |
426 | CLK(NULL, "rmii", &rmii_clk), | |
427 | CLK(NULL, NULL, NULL), | |
428 | }; | |
429 | ||
55c79a40 MG |
430 | /* |
431 | * Device specific mux setup | |
432 | * | |
433 | * soc description mux mode mode mux dbg | |
434 | * reg offset mask mode | |
435 | */ | |
436 | static const struct mux_config da830_pins[] = { | |
437 | #ifdef CONFIG_DAVINCI_MUX | |
438 | MUX_CFG(DA830, GPIO7_14, 0, 0, 0xf, 1, false) | |
439 | MUX_CFG(DA830, RTCK, 0, 0, 0xf, 8, false) | |
440 | MUX_CFG(DA830, GPIO7_15, 0, 4, 0xf, 1, false) | |
441 | MUX_CFG(DA830, EMU_0, 0, 4, 0xf, 8, false) | |
442 | MUX_CFG(DA830, EMB_SDCKE, 0, 8, 0xf, 1, false) | |
443 | MUX_CFG(DA830, EMB_CLK_GLUE, 0, 12, 0xf, 1, false) | |
444 | MUX_CFG(DA830, EMB_CLK, 0, 12, 0xf, 2, false) | |
445 | MUX_CFG(DA830, NEMB_CS_0, 0, 16, 0xf, 1, false) | |
446 | MUX_CFG(DA830, NEMB_CAS, 0, 20, 0xf, 1, false) | |
447 | MUX_CFG(DA830, NEMB_RAS, 0, 24, 0xf, 1, false) | |
448 | MUX_CFG(DA830, NEMB_WE, 0, 28, 0xf, 1, false) | |
449 | MUX_CFG(DA830, EMB_BA_1, 1, 0, 0xf, 1, false) | |
450 | MUX_CFG(DA830, EMB_BA_0, 1, 4, 0xf, 1, false) | |
451 | MUX_CFG(DA830, EMB_A_0, 1, 8, 0xf, 1, false) | |
452 | MUX_CFG(DA830, EMB_A_1, 1, 12, 0xf, 1, false) | |
453 | MUX_CFG(DA830, EMB_A_2, 1, 16, 0xf, 1, false) | |
454 | MUX_CFG(DA830, EMB_A_3, 1, 20, 0xf, 1, false) | |
455 | MUX_CFG(DA830, EMB_A_4, 1, 24, 0xf, 1, false) | |
456 | MUX_CFG(DA830, EMB_A_5, 1, 28, 0xf, 1, false) | |
457 | MUX_CFG(DA830, GPIO7_0, 1, 0, 0xf, 8, false) | |
458 | MUX_CFG(DA830, GPIO7_1, 1, 4, 0xf, 8, false) | |
459 | MUX_CFG(DA830, GPIO7_2, 1, 8, 0xf, 8, false) | |
460 | MUX_CFG(DA830, GPIO7_3, 1, 12, 0xf, 8, false) | |
461 | MUX_CFG(DA830, GPIO7_4, 1, 16, 0xf, 8, false) | |
462 | MUX_CFG(DA830, GPIO7_5, 1, 20, 0xf, 8, false) | |
463 | MUX_CFG(DA830, GPIO7_6, 1, 24, 0xf, 8, false) | |
464 | MUX_CFG(DA830, GPIO7_7, 1, 28, 0xf, 8, false) | |
465 | MUX_CFG(DA830, EMB_A_6, 2, 0, 0xf, 1, false) | |
466 | MUX_CFG(DA830, EMB_A_7, 2, 4, 0xf, 1, false) | |
467 | MUX_CFG(DA830, EMB_A_8, 2, 8, 0xf, 1, false) | |
468 | MUX_CFG(DA830, EMB_A_9, 2, 12, 0xf, 1, false) | |
469 | MUX_CFG(DA830, EMB_A_10, 2, 16, 0xf, 1, false) | |
470 | MUX_CFG(DA830, EMB_A_11, 2, 20, 0xf, 1, false) | |
471 | MUX_CFG(DA830, EMB_A_12, 2, 24, 0xf, 1, false) | |
472 | MUX_CFG(DA830, EMB_D_31, 2, 28, 0xf, 1, false) | |
473 | MUX_CFG(DA830, GPIO7_8, 2, 0, 0xf, 8, false) | |
474 | MUX_CFG(DA830, GPIO7_9, 2, 4, 0xf, 8, false) | |
475 | MUX_CFG(DA830, GPIO7_10, 2, 8, 0xf, 8, false) | |
476 | MUX_CFG(DA830, GPIO7_11, 2, 12, 0xf, 8, false) | |
477 | MUX_CFG(DA830, GPIO7_12, 2, 16, 0xf, 8, false) | |
478 | MUX_CFG(DA830, GPIO7_13, 2, 20, 0xf, 8, false) | |
479 | MUX_CFG(DA830, GPIO3_13, 2, 24, 0xf, 8, false) | |
480 | MUX_CFG(DA830, EMB_D_30, 3, 0, 0xf, 1, false) | |
481 | MUX_CFG(DA830, EMB_D_29, 3, 4, 0xf, 1, false) | |
482 | MUX_CFG(DA830, EMB_D_28, 3, 8, 0xf, 1, false) | |
483 | MUX_CFG(DA830, EMB_D_27, 3, 12, 0xf, 1, false) | |
484 | MUX_CFG(DA830, EMB_D_26, 3, 16, 0xf, 1, false) | |
485 | MUX_CFG(DA830, EMB_D_25, 3, 20, 0xf, 1, false) | |
486 | MUX_CFG(DA830, EMB_D_24, 3, 24, 0xf, 1, false) | |
487 | MUX_CFG(DA830, EMB_D_23, 3, 28, 0xf, 1, false) | |
488 | MUX_CFG(DA830, EMB_D_22, 4, 0, 0xf, 1, false) | |
489 | MUX_CFG(DA830, EMB_D_21, 4, 4, 0xf, 1, false) | |
490 | MUX_CFG(DA830, EMB_D_20, 4, 8, 0xf, 1, false) | |
491 | MUX_CFG(DA830, EMB_D_19, 4, 12, 0xf, 1, false) | |
492 | MUX_CFG(DA830, EMB_D_18, 4, 16, 0xf, 1, false) | |
493 | MUX_CFG(DA830, EMB_D_17, 4, 20, 0xf, 1, false) | |
494 | MUX_CFG(DA830, EMB_D_16, 4, 24, 0xf, 1, false) | |
495 | MUX_CFG(DA830, NEMB_WE_DQM_3, 4, 28, 0xf, 1, false) | |
496 | MUX_CFG(DA830, NEMB_WE_DQM_2, 5, 0, 0xf, 1, false) | |
497 | MUX_CFG(DA830, EMB_D_0, 5, 4, 0xf, 1, false) | |
498 | MUX_CFG(DA830, EMB_D_1, 5, 8, 0xf, 1, false) | |
499 | MUX_CFG(DA830, EMB_D_2, 5, 12, 0xf, 1, false) | |
500 | MUX_CFG(DA830, EMB_D_3, 5, 16, 0xf, 1, false) | |
501 | MUX_CFG(DA830, EMB_D_4, 5, 20, 0xf, 1, false) | |
502 | MUX_CFG(DA830, EMB_D_5, 5, 24, 0xf, 1, false) | |
503 | MUX_CFG(DA830, EMB_D_6, 5, 28, 0xf, 1, false) | |
504 | MUX_CFG(DA830, GPIO6_0, 5, 4, 0xf, 8, false) | |
505 | MUX_CFG(DA830, GPIO6_1, 5, 8, 0xf, 8, false) | |
506 | MUX_CFG(DA830, GPIO6_2, 5, 12, 0xf, 8, false) | |
507 | MUX_CFG(DA830, GPIO6_3, 5, 16, 0xf, 8, false) | |
508 | MUX_CFG(DA830, GPIO6_4, 5, 20, 0xf, 8, false) | |
509 | MUX_CFG(DA830, GPIO6_5, 5, 24, 0xf, 8, false) | |
510 | MUX_CFG(DA830, GPIO6_6, 5, 28, 0xf, 8, false) | |
511 | MUX_CFG(DA830, EMB_D_7, 6, 0, 0xf, 1, false) | |
512 | MUX_CFG(DA830, EMB_D_8, 6, 4, 0xf, 1, false) | |
513 | MUX_CFG(DA830, EMB_D_9, 6, 8, 0xf, 1, false) | |
514 | MUX_CFG(DA830, EMB_D_10, 6, 12, 0xf, 1, false) | |
515 | MUX_CFG(DA830, EMB_D_11, 6, 16, 0xf, 1, false) | |
516 | MUX_CFG(DA830, EMB_D_12, 6, 20, 0xf, 1, false) | |
517 | MUX_CFG(DA830, EMB_D_13, 6, 24, 0xf, 1, false) | |
518 | MUX_CFG(DA830, EMB_D_14, 6, 28, 0xf, 1, false) | |
519 | MUX_CFG(DA830, GPIO6_7, 6, 0, 0xf, 8, false) | |
520 | MUX_CFG(DA830, GPIO6_8, 6, 4, 0xf, 8, false) | |
521 | MUX_CFG(DA830, GPIO6_9, 6, 8, 0xf, 8, false) | |
522 | MUX_CFG(DA830, GPIO6_10, 6, 12, 0xf, 8, false) | |
523 | MUX_CFG(DA830, GPIO6_11, 6, 16, 0xf, 8, false) | |
524 | MUX_CFG(DA830, GPIO6_12, 6, 20, 0xf, 8, false) | |
525 | MUX_CFG(DA830, GPIO6_13, 6, 24, 0xf, 8, false) | |
526 | MUX_CFG(DA830, GPIO6_14, 6, 28, 0xf, 8, false) | |
527 | MUX_CFG(DA830, EMB_D_15, 7, 0, 0xf, 1, false) | |
528 | MUX_CFG(DA830, NEMB_WE_DQM_1, 7, 4, 0xf, 1, false) | |
529 | MUX_CFG(DA830, NEMB_WE_DQM_0, 7, 8, 0xf, 1, false) | |
530 | MUX_CFG(DA830, SPI0_SOMI_0, 7, 12, 0xf, 1, false) | |
531 | MUX_CFG(DA830, SPI0_SIMO_0, 7, 16, 0xf, 1, false) | |
532 | MUX_CFG(DA830, SPI0_CLK, 7, 20, 0xf, 1, false) | |
533 | MUX_CFG(DA830, NSPI0_ENA, 7, 24, 0xf, 1, false) | |
534 | MUX_CFG(DA830, NSPI0_SCS_0, 7, 28, 0xf, 1, false) | |
535 | MUX_CFG(DA830, EQEP0I, 7, 12, 0xf, 2, false) | |
536 | MUX_CFG(DA830, EQEP0S, 7, 16, 0xf, 2, false) | |
537 | MUX_CFG(DA830, EQEP1I, 7, 20, 0xf, 2, false) | |
538 | MUX_CFG(DA830, NUART0_CTS, 7, 24, 0xf, 2, false) | |
539 | MUX_CFG(DA830, NUART0_RTS, 7, 28, 0xf, 2, false) | |
540 | MUX_CFG(DA830, EQEP0A, 7, 24, 0xf, 4, false) | |
541 | MUX_CFG(DA830, EQEP0B, 7, 28, 0xf, 4, false) | |
542 | MUX_CFG(DA830, GPIO6_15, 7, 0, 0xf, 8, false) | |
543 | MUX_CFG(DA830, GPIO5_14, 7, 4, 0xf, 8, false) | |
544 | MUX_CFG(DA830, GPIO5_15, 7, 8, 0xf, 8, false) | |
545 | MUX_CFG(DA830, GPIO5_0, 7, 12, 0xf, 8, false) | |
546 | MUX_CFG(DA830, GPIO5_1, 7, 16, 0xf, 8, false) | |
547 | MUX_CFG(DA830, GPIO5_2, 7, 20, 0xf, 8, false) | |
548 | MUX_CFG(DA830, GPIO5_3, 7, 24, 0xf, 8, false) | |
549 | MUX_CFG(DA830, GPIO5_4, 7, 28, 0xf, 8, false) | |
550 | MUX_CFG(DA830, SPI1_SOMI_0, 8, 0, 0xf, 1, false) | |
551 | MUX_CFG(DA830, SPI1_SIMO_0, 8, 4, 0xf, 1, false) | |
552 | MUX_CFG(DA830, SPI1_CLK, 8, 8, 0xf, 1, false) | |
553 | MUX_CFG(DA830, UART0_RXD, 8, 12, 0xf, 1, false) | |
554 | MUX_CFG(DA830, UART0_TXD, 8, 16, 0xf, 1, false) | |
555 | MUX_CFG(DA830, AXR1_10, 8, 20, 0xf, 1, false) | |
556 | MUX_CFG(DA830, AXR1_11, 8, 24, 0xf, 1, false) | |
557 | MUX_CFG(DA830, NSPI1_ENA, 8, 28, 0xf, 1, false) | |
558 | MUX_CFG(DA830, I2C1_SCL, 8, 0, 0xf, 2, false) | |
559 | MUX_CFG(DA830, I2C1_SDA, 8, 4, 0xf, 2, false) | |
560 | MUX_CFG(DA830, EQEP1S, 8, 8, 0xf, 2, false) | |
561 | MUX_CFG(DA830, I2C0_SDA, 8, 12, 0xf, 2, false) | |
562 | MUX_CFG(DA830, I2C0_SCL, 8, 16, 0xf, 2, false) | |
563 | MUX_CFG(DA830, UART2_RXD, 8, 28, 0xf, 2, false) | |
564 | MUX_CFG(DA830, TM64P0_IN12, 8, 12, 0xf, 4, false) | |
565 | MUX_CFG(DA830, TM64P0_OUT12, 8, 16, 0xf, 4, false) | |
566 | MUX_CFG(DA830, GPIO5_5, 8, 0, 0xf, 8, false) | |
567 | MUX_CFG(DA830, GPIO5_6, 8, 4, 0xf, 8, false) | |
568 | MUX_CFG(DA830, GPIO5_7, 8, 8, 0xf, 8, false) | |
569 | MUX_CFG(DA830, GPIO5_8, 8, 12, 0xf, 8, false) | |
570 | MUX_CFG(DA830, GPIO5_9, 8, 16, 0xf, 8, false) | |
571 | MUX_CFG(DA830, GPIO5_10, 8, 20, 0xf, 8, false) | |
572 | MUX_CFG(DA830, GPIO5_11, 8, 24, 0xf, 8, false) | |
573 | MUX_CFG(DA830, GPIO5_12, 8, 28, 0xf, 8, false) | |
574 | MUX_CFG(DA830, NSPI1_SCS_0, 9, 0, 0xf, 1, false) | |
575 | MUX_CFG(DA830, USB0_DRVVBUS, 9, 4, 0xf, 1, false) | |
576 | MUX_CFG(DA830, AHCLKX0, 9, 8, 0xf, 1, false) | |
577 | MUX_CFG(DA830, ACLKX0, 9, 12, 0xf, 1, false) | |
578 | MUX_CFG(DA830, AFSX0, 9, 16, 0xf, 1, false) | |
579 | MUX_CFG(DA830, AHCLKR0, 9, 20, 0xf, 1, false) | |
580 | MUX_CFG(DA830, ACLKR0, 9, 24, 0xf, 1, false) | |
581 | MUX_CFG(DA830, AFSR0, 9, 28, 0xf, 1, false) | |
582 | MUX_CFG(DA830, UART2_TXD, 9, 0, 0xf, 2, false) | |
583 | MUX_CFG(DA830, AHCLKX2, 9, 8, 0xf, 2, false) | |
584 | MUX_CFG(DA830, ECAP0_APWM0, 9, 12, 0xf, 2, false) | |
585 | MUX_CFG(DA830, RMII_MHZ_50_CLK, 9, 20, 0xf, 2, false) | |
586 | MUX_CFG(DA830, ECAP1_APWM1, 9, 24, 0xf, 2, false) | |
587 | MUX_CFG(DA830, USB_REFCLKIN, 9, 8, 0xf, 4, false) | |
588 | MUX_CFG(DA830, GPIO5_13, 9, 0, 0xf, 8, false) | |
589 | MUX_CFG(DA830, GPIO4_15, 9, 4, 0xf, 8, false) | |
590 | MUX_CFG(DA830, GPIO2_11, 9, 8, 0xf, 8, false) | |
591 | MUX_CFG(DA830, GPIO2_12, 9, 12, 0xf, 8, false) | |
592 | MUX_CFG(DA830, GPIO2_13, 9, 16, 0xf, 8, false) | |
593 | MUX_CFG(DA830, GPIO2_14, 9, 20, 0xf, 8, false) | |
594 | MUX_CFG(DA830, GPIO2_15, 9, 24, 0xf, 8, false) | |
595 | MUX_CFG(DA830, GPIO3_12, 9, 28, 0xf, 8, false) | |
596 | MUX_CFG(DA830, AMUTE0, 10, 0, 0xf, 1, false) | |
597 | MUX_CFG(DA830, AXR0_0, 10, 4, 0xf, 1, false) | |
598 | MUX_CFG(DA830, AXR0_1, 10, 8, 0xf, 1, false) | |
599 | MUX_CFG(DA830, AXR0_2, 10, 12, 0xf, 1, false) | |
600 | MUX_CFG(DA830, AXR0_3, 10, 16, 0xf, 1, false) | |
601 | MUX_CFG(DA830, AXR0_4, 10, 20, 0xf, 1, false) | |
602 | MUX_CFG(DA830, AXR0_5, 10, 24, 0xf, 1, false) | |
603 | MUX_CFG(DA830, AXR0_6, 10, 28, 0xf, 1, false) | |
604 | MUX_CFG(DA830, RMII_TXD_0, 10, 4, 0xf, 2, false) | |
605 | MUX_CFG(DA830, RMII_TXD_1, 10, 8, 0xf, 2, false) | |
606 | MUX_CFG(DA830, RMII_TXEN, 10, 12, 0xf, 2, false) | |
607 | MUX_CFG(DA830, RMII_CRS_DV, 10, 16, 0xf, 2, false) | |
608 | MUX_CFG(DA830, RMII_RXD_0, 10, 20, 0xf, 2, false) | |
609 | MUX_CFG(DA830, RMII_RXD_1, 10, 24, 0xf, 2, false) | |
610 | MUX_CFG(DA830, RMII_RXER, 10, 28, 0xf, 2, false) | |
611 | MUX_CFG(DA830, AFSR2, 10, 4, 0xf, 4, false) | |
612 | MUX_CFG(DA830, ACLKX2, 10, 8, 0xf, 4, false) | |
613 | MUX_CFG(DA830, AXR2_3, 10, 12, 0xf, 4, false) | |
614 | MUX_CFG(DA830, AXR2_2, 10, 16, 0xf, 4, false) | |
615 | MUX_CFG(DA830, AXR2_1, 10, 20, 0xf, 4, false) | |
616 | MUX_CFG(DA830, AFSX2, 10, 24, 0xf, 4, false) | |
617 | MUX_CFG(DA830, ACLKR2, 10, 28, 0xf, 4, false) | |
618 | MUX_CFG(DA830, NRESETOUT, 10, 0, 0xf, 8, false) | |
619 | MUX_CFG(DA830, GPIO3_0, 10, 4, 0xf, 8, false) | |
620 | MUX_CFG(DA830, GPIO3_1, 10, 8, 0xf, 8, false) | |
621 | MUX_CFG(DA830, GPIO3_2, 10, 12, 0xf, 8, false) | |
622 | MUX_CFG(DA830, GPIO3_3, 10, 16, 0xf, 8, false) | |
623 | MUX_CFG(DA830, GPIO3_4, 10, 20, 0xf, 8, false) | |
624 | MUX_CFG(DA830, GPIO3_5, 10, 24, 0xf, 8, false) | |
625 | MUX_CFG(DA830, GPIO3_6, 10, 28, 0xf, 8, false) | |
626 | MUX_CFG(DA830, AXR0_7, 11, 0, 0xf, 1, false) | |
627 | MUX_CFG(DA830, AXR0_8, 11, 4, 0xf, 1, false) | |
628 | MUX_CFG(DA830, UART1_RXD, 11, 8, 0xf, 1, false) | |
629 | MUX_CFG(DA830, UART1_TXD, 11, 12, 0xf, 1, false) | |
630 | MUX_CFG(DA830, AXR0_11, 11, 16, 0xf, 1, false) | |
631 | MUX_CFG(DA830, AHCLKX1, 11, 20, 0xf, 1, false) | |
632 | MUX_CFG(DA830, ACLKX1, 11, 24, 0xf, 1, false) | |
633 | MUX_CFG(DA830, AFSX1, 11, 28, 0xf, 1, false) | |
634 | MUX_CFG(DA830, MDIO_CLK, 11, 0, 0xf, 2, false) | |
635 | MUX_CFG(DA830, MDIO_D, 11, 4, 0xf, 2, false) | |
636 | MUX_CFG(DA830, AXR0_9, 11, 8, 0xf, 2, false) | |
637 | MUX_CFG(DA830, AXR0_10, 11, 12, 0xf, 2, false) | |
638 | MUX_CFG(DA830, EPWM0B, 11, 20, 0xf, 2, false) | |
639 | MUX_CFG(DA830, EPWM0A, 11, 24, 0xf, 2, false) | |
640 | MUX_CFG(DA830, EPWMSYNCI, 11, 28, 0xf, 2, false) | |
641 | MUX_CFG(DA830, AXR2_0, 11, 16, 0xf, 4, false) | |
642 | MUX_CFG(DA830, EPWMSYNC0, 11, 28, 0xf, 4, false) | |
643 | MUX_CFG(DA830, GPIO3_7, 11, 0, 0xf, 8, false) | |
644 | MUX_CFG(DA830, GPIO3_8, 11, 4, 0xf, 8, false) | |
645 | MUX_CFG(DA830, GPIO3_9, 11, 8, 0xf, 8, false) | |
646 | MUX_CFG(DA830, GPIO3_10, 11, 12, 0xf, 8, false) | |
647 | MUX_CFG(DA830, GPIO3_11, 11, 16, 0xf, 8, false) | |
648 | MUX_CFG(DA830, GPIO3_14, 11, 20, 0xf, 8, false) | |
649 | MUX_CFG(DA830, GPIO3_15, 11, 24, 0xf, 8, false) | |
650 | MUX_CFG(DA830, GPIO4_10, 11, 28, 0xf, 8, false) | |
651 | MUX_CFG(DA830, AHCLKR1, 12, 0, 0xf, 1, false) | |
652 | MUX_CFG(DA830, ACLKR1, 12, 4, 0xf, 1, false) | |
653 | MUX_CFG(DA830, AFSR1, 12, 8, 0xf, 1, false) | |
654 | MUX_CFG(DA830, AMUTE1, 12, 12, 0xf, 1, false) | |
655 | MUX_CFG(DA830, AXR1_0, 12, 16, 0xf, 1, false) | |
656 | MUX_CFG(DA830, AXR1_1, 12, 20, 0xf, 1, false) | |
657 | MUX_CFG(DA830, AXR1_2, 12, 24, 0xf, 1, false) | |
658 | MUX_CFG(DA830, AXR1_3, 12, 28, 0xf, 1, false) | |
659 | MUX_CFG(DA830, ECAP2_APWM2, 12, 4, 0xf, 2, false) | |
660 | MUX_CFG(DA830, EHRPWMGLUETZ, 12, 12, 0xf, 2, false) | |
661 | MUX_CFG(DA830, EQEP1A, 12, 28, 0xf, 2, false) | |
662 | MUX_CFG(DA830, GPIO4_11, 12, 0, 0xf, 8, false) | |
663 | MUX_CFG(DA830, GPIO4_12, 12, 4, 0xf, 8, false) | |
664 | MUX_CFG(DA830, GPIO4_13, 12, 8, 0xf, 8, false) | |
665 | MUX_CFG(DA830, GPIO4_14, 12, 12, 0xf, 8, false) | |
666 | MUX_CFG(DA830, GPIO4_0, 12, 16, 0xf, 8, false) | |
667 | MUX_CFG(DA830, GPIO4_1, 12, 20, 0xf, 8, false) | |
668 | MUX_CFG(DA830, GPIO4_2, 12, 24, 0xf, 8, false) | |
669 | MUX_CFG(DA830, GPIO4_3, 12, 28, 0xf, 8, false) | |
670 | MUX_CFG(DA830, AXR1_4, 13, 0, 0xf, 1, false) | |
671 | MUX_CFG(DA830, AXR1_5, 13, 4, 0xf, 1, false) | |
672 | MUX_CFG(DA830, AXR1_6, 13, 8, 0xf, 1, false) | |
673 | MUX_CFG(DA830, AXR1_7, 13, 12, 0xf, 1, false) | |
674 | MUX_CFG(DA830, AXR1_8, 13, 16, 0xf, 1, false) | |
675 | MUX_CFG(DA830, AXR1_9, 13, 20, 0xf, 1, false) | |
676 | MUX_CFG(DA830, EMA_D_0, 13, 24, 0xf, 1, false) | |
677 | MUX_CFG(DA830, EMA_D_1, 13, 28, 0xf, 1, false) | |
678 | MUX_CFG(DA830, EQEP1B, 13, 0, 0xf, 2, false) | |
679 | MUX_CFG(DA830, EPWM2B, 13, 4, 0xf, 2, false) | |
680 | MUX_CFG(DA830, EPWM2A, 13, 8, 0xf, 2, false) | |
681 | MUX_CFG(DA830, EPWM1B, 13, 12, 0xf, 2, false) | |
682 | MUX_CFG(DA830, EPWM1A, 13, 16, 0xf, 2, false) | |
683 | MUX_CFG(DA830, MMCSD_DAT_0, 13, 24, 0xf, 2, false) | |
684 | MUX_CFG(DA830, MMCSD_DAT_1, 13, 28, 0xf, 2, false) | |
685 | MUX_CFG(DA830, UHPI_HD_0, 13, 24, 0xf, 4, false) | |
686 | MUX_CFG(DA830, UHPI_HD_1, 13, 28, 0xf, 4, false) | |
687 | MUX_CFG(DA830, GPIO4_4, 13, 0, 0xf, 8, false) | |
688 | MUX_CFG(DA830, GPIO4_5, 13, 4, 0xf, 8, false) | |
689 | MUX_CFG(DA830, GPIO4_6, 13, 8, 0xf, 8, false) | |
690 | MUX_CFG(DA830, GPIO4_7, 13, 12, 0xf, 8, false) | |
691 | MUX_CFG(DA830, GPIO4_8, 13, 16, 0xf, 8, false) | |
692 | MUX_CFG(DA830, GPIO4_9, 13, 20, 0xf, 8, false) | |
693 | MUX_CFG(DA830, GPIO0_0, 13, 24, 0xf, 8, false) | |
694 | MUX_CFG(DA830, GPIO0_1, 13, 28, 0xf, 8, false) | |
695 | MUX_CFG(DA830, EMA_D_2, 14, 0, 0xf, 1, false) | |
696 | MUX_CFG(DA830, EMA_D_3, 14, 4, 0xf, 1, false) | |
697 | MUX_CFG(DA830, EMA_D_4, 14, 8, 0xf, 1, false) | |
698 | MUX_CFG(DA830, EMA_D_5, 14, 12, 0xf, 1, false) | |
699 | MUX_CFG(DA830, EMA_D_6, 14, 16, 0xf, 1, false) | |
700 | MUX_CFG(DA830, EMA_D_7, 14, 20, 0xf, 1, false) | |
701 | MUX_CFG(DA830, EMA_D_8, 14, 24, 0xf, 1, false) | |
702 | MUX_CFG(DA830, EMA_D_9, 14, 28, 0xf, 1, false) | |
703 | MUX_CFG(DA830, MMCSD_DAT_2, 14, 0, 0xf, 2, false) | |
704 | MUX_CFG(DA830, MMCSD_DAT_3, 14, 4, 0xf, 2, false) | |
705 | MUX_CFG(DA830, MMCSD_DAT_4, 14, 8, 0xf, 2, false) | |
706 | MUX_CFG(DA830, MMCSD_DAT_5, 14, 12, 0xf, 2, false) | |
707 | MUX_CFG(DA830, MMCSD_DAT_6, 14, 16, 0xf, 2, false) | |
708 | MUX_CFG(DA830, MMCSD_DAT_7, 14, 20, 0xf, 2, false) | |
709 | MUX_CFG(DA830, UHPI_HD_8, 14, 24, 0xf, 2, false) | |
710 | MUX_CFG(DA830, UHPI_HD_9, 14, 28, 0xf, 2, false) | |
711 | MUX_CFG(DA830, UHPI_HD_2, 14, 0, 0xf, 4, false) | |
712 | MUX_CFG(DA830, UHPI_HD_3, 14, 4, 0xf, 4, false) | |
713 | MUX_CFG(DA830, UHPI_HD_4, 14, 8, 0xf, 4, false) | |
714 | MUX_CFG(DA830, UHPI_HD_5, 14, 12, 0xf, 4, false) | |
715 | MUX_CFG(DA830, UHPI_HD_6, 14, 16, 0xf, 4, false) | |
716 | MUX_CFG(DA830, UHPI_HD_7, 14, 20, 0xf, 4, false) | |
717 | MUX_CFG(DA830, LCD_D_8, 14, 24, 0xf, 4, false) | |
718 | MUX_CFG(DA830, LCD_D_9, 14, 28, 0xf, 4, false) | |
719 | MUX_CFG(DA830, GPIO0_2, 14, 0, 0xf, 8, false) | |
720 | MUX_CFG(DA830, GPIO0_3, 14, 4, 0xf, 8, false) | |
721 | MUX_CFG(DA830, GPIO0_4, 14, 8, 0xf, 8, false) | |
722 | MUX_CFG(DA830, GPIO0_5, 14, 12, 0xf, 8, false) | |
723 | MUX_CFG(DA830, GPIO0_6, 14, 16, 0xf, 8, false) | |
724 | MUX_CFG(DA830, GPIO0_7, 14, 20, 0xf, 8, false) | |
725 | MUX_CFG(DA830, GPIO0_8, 14, 24, 0xf, 8, false) | |
726 | MUX_CFG(DA830, GPIO0_9, 14, 28, 0xf, 8, false) | |
727 | MUX_CFG(DA830, EMA_D_10, 15, 0, 0xf, 1, false) | |
728 | MUX_CFG(DA830, EMA_D_11, 15, 4, 0xf, 1, false) | |
729 | MUX_CFG(DA830, EMA_D_12, 15, 8, 0xf, 1, false) | |
730 | MUX_CFG(DA830, EMA_D_13, 15, 12, 0xf, 1, false) | |
731 | MUX_CFG(DA830, EMA_D_14, 15, 16, 0xf, 1, false) | |
732 | MUX_CFG(DA830, EMA_D_15, 15, 20, 0xf, 1, false) | |
733 | MUX_CFG(DA830, EMA_A_0, 15, 24, 0xf, 1, false) | |
734 | MUX_CFG(DA830, EMA_A_1, 15, 28, 0xf, 1, false) | |
735 | MUX_CFG(DA830, UHPI_HD_10, 15, 0, 0xf, 2, false) | |
736 | MUX_CFG(DA830, UHPI_HD_11, 15, 4, 0xf, 2, false) | |
737 | MUX_CFG(DA830, UHPI_HD_12, 15, 8, 0xf, 2, false) | |
738 | MUX_CFG(DA830, UHPI_HD_13, 15, 12, 0xf, 2, false) | |
739 | MUX_CFG(DA830, UHPI_HD_14, 15, 16, 0xf, 2, false) | |
740 | MUX_CFG(DA830, UHPI_HD_15, 15, 20, 0xf, 2, false) | |
741 | MUX_CFG(DA830, LCD_D_7, 15, 24, 0xf, 2, false) | |
742 | MUX_CFG(DA830, MMCSD_CLK, 15, 28, 0xf, 2, false) | |
743 | MUX_CFG(DA830, LCD_D_10, 15, 0, 0xf, 4, false) | |
744 | MUX_CFG(DA830, LCD_D_11, 15, 4, 0xf, 4, false) | |
745 | MUX_CFG(DA830, LCD_D_12, 15, 8, 0xf, 4, false) | |
746 | MUX_CFG(DA830, LCD_D_13, 15, 12, 0xf, 4, false) | |
747 | MUX_CFG(DA830, LCD_D_14, 15, 16, 0xf, 4, false) | |
748 | MUX_CFG(DA830, LCD_D_15, 15, 20, 0xf, 4, false) | |
749 | MUX_CFG(DA830, UHPI_HCNTL0, 15, 28, 0xf, 4, false) | |
750 | MUX_CFG(DA830, GPIO0_10, 15, 0, 0xf, 8, false) | |
751 | MUX_CFG(DA830, GPIO0_11, 15, 4, 0xf, 8, false) | |
752 | MUX_CFG(DA830, GPIO0_12, 15, 8, 0xf, 8, false) | |
753 | MUX_CFG(DA830, GPIO0_13, 15, 12, 0xf, 8, false) | |
754 | MUX_CFG(DA830, GPIO0_14, 15, 16, 0xf, 8, false) | |
755 | MUX_CFG(DA830, GPIO0_15, 15, 20, 0xf, 8, false) | |
756 | MUX_CFG(DA830, GPIO1_0, 15, 24, 0xf, 8, false) | |
757 | MUX_CFG(DA830, GPIO1_1, 15, 28, 0xf, 8, false) | |
758 | MUX_CFG(DA830, EMA_A_2, 16, 0, 0xf, 1, false) | |
759 | MUX_CFG(DA830, EMA_A_3, 16, 4, 0xf, 1, false) | |
760 | MUX_CFG(DA830, EMA_A_4, 16, 8, 0xf, 1, false) | |
761 | MUX_CFG(DA830, EMA_A_5, 16, 12, 0xf, 1, false) | |
762 | MUX_CFG(DA830, EMA_A_6, 16, 16, 0xf, 1, false) | |
763 | MUX_CFG(DA830, EMA_A_7, 16, 20, 0xf, 1, false) | |
764 | MUX_CFG(DA830, EMA_A_8, 16, 24, 0xf, 1, false) | |
765 | MUX_CFG(DA830, EMA_A_9, 16, 28, 0xf, 1, false) | |
766 | MUX_CFG(DA830, MMCSD_CMD, 16, 0, 0xf, 2, false) | |
767 | MUX_CFG(DA830, LCD_D_6, 16, 4, 0xf, 2, false) | |
768 | MUX_CFG(DA830, LCD_D_3, 16, 8, 0xf, 2, false) | |
769 | MUX_CFG(DA830, LCD_D_2, 16, 12, 0xf, 2, false) | |
770 | MUX_CFG(DA830, LCD_D_1, 16, 16, 0xf, 2, false) | |
771 | MUX_CFG(DA830, LCD_D_0, 16, 20, 0xf, 2, false) | |
772 | MUX_CFG(DA830, LCD_PCLK, 16, 24, 0xf, 2, false) | |
773 | MUX_CFG(DA830, LCD_HSYNC, 16, 28, 0xf, 2, false) | |
774 | MUX_CFG(DA830, UHPI_HCNTL1, 16, 0, 0xf, 4, false) | |
775 | MUX_CFG(DA830, GPIO1_2, 16, 0, 0xf, 8, false) | |
776 | MUX_CFG(DA830, GPIO1_3, 16, 4, 0xf, 8, false) | |
777 | MUX_CFG(DA830, GPIO1_4, 16, 8, 0xf, 8, false) | |
778 | MUX_CFG(DA830, GPIO1_5, 16, 12, 0xf, 8, false) | |
779 | MUX_CFG(DA830, GPIO1_6, 16, 16, 0xf, 8, false) | |
780 | MUX_CFG(DA830, GPIO1_7, 16, 20, 0xf, 8, false) | |
781 | MUX_CFG(DA830, GPIO1_8, 16, 24, 0xf, 8, false) | |
782 | MUX_CFG(DA830, GPIO1_9, 16, 28, 0xf, 8, false) | |
783 | MUX_CFG(DA830, EMA_A_10, 17, 0, 0xf, 1, false) | |
784 | MUX_CFG(DA830, EMA_A_11, 17, 4, 0xf, 1, false) | |
785 | MUX_CFG(DA830, EMA_A_12, 17, 8, 0xf, 1, false) | |
786 | MUX_CFG(DA830, EMA_BA_1, 17, 12, 0xf, 1, false) | |
787 | MUX_CFG(DA830, EMA_BA_0, 17, 16, 0xf, 1, false) | |
788 | MUX_CFG(DA830, EMA_CLK, 17, 20, 0xf, 1, false) | |
789 | MUX_CFG(DA830, EMA_SDCKE, 17, 24, 0xf, 1, false) | |
790 | MUX_CFG(DA830, NEMA_CAS, 17, 28, 0xf, 1, false) | |
791 | MUX_CFG(DA830, LCD_VSYNC, 17, 0, 0xf, 2, false) | |
792 | MUX_CFG(DA830, NLCD_AC_ENB_CS, 17, 4, 0xf, 2, false) | |
793 | MUX_CFG(DA830, LCD_MCLK, 17, 8, 0xf, 2, false) | |
794 | MUX_CFG(DA830, LCD_D_5, 17, 12, 0xf, 2, false) | |
795 | MUX_CFG(DA830, LCD_D_4, 17, 16, 0xf, 2, false) | |
796 | MUX_CFG(DA830, OBSCLK, 17, 20, 0xf, 2, false) | |
797 | MUX_CFG(DA830, NEMA_CS_4, 17, 28, 0xf, 2, false) | |
798 | MUX_CFG(DA830, UHPI_HHWIL, 17, 12, 0xf, 4, false) | |
799 | MUX_CFG(DA830, AHCLKR2, 17, 20, 0xf, 4, false) | |
800 | MUX_CFG(DA830, GPIO1_10, 17, 0, 0xf, 8, false) | |
801 | MUX_CFG(DA830, GPIO1_11, 17, 4, 0xf, 8, false) | |
802 | MUX_CFG(DA830, GPIO1_12, 17, 8, 0xf, 8, false) | |
803 | MUX_CFG(DA830, GPIO1_13, 17, 12, 0xf, 8, false) | |
804 | MUX_CFG(DA830, GPIO1_14, 17, 16, 0xf, 8, false) | |
805 | MUX_CFG(DA830, GPIO1_15, 17, 20, 0xf, 8, false) | |
806 | MUX_CFG(DA830, GPIO2_0, 17, 24, 0xf, 8, false) | |
807 | MUX_CFG(DA830, GPIO2_1, 17, 28, 0xf, 8, false) | |
808 | MUX_CFG(DA830, NEMA_RAS, 18, 0, 0xf, 1, false) | |
809 | MUX_CFG(DA830, NEMA_WE, 18, 4, 0xf, 1, false) | |
810 | MUX_CFG(DA830, NEMA_CS_0, 18, 8, 0xf, 1, false) | |
811 | MUX_CFG(DA830, NEMA_CS_2, 18, 12, 0xf, 1, false) | |
812 | MUX_CFG(DA830, NEMA_CS_3, 18, 16, 0xf, 1, false) | |
813 | MUX_CFG(DA830, NEMA_OE, 18, 20, 0xf, 1, false) | |
814 | MUX_CFG(DA830, NEMA_WE_DQM_1, 18, 24, 0xf, 1, false) | |
815 | MUX_CFG(DA830, NEMA_WE_DQM_0, 18, 28, 0xf, 1, false) | |
816 | MUX_CFG(DA830, NEMA_CS_5, 18, 0, 0xf, 2, false) | |
817 | MUX_CFG(DA830, UHPI_HRNW, 18, 4, 0xf, 2, false) | |
818 | MUX_CFG(DA830, NUHPI_HAS, 18, 8, 0xf, 2, false) | |
819 | MUX_CFG(DA830, NUHPI_HCS, 18, 12, 0xf, 2, false) | |
820 | MUX_CFG(DA830, NUHPI_HDS1, 18, 20, 0xf, 2, false) | |
821 | MUX_CFG(DA830, NUHPI_HDS2, 18, 24, 0xf, 2, false) | |
822 | MUX_CFG(DA830, NUHPI_HINT, 18, 28, 0xf, 2, false) | |
823 | MUX_CFG(DA830, AXR0_12, 18, 4, 0xf, 4, false) | |
824 | MUX_CFG(DA830, AMUTE2, 18, 16, 0xf, 4, false) | |
825 | MUX_CFG(DA830, AXR0_13, 18, 20, 0xf, 4, false) | |
826 | MUX_CFG(DA830, AXR0_14, 18, 24, 0xf, 4, false) | |
827 | MUX_CFG(DA830, AXR0_15, 18, 28, 0xf, 4, false) | |
828 | MUX_CFG(DA830, GPIO2_2, 18, 0, 0xf, 8, false) | |
829 | MUX_CFG(DA830, GPIO2_3, 18, 4, 0xf, 8, false) | |
830 | MUX_CFG(DA830, GPIO2_4, 18, 8, 0xf, 8, false) | |
831 | MUX_CFG(DA830, GPIO2_5, 18, 12, 0xf, 8, false) | |
832 | MUX_CFG(DA830, GPIO2_6, 18, 16, 0xf, 8, false) | |
833 | MUX_CFG(DA830, GPIO2_7, 18, 20, 0xf, 8, false) | |
834 | MUX_CFG(DA830, GPIO2_8, 18, 24, 0xf, 8, false) | |
835 | MUX_CFG(DA830, GPIO2_9, 18, 28, 0xf, 8, false) | |
836 | MUX_CFG(DA830, EMA_WAIT_0, 19, 0, 0xf, 1, false) | |
837 | MUX_CFG(DA830, NUHPI_HRDY, 19, 0, 0xf, 2, false) | |
838 | MUX_CFG(DA830, GPIO2_10, 19, 0, 0xf, 8, false) | |
839 | #endif | |
840 | }; | |
841 | ||
bcad6dc3 | 842 | const short da830_emif25_pins[] __initconst = { |
55c79a40 MG |
843 | DA830_EMA_D_0, DA830_EMA_D_1, DA830_EMA_D_2, DA830_EMA_D_3, |
844 | DA830_EMA_D_4, DA830_EMA_D_5, DA830_EMA_D_6, DA830_EMA_D_7, | |
845 | DA830_EMA_D_8, DA830_EMA_D_9, DA830_EMA_D_10, DA830_EMA_D_11, | |
846 | DA830_EMA_D_12, DA830_EMA_D_13, DA830_EMA_D_14, DA830_EMA_D_15, | |
847 | DA830_EMA_A_0, DA830_EMA_A_1, DA830_EMA_A_2, DA830_EMA_A_3, | |
848 | DA830_EMA_A_4, DA830_EMA_A_5, DA830_EMA_A_6, DA830_EMA_A_7, | |
849 | DA830_EMA_A_8, DA830_EMA_A_9, DA830_EMA_A_10, DA830_EMA_A_11, | |
850 | DA830_EMA_A_12, DA830_EMA_BA_0, DA830_EMA_BA_1, DA830_EMA_CLK, | |
851 | DA830_EMA_SDCKE, DA830_NEMA_CS_4, DA830_NEMA_CS_5, DA830_NEMA_WE, | |
852 | DA830_NEMA_CS_0, DA830_NEMA_CS_2, DA830_NEMA_CS_3, DA830_NEMA_OE, | |
853 | DA830_NEMA_WE_DQM_1, DA830_NEMA_WE_DQM_0, DA830_EMA_WAIT_0, | |
854 | -1 | |
855 | }; | |
856 | ||
bcad6dc3 | 857 | const short da830_spi0_pins[] __initconst = { |
55c79a40 MG |
858 | DA830_SPI0_SOMI_0, DA830_SPI0_SIMO_0, DA830_SPI0_CLK, DA830_NSPI0_ENA, |
859 | DA830_NSPI0_SCS_0, | |
860 | -1 | |
861 | }; | |
862 | ||
bcad6dc3 | 863 | const short da830_spi1_pins[] __initconst = { |
55c79a40 MG |
864 | DA830_SPI1_SOMI_0, DA830_SPI1_SIMO_0, DA830_SPI1_CLK, DA830_NSPI1_ENA, |
865 | DA830_NSPI1_SCS_0, | |
866 | -1 | |
867 | }; | |
868 | ||
bcad6dc3 | 869 | const short da830_mmc_sd_pins[] __initconst = { |
55c79a40 MG |
870 | DA830_MMCSD_DAT_0, DA830_MMCSD_DAT_1, DA830_MMCSD_DAT_2, |
871 | DA830_MMCSD_DAT_3, DA830_MMCSD_DAT_4, DA830_MMCSD_DAT_5, | |
872 | DA830_MMCSD_DAT_6, DA830_MMCSD_DAT_7, DA830_MMCSD_CLK, | |
873 | DA830_MMCSD_CMD, | |
874 | -1 | |
875 | }; | |
876 | ||
bcad6dc3 | 877 | const short da830_uart0_pins[] __initconst = { |
55c79a40 MG |
878 | DA830_NUART0_CTS, DA830_NUART0_RTS, DA830_UART0_RXD, DA830_UART0_TXD, |
879 | -1 | |
880 | }; | |
881 | ||
bcad6dc3 | 882 | const short da830_uart1_pins[] __initconst = { |
55c79a40 MG |
883 | DA830_UART1_RXD, DA830_UART1_TXD, |
884 | -1 | |
885 | }; | |
886 | ||
bcad6dc3 | 887 | const short da830_uart2_pins[] __initconst = { |
55c79a40 MG |
888 | DA830_UART2_RXD, DA830_UART2_TXD, |
889 | -1 | |
890 | }; | |
891 | ||
bcad6dc3 | 892 | const short da830_usb20_pins[] __initconst = { |
55c79a40 MG |
893 | DA830_USB0_DRVVBUS, DA830_USB_REFCLKIN, |
894 | -1 | |
895 | }; | |
896 | ||
bcad6dc3 | 897 | const short da830_usb11_pins[] __initconst = { |
55c79a40 MG |
898 | DA830_USB_REFCLKIN, |
899 | -1 | |
900 | }; | |
901 | ||
bcad6dc3 | 902 | const short da830_uhpi_pins[] __initconst = { |
55c79a40 MG |
903 | DA830_UHPI_HD_0, DA830_UHPI_HD_1, DA830_UHPI_HD_2, DA830_UHPI_HD_3, |
904 | DA830_UHPI_HD_4, DA830_UHPI_HD_5, DA830_UHPI_HD_6, DA830_UHPI_HD_7, | |
905 | DA830_UHPI_HD_8, DA830_UHPI_HD_9, DA830_UHPI_HD_10, DA830_UHPI_HD_11, | |
906 | DA830_UHPI_HD_12, DA830_UHPI_HD_13, DA830_UHPI_HD_14, DA830_UHPI_HD_15, | |
907 | DA830_UHPI_HCNTL0, DA830_UHPI_HCNTL1, DA830_UHPI_HHWIL, DA830_UHPI_HRNW, | |
908 | DA830_NUHPI_HAS, DA830_NUHPI_HCS, DA830_NUHPI_HDS1, DA830_NUHPI_HDS2, | |
909 | DA830_NUHPI_HINT, DA830_NUHPI_HRDY, | |
910 | -1 | |
911 | }; | |
912 | ||
bcad6dc3 | 913 | const short da830_cpgmac_pins[] __initconst = { |
55c79a40 MG |
914 | DA830_RMII_TXD_0, DA830_RMII_TXD_1, DA830_RMII_TXEN, DA830_RMII_CRS_DV, |
915 | DA830_RMII_RXD_0, DA830_RMII_RXD_1, DA830_RMII_RXER, DA830_MDIO_CLK, | |
916 | DA830_MDIO_D, | |
917 | -1 | |
918 | }; | |
919 | ||
bcad6dc3 | 920 | const short da830_emif3c_pins[] __initconst = { |
55c79a40 MG |
921 | DA830_EMB_SDCKE, DA830_EMB_CLK_GLUE, DA830_EMB_CLK, DA830_NEMB_CS_0, |
922 | DA830_NEMB_CAS, DA830_NEMB_RAS, DA830_NEMB_WE, DA830_EMB_BA_1, | |
923 | DA830_EMB_BA_0, DA830_EMB_A_0, DA830_EMB_A_1, DA830_EMB_A_2, | |
924 | DA830_EMB_A_3, DA830_EMB_A_4, DA830_EMB_A_5, DA830_EMB_A_6, | |
925 | DA830_EMB_A_7, DA830_EMB_A_8, DA830_EMB_A_9, DA830_EMB_A_10, | |
926 | DA830_EMB_A_11, DA830_EMB_A_12, DA830_NEMB_WE_DQM_3, | |
927 | DA830_NEMB_WE_DQM_2, DA830_EMB_D_0, DA830_EMB_D_1, DA830_EMB_D_2, | |
928 | DA830_EMB_D_3, DA830_EMB_D_4, DA830_EMB_D_5, DA830_EMB_D_6, | |
929 | DA830_EMB_D_7, DA830_EMB_D_8, DA830_EMB_D_9, DA830_EMB_D_10, | |
930 | DA830_EMB_D_11, DA830_EMB_D_12, DA830_EMB_D_13, DA830_EMB_D_14, | |
931 | DA830_EMB_D_15, DA830_EMB_D_16, DA830_EMB_D_17, DA830_EMB_D_18, | |
932 | DA830_EMB_D_19, DA830_EMB_D_20, DA830_EMB_D_21, DA830_EMB_D_22, | |
933 | DA830_EMB_D_23, DA830_EMB_D_24, DA830_EMB_D_25, DA830_EMB_D_26, | |
934 | DA830_EMB_D_27, DA830_EMB_D_28, DA830_EMB_D_29, DA830_EMB_D_30, | |
935 | DA830_EMB_D_31, DA830_NEMB_WE_DQM_1, DA830_NEMB_WE_DQM_0, | |
936 | -1 | |
937 | }; | |
938 | ||
bcad6dc3 | 939 | const short da830_mcasp0_pins[] __initconst = { |
55c79a40 MG |
940 | DA830_AHCLKX0, DA830_ACLKX0, DA830_AFSX0, |
941 | DA830_AHCLKR0, DA830_ACLKR0, DA830_AFSR0, DA830_AMUTE0, | |
942 | DA830_AXR0_0, DA830_AXR0_1, DA830_AXR0_2, DA830_AXR0_3, | |
943 | DA830_AXR0_4, DA830_AXR0_5, DA830_AXR0_6, DA830_AXR0_7, | |
944 | DA830_AXR0_8, DA830_AXR0_9, DA830_AXR0_10, DA830_AXR0_11, | |
945 | DA830_AXR0_12, DA830_AXR0_13, DA830_AXR0_14, DA830_AXR0_15, | |
946 | -1 | |
947 | }; | |
948 | ||
bcad6dc3 | 949 | const short da830_mcasp1_pins[] __initconst = { |
55c79a40 MG |
950 | DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1, |
951 | DA830_AHCLKR1, DA830_ACLKR1, DA830_AFSR1, DA830_AMUTE1, | |
952 | DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_3, | |
953 | DA830_AXR1_4, DA830_AXR1_5, DA830_AXR1_6, DA830_AXR1_7, | |
954 | DA830_AXR1_8, DA830_AXR1_9, DA830_AXR1_10, DA830_AXR1_11, | |
955 | -1 | |
956 | }; | |
957 | ||
bcad6dc3 | 958 | const short da830_mcasp2_pins[] __initconst = { |
55c79a40 MG |
959 | DA830_AHCLKX2, DA830_ACLKX2, DA830_AFSX2, |
960 | DA830_AHCLKR2, DA830_ACLKR2, DA830_AFSR2, DA830_AMUTE2, | |
961 | DA830_AXR2_0, DA830_AXR2_1, DA830_AXR2_2, DA830_AXR2_3, | |
962 | -1 | |
963 | }; | |
964 | ||
bcad6dc3 | 965 | const short da830_i2c0_pins[] __initconst = { |
55c79a40 MG |
966 | DA830_I2C0_SDA, DA830_I2C0_SCL, |
967 | -1 | |
968 | }; | |
969 | ||
bcad6dc3 | 970 | const short da830_i2c1_pins[] __initconst = { |
55c79a40 MG |
971 | DA830_I2C1_SCL, DA830_I2C1_SDA, |
972 | -1 | |
973 | }; | |
974 | ||
bcad6dc3 | 975 | const short da830_lcdcntl_pins[] __initconst = { |
55c79a40 MG |
976 | DA830_LCD_D_0, DA830_LCD_D_1, DA830_LCD_D_2, DA830_LCD_D_3, |
977 | DA830_LCD_D_4, DA830_LCD_D_5, DA830_LCD_D_6, DA830_LCD_D_7, | |
978 | DA830_LCD_D_8, DA830_LCD_D_9, DA830_LCD_D_10, DA830_LCD_D_11, | |
979 | DA830_LCD_D_12, DA830_LCD_D_13, DA830_LCD_D_14, DA830_LCD_D_15, | |
980 | DA830_LCD_PCLK, DA830_LCD_HSYNC, DA830_LCD_VSYNC, DA830_NLCD_AC_ENB_CS, | |
981 | DA830_LCD_MCLK, | |
982 | -1 | |
983 | }; | |
984 | ||
bcad6dc3 | 985 | const short da830_pwm_pins[] __initconst = { |
55c79a40 MG |
986 | DA830_ECAP0_APWM0, DA830_ECAP1_APWM1, DA830_EPWM0B, DA830_EPWM0A, |
987 | DA830_EPWMSYNCI, DA830_EPWMSYNC0, DA830_ECAP2_APWM2, DA830_EHRPWMGLUETZ, | |
988 | DA830_EPWM2B, DA830_EPWM2A, DA830_EPWM1B, DA830_EPWM1A, | |
989 | -1 | |
990 | }; | |
991 | ||
bcad6dc3 | 992 | const short da830_ecap0_pins[] __initconst = { |
55c79a40 MG |
993 | DA830_ECAP0_APWM0, |
994 | -1 | |
995 | }; | |
996 | ||
bcad6dc3 | 997 | const short da830_ecap1_pins[] __initconst = { |
55c79a40 MG |
998 | DA830_ECAP1_APWM1, |
999 | -1 | |
1000 | }; | |
1001 | ||
bcad6dc3 | 1002 | const short da830_ecap2_pins[] __initconst = { |
55c79a40 MG |
1003 | DA830_ECAP2_APWM2, |
1004 | -1 | |
1005 | }; | |
1006 | ||
bcad6dc3 | 1007 | const short da830_eqep0_pins[] __initconst = { |
55c79a40 MG |
1008 | DA830_EQEP0I, DA830_EQEP0S, DA830_EQEP0A, DA830_EQEP0B, |
1009 | -1 | |
1010 | }; | |
1011 | ||
bcad6dc3 | 1012 | const short da830_eqep1_pins[] __initconst = { |
55c79a40 MG |
1013 | DA830_EQEP1I, DA830_EQEP1S, DA830_EQEP1A, DA830_EQEP1B, |
1014 | -1 | |
1015 | }; | |
1016 | ||
55c79a40 MG |
1017 | /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ |
1018 | static u8 da830_default_priorities[DA830_N_CP_INTC_IRQ] = { | |
1019 | [IRQ_DA8XX_COMMTX] = 7, | |
1020 | [IRQ_DA8XX_COMMRX] = 7, | |
1021 | [IRQ_DA8XX_NINT] = 7, | |
1022 | [IRQ_DA8XX_EVTOUT0] = 7, | |
1023 | [IRQ_DA8XX_EVTOUT1] = 7, | |
1024 | [IRQ_DA8XX_EVTOUT2] = 7, | |
1025 | [IRQ_DA8XX_EVTOUT3] = 7, | |
1026 | [IRQ_DA8XX_EVTOUT4] = 7, | |
1027 | [IRQ_DA8XX_EVTOUT5] = 7, | |
1028 | [IRQ_DA8XX_EVTOUT6] = 7, | |
55c79a40 MG |
1029 | [IRQ_DA8XX_EVTOUT7] = 7, |
1030 | [IRQ_DA8XX_CCINT0] = 7, | |
1031 | [IRQ_DA8XX_CCERRINT] = 7, | |
1032 | [IRQ_DA8XX_TCERRINT0] = 7, | |
1033 | [IRQ_DA8XX_AEMIFINT] = 7, | |
1034 | [IRQ_DA8XX_I2CINT0] = 7, | |
1035 | [IRQ_DA8XX_MMCSDINT0] = 7, | |
1036 | [IRQ_DA8XX_MMCSDINT1] = 7, | |
1037 | [IRQ_DA8XX_ALLINT0] = 7, | |
1038 | [IRQ_DA8XX_RTC] = 7, | |
1039 | [IRQ_DA8XX_SPINT0] = 7, | |
1040 | [IRQ_DA8XX_TINT12_0] = 7, | |
1041 | [IRQ_DA8XX_TINT34_0] = 7, | |
1042 | [IRQ_DA8XX_TINT12_1] = 7, | |
1043 | [IRQ_DA8XX_TINT34_1] = 7, | |
1044 | [IRQ_DA8XX_UARTINT0] = 7, | |
1045 | [IRQ_DA8XX_KEYMGRINT] = 7, | |
55c79a40 | 1046 | [IRQ_DA830_MPUERR] = 7, |
55c79a40 MG |
1047 | [IRQ_DA8XX_CHIPINT0] = 7, |
1048 | [IRQ_DA8XX_CHIPINT1] = 7, | |
1049 | [IRQ_DA8XX_CHIPINT2] = 7, | |
1050 | [IRQ_DA8XX_CHIPINT3] = 7, | |
1051 | [IRQ_DA8XX_TCERRINT1] = 7, | |
1052 | [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7, | |
1053 | [IRQ_DA8XX_C0_RX_PULSE] = 7, | |
1054 | [IRQ_DA8XX_C0_TX_PULSE] = 7, | |
1055 | [IRQ_DA8XX_C0_MISC_PULSE] = 7, | |
1056 | [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7, | |
1057 | [IRQ_DA8XX_C1_RX_PULSE] = 7, | |
1058 | [IRQ_DA8XX_C1_TX_PULSE] = 7, | |
1059 | [IRQ_DA8XX_C1_MISC_PULSE] = 7, | |
1060 | [IRQ_DA8XX_MEMERR] = 7, | |
1061 | [IRQ_DA8XX_GPIO0] = 7, | |
1062 | [IRQ_DA8XX_GPIO1] = 7, | |
1063 | [IRQ_DA8XX_GPIO2] = 7, | |
1064 | [IRQ_DA8XX_GPIO3] = 7, | |
1065 | [IRQ_DA8XX_GPIO4] = 7, | |
1066 | [IRQ_DA8XX_GPIO5] = 7, | |
1067 | [IRQ_DA8XX_GPIO6] = 7, | |
1068 | [IRQ_DA8XX_GPIO7] = 7, | |
1069 | [IRQ_DA8XX_GPIO8] = 7, | |
1070 | [IRQ_DA8XX_I2CINT1] = 7, | |
1071 | [IRQ_DA8XX_LCDINT] = 7, | |
1072 | [IRQ_DA8XX_UARTINT1] = 7, | |
1073 | [IRQ_DA8XX_MCASPINT] = 7, | |
1074 | [IRQ_DA8XX_ALLINT1] = 7, | |
1075 | [IRQ_DA8XX_SPINT1] = 7, | |
1076 | [IRQ_DA8XX_UHPI_INT1] = 7, | |
1077 | [IRQ_DA8XX_USB_INT] = 7, | |
1078 | [IRQ_DA8XX_IRQN] = 7, | |
1079 | [IRQ_DA8XX_RWAKEUP] = 7, | |
1080 | [IRQ_DA8XX_UARTINT2] = 7, | |
1081 | [IRQ_DA8XX_DFTSSINT] = 7, | |
1082 | [IRQ_DA8XX_EHRPWM0] = 7, | |
1083 | [IRQ_DA8XX_EHRPWM0TZ] = 7, | |
1084 | [IRQ_DA8XX_EHRPWM1] = 7, | |
1085 | [IRQ_DA8XX_EHRPWM1TZ] = 7, | |
1086 | [IRQ_DA830_EHRPWM2] = 7, | |
1087 | [IRQ_DA830_EHRPWM2TZ] = 7, | |
1088 | [IRQ_DA8XX_ECAP0] = 7, | |
1089 | [IRQ_DA8XX_ECAP1] = 7, | |
1090 | [IRQ_DA8XX_ECAP2] = 7, | |
1091 | [IRQ_DA830_EQEP0] = 7, | |
1092 | [IRQ_DA830_EQEP1] = 7, | |
1093 | [IRQ_DA830_T12CMPINT0_0] = 7, | |
1094 | [IRQ_DA830_T12CMPINT1_0] = 7, | |
1095 | [IRQ_DA830_T12CMPINT2_0] = 7, | |
1096 | [IRQ_DA830_T12CMPINT3_0] = 7, | |
1097 | [IRQ_DA830_T12CMPINT4_0] = 7, | |
1098 | [IRQ_DA830_T12CMPINT5_0] = 7, | |
1099 | [IRQ_DA830_T12CMPINT6_0] = 7, | |
1100 | [IRQ_DA830_T12CMPINT7_0] = 7, | |
1101 | [IRQ_DA830_T12CMPINT0_1] = 7, | |
1102 | [IRQ_DA830_T12CMPINT1_1] = 7, | |
1103 | [IRQ_DA830_T12CMPINT2_1] = 7, | |
1104 | [IRQ_DA830_T12CMPINT3_1] = 7, | |
1105 | [IRQ_DA830_T12CMPINT4_1] = 7, | |
1106 | [IRQ_DA830_T12CMPINT5_1] = 7, | |
1107 | [IRQ_DA830_T12CMPINT6_1] = 7, | |
1108 | [IRQ_DA830_T12CMPINT7_1] = 7, | |
1109 | [IRQ_DA8XX_ARMCLKSTOPREQ] = 7, | |
1110 | }; | |
1111 | ||
1112 | static struct map_desc da830_io_desc[] = { | |
1113 | { | |
1114 | .virtual = IO_VIRT, | |
1115 | .pfn = __phys_to_pfn(IO_PHYS), | |
1116 | .length = IO_SIZE, | |
1117 | .type = MT_DEVICE | |
1118 | }, | |
1119 | { | |
1120 | .virtual = DA8XX_CP_INTC_VIRT, | |
1121 | .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE), | |
1122 | .length = DA8XX_CP_INTC_SIZE, | |
1123 | .type = MT_DEVICE | |
1124 | }, | |
1125 | }; | |
1126 | ||
e4c822c7 | 1127 | static u32 da830_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE }; |
55c79a40 MG |
1128 | |
1129 | /* Contents of JTAG ID register used to identify exact cpu type */ | |
1130 | static struct davinci_id da830_ids[] = { | |
1131 | { | |
1132 | .variant = 0x0, | |
1133 | .part_no = 0xb7df, | |
1134 | .manufacturer = 0x017, /* 0x02f >> 1 */ | |
1135 | .cpu_id = DAVINCI_CPU_ID_DA830, | |
f2024a99 KH |
1136 | .name = "da830/omap-l137 rev1.0", |
1137 | }, | |
1138 | { | |
1139 | .variant = 0x8, | |
1140 | .part_no = 0xb7df, | |
1141 | .manufacturer = 0x017, | |
1142 | .cpu_id = DAVINCI_CPU_ID_DA830, | |
1143 | .name = "da830/omap-l137 rev1.1", | |
1144 | }, | |
1145 | { | |
1146 | .variant = 0x9, | |
1147 | .part_no = 0xb7df, | |
1148 | .manufacturer = 0x017, | |
1149 | .cpu_id = DAVINCI_CPU_ID_DA830, | |
1150 | .name = "da830/omap-l137 rev2.0", | |
55c79a40 MG |
1151 | }, |
1152 | }; | |
1153 | ||
f606d38d KS |
1154 | static struct davinci_gpio_platform_data da830_gpio_platform_data = { |
1155 | .ngpio = 128, | |
f606d38d KS |
1156 | }; |
1157 | ||
1158 | int __init da830_register_gpio(void) | |
1159 | { | |
1160 | return da8xx_register_gpio(&da830_gpio_platform_data); | |
1161 | } | |
1162 | ||
55c79a40 MG |
1163 | static struct davinci_timer_instance da830_timer_instance[2] = { |
1164 | { | |
1bcd38ad | 1165 | .base = DA8XX_TIMER64P0_BASE, |
55c79a40 MG |
1166 | .bottom_irq = IRQ_DA8XX_TINT12_0, |
1167 | .top_irq = IRQ_DA8XX_TINT34_0, | |
1168 | .cmp_off = DA830_CMP12_0, | |
1169 | .cmp_irq = IRQ_DA830_T12CMPINT0_0, | |
1170 | }, | |
1171 | { | |
1bcd38ad | 1172 | .base = DA8XX_TIMER64P1_BASE, |
55c79a40 MG |
1173 | .bottom_irq = IRQ_DA8XX_TINT12_1, |
1174 | .top_irq = IRQ_DA8XX_TINT34_1, | |
1175 | .cmp_off = DA830_CMP12_0, | |
1176 | .cmp_irq = IRQ_DA830_T12CMPINT0_1, | |
1177 | }, | |
1178 | }; | |
1179 | ||
1180 | /* | |
1181 | * T0_BOT: Timer 0, bottom : Used for clock_event & clocksource | |
1182 | * T0_TOP: Timer 0, top : Used by DSP | |
1183 | * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer | |
1184 | */ | |
1185 | static struct davinci_timer_info da830_timer_info = { | |
1186 | .timers = da830_timer_instance, | |
1187 | .clockevent_id = T0_BOT, | |
1188 | .clocksource_id = T0_BOT, | |
1189 | }; | |
1190 | ||
1191 | static struct davinci_soc_info davinci_soc_info_da830 = { | |
1192 | .io_desc = da830_io_desc, | |
1193 | .io_desc_num = ARRAY_SIZE(da830_io_desc), | |
3347db83 | 1194 | .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG, |
55c79a40 MG |
1195 | .ids = da830_ids, |
1196 | .ids_num = ARRAY_SIZE(da830_ids), | |
1197 | .cpu_clks = da830_clks, | |
1198 | .psc_bases = da830_psc_bases, | |
1199 | .psc_bases_num = ARRAY_SIZE(da830_psc_bases), | |
779b0d53 | 1200 | .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120, |
55c79a40 MG |
1201 | .pinmux_pins = da830_pins, |
1202 | .pinmux_pins_num = ARRAY_SIZE(da830_pins), | |
bd808947 | 1203 | .intc_base = DA8XX_CP_INTC_BASE, |
55c79a40 MG |
1204 | .intc_type = DAVINCI_INTC_TYPE_CP_INTC, |
1205 | .intc_irq_prios = da830_default_priorities, | |
1206 | .intc_irq_num = DA830_N_CP_INTC_IRQ, | |
1207 | .timer_info = &da830_timer_info, | |
55c79a40 MG |
1208 | .emac_pdata = &da8xx_emac_pdata, |
1209 | }; | |
1210 | ||
1211 | void __init da830_init(void) | |
1212 | { | |
1213 | davinci_common_init(&davinci_soc_info_da830); | |
bcd6a1c6 CC |
1214 | |
1215 | da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K); | |
1216 | WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"); | |
55c79a40 | 1217 | } |