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[deliverable/linux.git] / arch / arm / mach-davinci / da850.c
CommitLineData
e1a8d7e2
SR		 1/*
2 * TI DA850/OMAP-L138 chip specific setup
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Derived from: arch/arm/mach-davinci/da830.c
7 * Original Copyrights follow:
8 *
9 * 2009 (c) MontaVista Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
2d34e507 14#include <linux/clkdev.h>
2f8163ba 15#include <linux/gpio.h>
e1a8d7e2
SR		 16#include <linux/init.h>
17#include <linux/clk.h>
18#include <linux/platform_device.h>
683b1e1f 19#include <linux/cpufreq.h>
35f9acd8 20#include <linux/regulator/consumer.h>
f606d38d 21#include <linux/platform_data/gpio-davinci.h>
e1a8d7e2
SR		 22
23#include <asm/mach/map.h>
24
3acf731c 25#include "psc.h"
e1a8d7e2
SR		 26#include <mach/irqs.h>
27#include <mach/cputype.h>
28#include <mach/common.h>
29#include <mach/time.h>
30#include <mach/da8xx.h>
683b1e1f 31#include <mach/cpufreq.h>
044ca015 32#include <mach/pm.h>
e1a8d7e2
SR		 33
34#include "clock.h"
35#include "mux.h"
36
37#define DA850_PLL1_BASE 0x01e1a000
38#define DA850_TIMER64P2_BASE 0x01f0c000
39#define DA850_TIMER64P3_BASE 0x01f0d000
40
41#define DA850_REF_FREQ 24000000
42
5d36a332 43#define CFGCHIP3_ASYNC3_CLKSRC BIT(4)
7aad472b 44#define CFGCHIP3_PLL1_MASTER_LOCK BIT(5)
683b1e1f
SN		 45#define CFGCHIP0_PLL_MASTER_LOCK BIT(4)
46
47static int da850_set_armrate(struct clk *clk, unsigned long rate);
48static int da850_round_armrate(struct clk *clk, unsigned long rate);
49static int da850_set_pll0rate(struct clk *clk, unsigned long armrate);
5d36a332 50
e1a8d7e2
SR		 51static struct pll_data pll0_data = {
52 .num = 1,
53 .phys_base = DA8XX_PLL0_BASE,
54 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
55};
56
57static struct clk ref_clk = {
58 .name = "ref_clk",
59 .rate = DA850_REF_FREQ,
8d54297b 60 .set_rate = davinci_simple_set_rate,
e1a8d7e2
SR		 61};
62
63static struct clk pll0_clk = {
64 .name = "pll0",
65 .parent = &ref_clk,
66 .pll_data = &pll0_data,
67 .flags = CLK_PLL,
683b1e1f 68 .set_rate = da850_set_pll0rate,
e1a8d7e2
SR		 69};
70
71static struct clk pll0_aux_clk = {
72 .name = "pll0_aux_clk",
73 .parent = &pll0_clk,
74 .flags = CLK_PLL | PRE_PLL,
75};
76
09810a85
RT		 77static struct clk pll0_sysclk1 = {
78 .name = "pll0_sysclk1",
79 .parent = &pll0_clk,
80 .flags = CLK_PLL,
81 .div_reg = PLLDIV1,
82};
83
e1a8d7e2
SR		 84static struct clk pll0_sysclk2 = {
85 .name = "pll0_sysclk2",
86 .parent = &pll0_clk,
87 .flags = CLK_PLL,
88 .div_reg = PLLDIV2,
89};
90
91static struct clk pll0_sysclk3 = {
92 .name = "pll0_sysclk3",
93 .parent = &pll0_clk,
94 .flags = CLK_PLL,
95 .div_reg = PLLDIV3,
b987c4b2
SN		 96 .set_rate = davinci_set_sysclk_rate,
97 .maxrate = 100000000,
e1a8d7e2
SR		 98};
99
100static struct clk pll0_sysclk4 = {
101 .name = "pll0_sysclk4",
102 .parent = &pll0_clk,
103 .flags = CLK_PLL,
104 .div_reg = PLLDIV4,
105};
106
107static struct clk pll0_sysclk5 = {
108 .name = "pll0_sysclk5",
109 .parent = &pll0_clk,
110 .flags = CLK_PLL,
111 .div_reg = PLLDIV5,
112};
113
114static struct clk pll0_sysclk6 = {
115 .name = "pll0_sysclk6",
116 .parent = &pll0_clk,
117 .flags = CLK_PLL,
118 .div_reg = PLLDIV6,
119};
120
121static struct clk pll0_sysclk7 = {
122 .name = "pll0_sysclk7",
123 .parent = &pll0_clk,
124 .flags = CLK_PLL,
125 .div_reg = PLLDIV7,
126};
127
128static struct pll_data pll1_data = {
129 .num = 2,
130 .phys_base = DA850_PLL1_BASE,
131 .flags = PLL_HAS_POSTDIV,
132};
133
134static struct clk pll1_clk = {
135 .name = "pll1",
136 .parent = &ref_clk,
137 .pll_data = &pll1_data,
138 .flags = CLK_PLL,
139};
140
141static struct clk pll1_aux_clk = {
142 .name = "pll1_aux_clk",
143 .parent = &pll1_clk,
144 .flags = CLK_PLL | PRE_PLL,
145};
146
147static struct clk pll1_sysclk2 = {
148 .name = "pll1_sysclk2",
149 .parent = &pll1_clk,
150 .flags = CLK_PLL,
151 .div_reg = PLLDIV2,
152};
153
154static struct clk pll1_sysclk3 = {
155 .name = "pll1_sysclk3",
156 .parent = &pll1_clk,
157 .flags = CLK_PLL,
158 .div_reg = PLLDIV3,
159};
160
3f2a09d5
DL		 161static int da850_async3_set_parent(struct clk *clk, struct clk *parent)
162{
163 u32 val;
164
165 val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
166
167 if (parent == &pll0_sysclk2) {
168 val &= ~CFGCHIP3_ASYNC3_CLKSRC;
169 } else if (parent == &pll1_sysclk2) {
170 val |= CFGCHIP3_ASYNC3_CLKSRC;
171 } else {
172 pr_err("Bad parent on async3 clock mux\n");
173 return -EINVAL;
174 }
175
176 writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
177
178 return 0;
179}
180
181static struct clk async3_clk = {
182 .name = "async3",
183 .parent = &pll1_sysclk2,
184 .set_parent = da850_async3_set_parent,
185};
186
e1a8d7e2
SR		 187static struct clk i2c0_clk = {
188 .name = "i2c0",
189 .parent = &pll0_aux_clk,
190};
191
192static struct clk timerp64_0_clk = {
193 .name = "timer0",
194 .parent = &pll0_aux_clk,
195};
196
197static struct clk timerp64_1_clk = {
198 .name = "timer1",
199 .parent = &pll0_aux_clk,
200};
201
202static struct clk arm_rom_clk = {
203 .name = "arm_rom",
204 .parent = &pll0_sysclk2,
205 .lpsc = DA8XX_LPSC0_ARM_RAM_ROM,
206 .flags = ALWAYS_ENABLED,
207};
208
209static struct clk tpcc0_clk = {
210 .name = "tpcc0",
211 .parent = &pll0_sysclk2,
212 .lpsc = DA8XX_LPSC0_TPCC,
213 .flags = ALWAYS_ENABLED | CLK_PSC,
214};
215
216static struct clk tptc0_clk = {
217 .name = "tptc0",
218 .parent = &pll0_sysclk2,
219 .lpsc = DA8XX_LPSC0_TPTC0,
220 .flags = ALWAYS_ENABLED,
221};
222
223static struct clk tptc1_clk = {
224 .name = "tptc1",
225 .parent = &pll0_sysclk2,
226 .lpsc = DA8XX_LPSC0_TPTC1,
227 .flags = ALWAYS_ENABLED,
228};
229
230static struct clk tpcc1_clk = {
231 .name = "tpcc1",
232 .parent = &pll0_sysclk2,
233 .lpsc = DA850_LPSC1_TPCC1,
789a785e 234 .gpsc = 1,
e1a8d7e2 235 .flags = CLK_PSC | ALWAYS_ENABLED,
e1a8d7e2
SR		 236};
237
238static struct clk tptc2_clk = {
239 .name = "tptc2",
240 .parent = &pll0_sysclk2,
241 .lpsc = DA850_LPSC1_TPTC2,
789a785e 242 .gpsc = 1,
e1a8d7e2 243 .flags = ALWAYS_ENABLED,
e1a8d7e2
SR		 244};
245
8e0d72d2
MP		 246static struct clk pruss_clk = {
247 .name = "pruss",
248 .parent = &pll0_sysclk2,
249 .lpsc = DA8XX_LPSC0_PRUSS,
250};
251
e1a8d7e2
SR		 252static struct clk uart0_clk = {
253 .name = "uart0",
254 .parent = &pll0_sysclk2,
255 .lpsc = DA8XX_LPSC0_UART0,
256};
257
258static struct clk uart1_clk = {
259 .name = "uart1",
3f2a09d5 260 .parent = &async3_clk,
e1a8d7e2 261 .lpsc = DA8XX_LPSC1_UART1,
789a785e 262 .gpsc = 1,
e1a8d7e2
SR		 263};
264
265static struct clk uart2_clk = {
266 .name = "uart2",
3f2a09d5 267 .parent = &async3_clk,
e1a8d7e2 268 .lpsc = DA8XX_LPSC1_UART2,
789a785e 269 .gpsc = 1,
e1a8d7e2
SR		 270};
271
272static struct clk aintc_clk = {
273 .name = "aintc",
274 .parent = &pll0_sysclk4,
275 .lpsc = DA8XX_LPSC0_AINTC,
276 .flags = ALWAYS_ENABLED,
277};
278
279static struct clk gpio_clk = {
280 .name = "gpio",
281 .parent = &pll0_sysclk4,
282 .lpsc = DA8XX_LPSC1_GPIO,
789a785e 283 .gpsc = 1,
e1a8d7e2
SR		 284};
285
286static struct clk i2c1_clk = {
287 .name = "i2c1",
288 .parent = &pll0_sysclk4,
289 .lpsc = DA8XX_LPSC1_I2C,
789a785e 290 .gpsc = 1,
e1a8d7e2
SR		 291};
292
293static struct clk emif3_clk = {
294 .name = "emif3",
295 .parent = &pll0_sysclk5,
296 .lpsc = DA8XX_LPSC1_EMIF3C,
789a785e 297 .gpsc = 1,
e1a8d7e2 298 .flags = ALWAYS_ENABLED,
e1a8d7e2
SR		 299};
300
301static struct clk arm_clk = {
302 .name = "arm",
303 .parent = &pll0_sysclk6,
304 .lpsc = DA8XX_LPSC0_ARM,
305 .flags = ALWAYS_ENABLED,
683b1e1f
SN		 306 .set_rate = da850_set_armrate,
307 .round_rate = da850_round_armrate,
e1a8d7e2
SR		 308};
309
310static struct clk rmii_clk = {
311 .name = "rmii",
312 .parent = &pll0_sysclk7,
313};
314
5a4b1315
SR		 315static struct clk emac_clk = {
316 .name = "emac",
317 .parent = &pll0_sysclk4,
318 .lpsc = DA8XX_LPSC1_CPGMAC,
789a785e 319 .gpsc = 1,
5a4b1315
SR		 320};
321
491214e1
C		 322static struct clk mcasp_clk = {
323 .name = "mcasp",
3f2a09d5 324 .parent = &async3_clk,
491214e1 325 .lpsc = DA8XX_LPSC1_McASP0,
789a785e 326 .gpsc = 1,
491214e1
C		 327};
328
5cbdf276
SR		 329static struct clk lcdc_clk = {
330 .name = "lcdc",
331 .parent = &pll0_sysclk2,
332 .lpsc = DA8XX_LPSC1_LCDC,
789a785e 333 .gpsc = 1,
5cbdf276
SR		 334};
335
051a6687
JK		 336static struct clk mmcsd0_clk = {
337 .name = "mmcsd0",
700691f2
SR		 338 .parent = &pll0_sysclk2,
339 .lpsc = DA8XX_LPSC0_MMC_SD,
340};
341
051a6687
JK		 342static struct clk mmcsd1_clk = {
343 .name = "mmcsd1",
344 .parent = &pll0_sysclk2,
345 .lpsc = DA850_LPSC1_MMC_SD1,
346 .gpsc = 1,
347};
348
38beb929
SR		 349static struct clk aemif_clk = {
350 .name = "aemif",
351 .parent = &pll0_sysclk3,
352 .lpsc = DA8XX_LPSC0_EMIF25,
353 .flags = ALWAYS_ENABLED,
354};
355
5efe330a
VR		 356static struct clk usb11_clk = {
357 .name = "usb11",
358 .parent = &pll0_sysclk4,
359 .lpsc = DA8XX_LPSC1_USB11,
360 .gpsc = 1,
361};
362
363static struct clk usb20_clk = {
364 .name = "usb20",
365 .parent = &pll0_sysclk2,
366 .lpsc = DA8XX_LPSC1_USB20,
367 .gpsc = 1,
368};
369
12d35cf3
MW		 370static struct clk spi0_clk = {
371 .name = "spi0",
372 .parent = &pll0_sysclk2,
373 .lpsc = DA8XX_LPSC0_SPI0,
374};
375
376static struct clk spi1_clk = {
377 .name = "spi1",
3f2a09d5 378 .parent = &async3_clk,
12d35cf3
MW		 379 .lpsc = DA8XX_LPSC1_SPI1,
380 .gpsc = 1,
12d35cf3
MW		 381};
382
154d54a8
MH		 383static struct clk vpif_clk = {
384 .name = "vpif",
385 .parent = &pll0_sysclk2,
386 .lpsc = DA850_LPSC1_VPIF,
387 .gpsc = 1,
388};
389
cbb2c961
SN		 390static struct clk sata_clk = {
391 .name = "sata",
392 .parent = &pll0_sysclk2,
393 .lpsc = DA850_LPSC1_SATA,
394 .gpsc = 1,
395 .flags = PSC_FORCE,
396};
397
09810a85
RT		 398static struct clk dsp_clk = {
399 .name = "dsp",
400 .parent = &pll0_sysclk1,
401 .domain = DAVINCI_GPSC_DSPDOMAIN,
402 .lpsc = DA8XX_LPSC0_GEM,
403 .flags = PSC_LRST | PSC_FORCE,
404};
405
bb170e61
PA		 406static struct clk ehrpwm_clk = {
407 .name = "ehrpwm",
3f2a09d5 408 .parent = &async3_clk,
bb170e61
PA		 409 .lpsc = DA8XX_LPSC1_PWM,
410 .gpsc = 1,
bb170e61
PA		 411};
412
413#define DA8XX_EHRPWM_TBCLKSYNC BIT(12)
414
415static void ehrpwm_tblck_enable(struct clk *clk)
416{
417 u32 val;
418
419 val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
420 val |= DA8XX_EHRPWM_TBCLKSYNC;
421 writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
422}
423
424static void ehrpwm_tblck_disable(struct clk *clk)
425{
426 u32 val;
427
428 val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
429 val &= ~DA8XX_EHRPWM_TBCLKSYNC;
430 writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
431}
432
433static struct clk ehrpwm_tbclk = {
434 .name = "ehrpwm_tbclk",
435 .parent = &ehrpwm_clk,
436 .clk_enable = ehrpwm_tblck_enable,
437 .clk_disable = ehrpwm_tblck_disable,
438};
439
440static struct clk ecap_clk = {
441 .name = "ecap",
3f2a09d5 442 .parent = &async3_clk,
bb170e61
PA		 443 .lpsc = DA8XX_LPSC1_ECAP,
444 .gpsc = 1,
bb170e61
PA		 445};
446
08aca087 447static struct clk_lookup da850_clks[] = {
e1a8d7e2
SR		 448 CLK(NULL, "ref", &ref_clk),
449 CLK(NULL, "pll0", &pll0_clk),
450 CLK(NULL, "pll0_aux", &pll0_aux_clk),
09810a85 451 CLK(NULL, "pll0_sysclk1", &pll0_sysclk1),
e1a8d7e2
SR		 452 CLK(NULL, "pll0_sysclk2", &pll0_sysclk2),
453 CLK(NULL, "pll0_sysclk3", &pll0_sysclk3),
454 CLK(NULL, "pll0_sysclk4", &pll0_sysclk4),
455 CLK(NULL, "pll0_sysclk5", &pll0_sysclk5),
456 CLK(NULL, "pll0_sysclk6", &pll0_sysclk6),
457 CLK(NULL, "pll0_sysclk7", &pll0_sysclk7),
458 CLK(NULL, "pll1", &pll1_clk),
459 CLK(NULL, "pll1_aux", &pll1_aux_clk),
460 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
461 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
3f2a09d5 462 CLK(NULL, "async3", &async3_clk),
e1a8d7e2
SR		 463 CLK("i2c_davinci.1", NULL, &i2c0_clk),
464 CLK(NULL, "timer0", &timerp64_0_clk),
84374812 465 CLK("davinci-wdt", NULL, &timerp64_1_clk),
e1a8d7e2
SR		 466 CLK(NULL, "arm_rom", &arm_rom_clk),
467 CLK(NULL, "tpcc0", &tpcc0_clk),
468 CLK(NULL, "tptc0", &tptc0_clk),
469 CLK(NULL, "tptc1", &tptc1_clk),
470 CLK(NULL, "tpcc1", &tpcc1_clk),
471 CLK(NULL, "tptc2", &tptc2_clk),
8e0d72d2 472 CLK("pruss_uio", "pruss", &pruss_clk),
19955c3d
MP		 473 CLK("serial8250.0", NULL, &uart0_clk),
474 CLK("serial8250.1", NULL, &uart1_clk),
475 CLK("serial8250.2", NULL, &uart2_clk),
e1a8d7e2
SR		 476 CLK(NULL, "aintc", &aintc_clk),
477 CLK(NULL, "gpio", &gpio_clk),
478 CLK("i2c_davinci.2", NULL, &i2c1_clk),
479 CLK(NULL, "emif3", &emif3_clk),
480 CLK(NULL, "arm", &arm_clk),
481 CLK(NULL, "rmii", &rmii_clk),
5a4b1315 482 CLK("davinci_emac.1", NULL, &emac_clk),
46c18334 483 CLK("davinci_mdio.0", "fck", &emac_clk),
491214e1 484 CLK("davinci-mcasp.0", NULL, &mcasp_clk),
81cec3c7 485 CLK("da8xx_lcdc.0", "fck", &lcdc_clk),
d7ca4c75
MP		 486 CLK("da830-mmc.0", NULL, &mmcsd0_clk),
487 CLK("da830-mmc.1", NULL, &mmcsd1_clk),
38beb929 488 CLK(NULL, "aemif", &aemif_clk),
5efe330a
VR		 489 CLK(NULL, "usb11", &usb11_clk),
490 CLK(NULL, "usb20", &usb20_clk),
12d35cf3
MW		 491 CLK("spi_davinci.0", NULL, &spi0_clk),
492 CLK("spi_davinci.1", NULL, &spi1_clk),
154d54a8 493 CLK("vpif", NULL, &vpif_clk),
080c492d 494 CLK("ahci_da850", NULL, &sata_clk),
09810a85 495 CLK("davinci-rproc.0", NULL, &dsp_clk),
bb170e61
PA		 496 CLK("ehrpwm", "fck", &ehrpwm_clk),
497 CLK("ehrpwm", "tbclk", &ehrpwm_tbclk),
498 CLK("ecap", "fck", &ecap_clk),
e1a8d7e2
SR		 499 CLK(NULL, NULL, NULL),
500};
501
502/*
503 * Device specific mux setup
504 *
505 * soc description mux mode mode mux dbg
506 * reg offset mask mode
507 */
508static const struct mux_config da850_pins[] = {
509#ifdef CONFIG_DAVINCI_MUX
510 /* UART0 function */
511 MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false)
512 MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false)
513 MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false)
514 MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false)
515 /* UART1 function */
516 MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false)
517 MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false)
518 /* UART2 function */
519 MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false)
520 MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false)
521 /* I2C1 function */
522 MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false)
523 MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false)
524 /* I2C0 function */
525 MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false)
526 MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false)
5a4b1315
SR		 527 /* EMAC function */
528 MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false)
529 MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false)
530 MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false)
531 MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false)
532 MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false)
533 MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false)
534 MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false)
535 MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false)
536 MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false)
537 MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false)
538 MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false)
539 MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false)
540 MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false)
541 MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false)
542 MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false)
53ca5c91
SR		 543 MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false)
544 MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false)
2206771c
C		 545 MUX_CFG(DA850, RMII_TXD_0, 14, 12, 15, 8, false)
546 MUX_CFG(DA850, RMII_TXD_1, 14, 8, 15, 8, false)
547 MUX_CFG(DA850, RMII_TXEN, 14, 16, 15, 8, false)
548 MUX_CFG(DA850, RMII_CRS_DV, 15, 4, 15, 8, false)
549 MUX_CFG(DA850, RMII_RXD_0, 14, 24, 15, 8, false)
550 MUX_CFG(DA850, RMII_RXD_1, 14, 20, 15, 8, false)
551 MUX_CFG(DA850, RMII_RXER, 14, 28, 15, 8, false)
552 MUX_CFG(DA850, RMII_MHZ_50_CLK, 15, 0, 15, 0, false)
491214e1
C		 553 /* McASP function */
554 MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false)
555 MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false)
556 MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false)
557 MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false)
558 MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false)
559 MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false)
560 MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false)
561 MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false)
562 MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false)
563 MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false)
564 MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false)
565 MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false)
566 MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false)
567 MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false)
568 MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false)
569 MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false)
570 MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false)
571 MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false)
572 MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false)
573 MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false)
574 MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false)
575 MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false)
576 MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false)
5cbdf276
SR		 577 /* LCD function */
578 MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false)
579 MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false)
580 MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false)
581 MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false)
582 MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false)
583 MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false)
584 MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false)
585 MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false)
586 MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false)
587 MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false)
588 MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false)
589 MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false)
590 MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false)
591 MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false)
592 MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false)
593 MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false)
594 MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false)
595 MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false)
596 MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false)
597 MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false)
700691f2
SR		 598 /* MMC/SD0 function */
599 MUX_CFG(DA850, MMCSD0_DAT_0, 10, 8, 15, 2, false)
600 MUX_CFG(DA850, MMCSD0_DAT_1, 10, 12, 15, 2, false)
601 MUX_CFG(DA850, MMCSD0_DAT_2, 10, 16, 15, 2, false)
602 MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false)
603 MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false)
604 MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false)
5c4d11b4
IY		 605 /* MMC/SD1 function */
606 MUX_CFG(DA850, MMCSD1_DAT_0, 18, 8, 15, 2, false)
607 MUX_CFG(DA850, MMCSD1_DAT_1, 19, 16, 15, 2, false)
608 MUX_CFG(DA850, MMCSD1_DAT_2, 19, 12, 15, 2, false)
609 MUX_CFG(DA850, MMCSD1_DAT_3, 19, 8, 15, 2, false)
610 MUX_CFG(DA850, MMCSD1_CLK, 18, 12, 15, 2, false)
611 MUX_CFG(DA850, MMCSD1_CMD, 18, 16, 15, 2, false)
38beb929
SR		 612 /* EMIF2.5/EMIFA function */
613 MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false)
614 MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false)
615 MUX_CFG(DA850, EMA_D_5, 9, 8, 15, 1, false)
616 MUX_CFG(DA850, EMA_D_4, 9, 12, 15, 1, false)
617 MUX_CFG(DA850, EMA_D_3, 9, 16, 15, 1, false)
618 MUX_CFG(DA850, EMA_D_2, 9, 20, 15, 1, false)
619 MUX_CFG(DA850, EMA_D_1, 9, 24, 15, 1, false)
620 MUX_CFG(DA850, EMA_D_0, 9, 28, 15, 1, false)
621 MUX_CFG(DA850, EMA_A_1, 12, 24, 15, 1, false)
622 MUX_CFG(DA850, EMA_A_2, 12, 20, 15, 1, false)
623 MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false)
624 MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false)
625 MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false)
626 MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false)
7c5ec609
SR		 627 MUX_CFG(DA850, EMA_A_0, 12, 28, 15, 1, false)
628 MUX_CFG(DA850, EMA_A_3, 12, 16, 15, 1, false)
629 MUX_CFG(DA850, EMA_A_4, 12, 12, 15, 1, false)
630 MUX_CFG(DA850, EMA_A_5, 12, 8, 15, 1, false)
631 MUX_CFG(DA850, EMA_A_6, 12, 4, 15, 1, false)
632 MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false)
633 MUX_CFG(DA850, EMA_A_8, 11, 28, 15, 1, false)
634 MUX_CFG(DA850, EMA_A_9, 11, 24, 15, 1, false)
635 MUX_CFG(DA850, EMA_A_10, 11, 20, 15, 1, false)
636 MUX_CFG(DA850, EMA_A_11, 11, 16, 15, 1, false)
637 MUX_CFG(DA850, EMA_A_12, 11, 12, 15, 1, false)
638 MUX_CFG(DA850, EMA_A_13, 11, 8, 15, 1, false)
639 MUX_CFG(DA850, EMA_A_14, 11, 4, 15, 1, false)
640 MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false)
641 MUX_CFG(DA850, EMA_A_16, 10, 28, 15, 1, false)
642 MUX_CFG(DA850, EMA_A_17, 10, 24, 15, 1, false)
643 MUX_CFG(DA850, EMA_A_18, 10, 20, 15, 1, false)
644 MUX_CFG(DA850, EMA_A_19, 10, 16, 15, 1, false)
645 MUX_CFG(DA850, EMA_A_20, 10, 12, 15, 1, false)
646 MUX_CFG(DA850, EMA_A_21, 10, 8, 15, 1, false)
647 MUX_CFG(DA850, EMA_A_22, 10, 4, 15, 1, false)
648 MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false)
649 MUX_CFG(DA850, EMA_D_8, 8, 28, 15, 1, false)
650 MUX_CFG(DA850, EMA_D_9, 8, 24, 15, 1, false)
651 MUX_CFG(DA850, EMA_D_10, 8, 20, 15, 1, false)
652 MUX_CFG(DA850, EMA_D_11, 8, 16, 15, 1, false)
653 MUX_CFG(DA850, EMA_D_12, 8, 12, 15, 1, false)
654 MUX_CFG(DA850, EMA_D_13, 8, 8, 15, 1, false)
655 MUX_CFG(DA850, EMA_D_14, 8, 4, 15, 1, false)
656 MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false)
657 MUX_CFG(DA850, EMA_BA_1, 5, 24, 15, 1, false)
658 MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false)
659 MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false)
660 MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false)
5cbdf276 661 /* GPIO function */
fe358d6a 662 MUX_CFG(DA850, GPIO2_4, 6, 12, 15, 8, false)
2206771c 663 MUX_CFG(DA850, GPIO2_6, 6, 4, 15, 8, false)
7761ef67 664 MUX_CFG(DA850, GPIO2_8, 5, 28, 15, 8, false)
5cbdf276 665 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false)
fe358d6a
VR		 666 MUX_CFG(DA850, GPIO3_12, 7, 12, 15, 8, false)
667 MUX_CFG(DA850, GPIO3_13, 7, 8, 15, 8, false)
700691f2
SR		 668 MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false)
669 MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false)
6836989c
IY		 670 MUX_CFG(DA850, GPIO6_9, 13, 24, 15, 8, false)
671 MUX_CFG(DA850, GPIO6_10, 13, 20, 15, 8, false)
fe358d6a 672 MUX_CFG(DA850, GPIO6_13, 13, 8, 15, 8, false)
044ca015 673 MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false)
154d54a8
MH		 674 /* VPIF Capture */
675 MUX_CFG(DA850, VPIF_DIN0, 15, 4, 15, 1, false)
676 MUX_CFG(DA850, VPIF_DIN1, 15, 0, 15, 1, false)
677 MUX_CFG(DA850, VPIF_DIN2, 14, 28, 15, 1, false)
678 MUX_CFG(DA850, VPIF_DIN3, 14, 24, 15, 1, false)
679 MUX_CFG(DA850, VPIF_DIN4, 14, 20, 15, 1, false)
680 MUX_CFG(DA850, VPIF_DIN5, 14, 16, 15, 1, false)
681 MUX_CFG(DA850, VPIF_DIN6, 14, 12, 15, 1, false)
682 MUX_CFG(DA850, VPIF_DIN7, 14, 8, 15, 1, false)
683 MUX_CFG(DA850, VPIF_DIN8, 16, 4, 15, 1, false)
684 MUX_CFG(DA850, VPIF_DIN9, 16, 0, 15, 1, false)
685 MUX_CFG(DA850, VPIF_DIN10, 15, 28, 15, 1, false)
686 MUX_CFG(DA850, VPIF_DIN11, 15, 24, 15, 1, false)
687 MUX_CFG(DA850, VPIF_DIN12, 15, 20, 15, 1, false)
688 MUX_CFG(DA850, VPIF_DIN13, 15, 16, 15, 1, false)
689 MUX_CFG(DA850, VPIF_DIN14, 15, 12, 15, 1, false)
690 MUX_CFG(DA850, VPIF_DIN15, 15, 8, 15, 1, false)
691 MUX_CFG(DA850, VPIF_CLKIN0, 14, 0, 15, 1, false)
692 MUX_CFG(DA850, VPIF_CLKIN1, 14, 4, 15, 1, false)
693 MUX_CFG(DA850, VPIF_CLKIN2, 19, 8, 15, 1, false)
694 MUX_CFG(DA850, VPIF_CLKIN3, 19, 16, 15, 1, false)
695 /* VPIF Display */
696 MUX_CFG(DA850, VPIF_DOUT0, 17, 4, 15, 1, false)
697 MUX_CFG(DA850, VPIF_DOUT1, 17, 0, 15, 1, false)
698 MUX_CFG(DA850, VPIF_DOUT2, 16, 28, 15, 1, false)
699 MUX_CFG(DA850, VPIF_DOUT3, 16, 24, 15, 1, false)
700 MUX_CFG(DA850, VPIF_DOUT4, 16, 20, 15, 1, false)
701 MUX_CFG(DA850, VPIF_DOUT5, 16, 16, 15, 1, false)
702 MUX_CFG(DA850, VPIF_DOUT6, 16, 12, 15, 1, false)
703 MUX_CFG(DA850, VPIF_DOUT7, 16, 8, 15, 1, false)
704 MUX_CFG(DA850, VPIF_DOUT8, 18, 4, 15, 1, false)
705 MUX_CFG(DA850, VPIF_DOUT9, 18, 0, 15, 1, false)
706 MUX_CFG(DA850, VPIF_DOUT10, 17, 28, 15, 1, false)
707 MUX_CFG(DA850, VPIF_DOUT11, 17, 24, 15, 1, false)
708 MUX_CFG(DA850, VPIF_DOUT12, 17, 20, 15, 1, false)
709 MUX_CFG(DA850, VPIF_DOUT13, 17, 16, 15, 1, false)
710 MUX_CFG(DA850, VPIF_DOUT14, 17, 12, 15, 1, false)
711 MUX_CFG(DA850, VPIF_DOUT15, 17, 8, 15, 1, false)
712 MUX_CFG(DA850, VPIF_CLKO2, 19, 12, 15, 1, false)
713 MUX_CFG(DA850, VPIF_CLKO3, 19, 20, 15, 1, false)
e1a8d7e2
SR		 714#endif
715};
716
bcad6dc3 717const short da850_i2c0_pins[] __initconst = {
e1a8d7e2
SR		 718 DA850_I2C0_SDA, DA850_I2C0_SCL,
719 -1
720};
721
bcad6dc3 722const short da850_i2c1_pins[] __initconst = {
e1a8d7e2
SR		 723 DA850_I2C1_SCL, DA850_I2C1_SDA,
724 -1
725};
726
bcad6dc3 727const short da850_lcdcntl_pins[] __initconst = {
7761ef67
SR		 728 DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
729 DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
730 DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11,
731 DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15,
732 DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS,
5cbdf276
SR		 733 -1
734};
735
19c233b7 736const short da850_vpif_capture_pins[] __initconst = {
154d54a8
MH		 737 DA850_VPIF_DIN0, DA850_VPIF_DIN1, DA850_VPIF_DIN2, DA850_VPIF_DIN3,
738 DA850_VPIF_DIN4, DA850_VPIF_DIN5, DA850_VPIF_DIN6, DA850_VPIF_DIN7,
739 DA850_VPIF_DIN8, DA850_VPIF_DIN9, DA850_VPIF_DIN10, DA850_VPIF_DIN11,
740 DA850_VPIF_DIN12, DA850_VPIF_DIN13, DA850_VPIF_DIN14, DA850_VPIF_DIN15,
741 DA850_VPIF_CLKIN0, DA850_VPIF_CLKIN1, DA850_VPIF_CLKIN2,
742 DA850_VPIF_CLKIN3,
743 -1
744};
745
19c233b7 746const short da850_vpif_display_pins[] __initconst = {
154d54a8
MH		 747 DA850_VPIF_DOUT0, DA850_VPIF_DOUT1, DA850_VPIF_DOUT2, DA850_VPIF_DOUT3,
748 DA850_VPIF_DOUT4, DA850_VPIF_DOUT5, DA850_VPIF_DOUT6, DA850_VPIF_DOUT7,
749 DA850_VPIF_DOUT8, DA850_VPIF_DOUT9, DA850_VPIF_DOUT10,
750 DA850_VPIF_DOUT11, DA850_VPIF_DOUT12, DA850_VPIF_DOUT13,
751 DA850_VPIF_DOUT14, DA850_VPIF_DOUT15, DA850_VPIF_CLKO2,
752 DA850_VPIF_CLKO3,
753 -1
754};
755
e1a8d7e2
SR		 756/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
757static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
758 [IRQ_DA8XX_COMMTX] = 7,
759 [IRQ_DA8XX_COMMRX] = 7,
760 [IRQ_DA8XX_NINT] = 7,
761 [IRQ_DA8XX_EVTOUT0] = 7,
762 [IRQ_DA8XX_EVTOUT1] = 7,
763 [IRQ_DA8XX_EVTOUT2] = 7,
764 [IRQ_DA8XX_EVTOUT3] = 7,
765 [IRQ_DA8XX_EVTOUT4] = 7,
766 [IRQ_DA8XX_EVTOUT5] = 7,
767 [IRQ_DA8XX_EVTOUT6] = 7,
e1a8d7e2
SR		 768 [IRQ_DA8XX_EVTOUT7] = 7,
769 [IRQ_DA8XX_CCINT0] = 7,
770 [IRQ_DA8XX_CCERRINT] = 7,
771 [IRQ_DA8XX_TCERRINT0] = 7,
772 [IRQ_DA8XX_AEMIFINT] = 7,
773 [IRQ_DA8XX_I2CINT0] = 7,
774 [IRQ_DA8XX_MMCSDINT0] = 7,
775 [IRQ_DA8XX_MMCSDINT1] = 7,
776 [IRQ_DA8XX_ALLINT0] = 7,
777 [IRQ_DA8XX_RTC] = 7,
778 [IRQ_DA8XX_SPINT0] = 7,
779 [IRQ_DA8XX_TINT12_0] = 7,
780 [IRQ_DA8XX_TINT34_0] = 7,
781 [IRQ_DA8XX_TINT12_1] = 7,
782 [IRQ_DA8XX_TINT34_1] = 7,
783 [IRQ_DA8XX_UARTINT0] = 7,
784 [IRQ_DA8XX_KEYMGRINT] = 7,
e1a8d7e2 785 [IRQ_DA850_MPUADDRERR0] = 7,
e1a8d7e2
SR		 786 [IRQ_DA8XX_CHIPINT0] = 7,
787 [IRQ_DA8XX_CHIPINT1] = 7,
788 [IRQ_DA8XX_CHIPINT2] = 7,
789 [IRQ_DA8XX_CHIPINT3] = 7,
790 [IRQ_DA8XX_TCERRINT1] = 7,
791 [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7,
792 [IRQ_DA8XX_C0_RX_PULSE] = 7,
793 [IRQ_DA8XX_C0_TX_PULSE] = 7,
794 [IRQ_DA8XX_C0_MISC_PULSE] = 7,
795 [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7,
796 [IRQ_DA8XX_C1_RX_PULSE] = 7,
797 [IRQ_DA8XX_C1_TX_PULSE] = 7,
798 [IRQ_DA8XX_C1_MISC_PULSE] = 7,
799 [IRQ_DA8XX_MEMERR] = 7,
800 [IRQ_DA8XX_GPIO0] = 7,
801 [IRQ_DA8XX_GPIO1] = 7,
802 [IRQ_DA8XX_GPIO2] = 7,
803 [IRQ_DA8XX_GPIO3] = 7,
804 [IRQ_DA8XX_GPIO4] = 7,
805 [IRQ_DA8XX_GPIO5] = 7,
806 [IRQ_DA8XX_GPIO6] = 7,
807 [IRQ_DA8XX_GPIO7] = 7,
808 [IRQ_DA8XX_GPIO8] = 7,
809 [IRQ_DA8XX_I2CINT1] = 7,
810 [IRQ_DA8XX_LCDINT] = 7,
811 [IRQ_DA8XX_UARTINT1] = 7,
812 [IRQ_DA8XX_MCASPINT] = 7,
813 [IRQ_DA8XX_ALLINT1] = 7,
814 [IRQ_DA8XX_SPINT1] = 7,
815 [IRQ_DA8XX_UHPI_INT1] = 7,
816 [IRQ_DA8XX_USB_INT] = 7,
817 [IRQ_DA8XX_IRQN] = 7,
818 [IRQ_DA8XX_RWAKEUP] = 7,
819 [IRQ_DA8XX_UARTINT2] = 7,
820 [IRQ_DA8XX_DFTSSINT] = 7,
821 [IRQ_DA8XX_EHRPWM0] = 7,
822 [IRQ_DA8XX_EHRPWM0TZ] = 7,
823 [IRQ_DA8XX_EHRPWM1] = 7,
824 [IRQ_DA8XX_EHRPWM1TZ] = 7,
825 [IRQ_DA850_SATAINT] = 7,
e1a8d7e2
SR		 826 [IRQ_DA850_TINTALL_2] = 7,
827 [IRQ_DA8XX_ECAP0] = 7,
828 [IRQ_DA8XX_ECAP1] = 7,
829 [IRQ_DA8XX_ECAP2] = 7,
830 [IRQ_DA850_MMCSDINT0_1] = 7,
831 [IRQ_DA850_MMCSDINT1_1] = 7,
832 [IRQ_DA850_T12CMPINT0_2] = 7,
833 [IRQ_DA850_T12CMPINT1_2] = 7,
834 [IRQ_DA850_T12CMPINT2_2] = 7,
835 [IRQ_DA850_T12CMPINT3_2] = 7,
836 [IRQ_DA850_T12CMPINT4_2] = 7,
837 [IRQ_DA850_T12CMPINT5_2] = 7,
838 [IRQ_DA850_T12CMPINT6_2] = 7,
839 [IRQ_DA850_T12CMPINT7_2] = 7,
840 [IRQ_DA850_T12CMPINT0_3] = 7,
841 [IRQ_DA850_T12CMPINT1_3] = 7,
842 [IRQ_DA850_T12CMPINT2_3] = 7,
843 [IRQ_DA850_T12CMPINT3_3] = 7,
844 [IRQ_DA850_T12CMPINT4_3] = 7,
845 [IRQ_DA850_T12CMPINT5_3] = 7,
846 [IRQ_DA850_T12CMPINT6_3] = 7,
847 [IRQ_DA850_T12CMPINT7_3] = 7,
848 [IRQ_DA850_RPIINT] = 7,
849 [IRQ_DA850_VPIFINT] = 7,
850 [IRQ_DA850_CCINT1] = 7,
851 [IRQ_DA850_CCERRINT1] = 7,
852 [IRQ_DA850_TCERRINT2] = 7,
e1a8d7e2
SR		 853 [IRQ_DA850_TINTALL_3] = 7,
854 [IRQ_DA850_MCBSP0RINT] = 7,
855 [IRQ_DA850_MCBSP0XINT] = 7,
856 [IRQ_DA850_MCBSP1RINT] = 7,
857 [IRQ_DA850_MCBSP1XINT] = 7,
858 [IRQ_DA8XX_ARMCLKSTOPREQ] = 7,
859};
860
861static struct map_desc da850_io_desc[] = {
862 {
863 .virtual = IO_VIRT,
864 .pfn = __phys_to_pfn(IO_PHYS),
865 .length = IO_SIZE,
866 .type = MT_DEVICE
867 },
868 {
869 .virtual = DA8XX_CP_INTC_VIRT,
870 .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE),
871 .length = DA8XX_CP_INTC_SIZE,
872 .type = MT_DEVICE
873 },
874};
875
e4c822c7 876static u32 da850_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE };
e1a8d7e2
SR		 877
878/* Contents of JTAG ID register used to identify exact cpu type */
879static struct davinci_id da850_ids[] = {
880 {
881 .variant = 0x0,
882 .part_no = 0xb7d1,
883 .manufacturer = 0x017, /* 0x02f >> 1 */
884 .cpu_id = DAVINCI_CPU_ID_DA850,
885 .name = "da850/omap-l138",
886 },
cbb691fb
SR		 887 {
888 .variant = 0x1,
889 .part_no = 0xb7d1,
890 .manufacturer = 0x017, /* 0x02f >> 1 */
891 .cpu_id = DAVINCI_CPU_ID_DA850,
892 .name = "da850/omap-l138/am18x",
893 },
e1a8d7e2
SR		 894};
895
896static struct davinci_timer_instance da850_timer_instance[4] = {
897 {
1bcd38ad 898 .base = DA8XX_TIMER64P0_BASE,
e1a8d7e2
SR		 899 .bottom_irq = IRQ_DA8XX_TINT12_0,
900 .top_irq = IRQ_DA8XX_TINT34_0,
901 },
902 {
1bcd38ad 903 .base = DA8XX_TIMER64P1_BASE,
e1a8d7e2
SR		 904 .bottom_irq = IRQ_DA8XX_TINT12_1,
905 .top_irq = IRQ_DA8XX_TINT34_1,
906 },
907 {
1bcd38ad 908 .base = DA850_TIMER64P2_BASE,
e1a8d7e2
SR		 909 .bottom_irq = IRQ_DA850_TINT12_2,
910 .top_irq = IRQ_DA850_TINT34_2,
911 },
912 {
1bcd38ad 913 .base = DA850_TIMER64P3_BASE,
e1a8d7e2
SR		 914 .bottom_irq = IRQ_DA850_TINT12_3,
915 .top_irq = IRQ_DA850_TINT34_3,
916 },
917};
918
919/*
920 * T0_BOT: Timer 0, bottom : Used for clock_event
921 * T0_TOP: Timer 0, top : Used for clocksource
922 * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
923 */
924static struct davinci_timer_info da850_timer_info = {
925 .timers = da850_timer_instance,
926 .clockevent_id = T0_BOT,
927 .clocksource_id = T0_TOP,
928};
929
683b1e1f
SN		 930#ifdef CONFIG_CPU_FREQ
931/*
932 * Notes:
933 * According to the TRM, minimum PLLM results in maximum power savings.
934 * The OPP definitions below should keep the PLLM as low as possible.
935 *
39e14550 936 * The output of the PLLM must be between 300 to 600 MHz.
683b1e1f
SN		 937 */
938struct da850_opp {
939 unsigned int freq; /* in KHz */
940 unsigned int prediv;
941 unsigned int mult;
942 unsigned int postdiv;
35f9acd8
SN		 943 unsigned int cvdd_min; /* in uV */
944 unsigned int cvdd_max; /* in uV */
683b1e1f
SN		 945};
946
39e14550
SN		 947static const struct da850_opp da850_opp_456 = {
948 .freq = 456000,
949 .prediv = 1,
950 .mult = 19,
951 .postdiv = 1,
952 .cvdd_min = 1300000,
953 .cvdd_max = 1350000,
954};
955
956static const struct da850_opp da850_opp_408 = {
957 .freq = 408000,
958 .prediv = 1,
959 .mult = 17,
960 .postdiv = 1,
961 .cvdd_min = 1300000,
962 .cvdd_max = 1350000,
963};
964
965static const struct da850_opp da850_opp_372 = {
966 .freq = 372000,
967 .prediv = 2,
968 .mult = 31,
969 .postdiv = 1,
970 .cvdd_min = 1200000,
971 .cvdd_max = 1320000,
972};
973
683b1e1f
SN		 974static const struct da850_opp da850_opp_300 = {
975 .freq = 300000,
976 .prediv = 1,
977 .mult = 25,
978 .postdiv = 2,
6ef62f82 979 .cvdd_min = 1200000,
35f9acd8 980 .cvdd_max = 1320000,
683b1e1f
SN		 981};
982
983static const struct da850_opp da850_opp_200 = {
984 .freq = 200000,
985 .prediv = 1,
986 .mult = 25,
987 .postdiv = 3,
6ef62f82 988 .cvdd_min = 1100000,
35f9acd8 989 .cvdd_max = 1160000,
683b1e1f
SN		 990};
991
992static const struct da850_opp da850_opp_96 = {
993 .freq = 96000,
994 .prediv = 1,
995 .mult = 20,
996 .postdiv = 5,
6ef62f82 997 .cvdd_min = 1000000,
35f9acd8 998 .cvdd_max = 1050000,
683b1e1f
SN		 999};
1000
1001#define OPP(freq) \
1002 { \
50701588 1003 .driver_data = (unsigned int) &da850_opp_##freq, \
683b1e1f
SN		 1004 .frequency = freq * 1000, \
1005 }
1006
1007static struct cpufreq_frequency_table da850_freq_table[] = {
39e14550
SN		 1008 OPP(456),
1009 OPP(408),
1010 OPP(372),
683b1e1f
SN		 1011 OPP(300),
1012 OPP(200),
1013 OPP(96),
1014 {
50701588 1015 .driver_data = 0,
683b1e1f
SN		 1016 .frequency = CPUFREQ_TABLE_END,
1017 },
1018};
1019
39e14550
SN		 1020#ifdef CONFIG_REGULATOR
1021static int da850_set_voltage(unsigned int index);
1022static int da850_regulator_init(void);
1023#endif
1024
1025static struct davinci_cpufreq_config cpufreq_info = {
1026 .freq_table = da850_freq_table,
1027#ifdef CONFIG_REGULATOR
1028 .init = da850_regulator_init,
1029 .set_voltage = da850_set_voltage,
1030#endif
1031};
1032
13d5e27a
SN		 1033#ifdef CONFIG_REGULATOR
1034static struct regulator *cvdd;
1035
1036static int da850_set_voltage(unsigned int index)
1037{
1038 struct da850_opp *opp;
1039
1040 if (!cvdd)
1041 return -ENODEV;
1042
50701588 1043 opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data;
13d5e27a
SN		 1044
1045 return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
1046}
1047
1048static int da850_regulator_init(void)
1049{
1050 cvdd = regulator_get(NULL, "cvdd");
1051 if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;"
1052 " voltage scaling unsupported\n")) {
1053 return PTR_ERR(cvdd);
1054 }
1055
1056 return 0;
1057}
1058#endif
1059
683b1e1f
SN		 1060static struct platform_device da850_cpufreq_device = {
1061 .name = "cpufreq-davinci",
1062 .dev = {
1063 .platform_data = &cpufreq_info,
1064 },
b987c4b2 1065 .id = -1,
683b1e1f
SN		 1066};
1067
39e14550
SN		 1068unsigned int da850_max_speed = 300000;
1069
5063557a 1070int da850_register_cpufreq(char *async_clk)
683b1e1f 1071{
39e14550
SN		 1072 int i;
1073
b987c4b2
SN		 1074 /* cpufreq driver can help keep an "async" clock constant */
1075 if (async_clk)
1076 clk_add_alias("async", da850_cpufreq_device.name,
1077 async_clk, NULL);
39e14550
SN		 1078 for (i = 0; i < ARRAY_SIZE(da850_freq_table); i++) {
1079 if (da850_freq_table[i].frequency <= da850_max_speed) {
1080 cpufreq_info.freq_table = &da850_freq_table[i];
1081 break;
1082 }
1083 }
b987c4b2 1084
683b1e1f
SN		 1085 return platform_device_register(&da850_cpufreq_device);
1086}
1087
1088static int da850_round_armrate(struct clk *clk, unsigned long rate)
1089{
499f8ad5 1090 int ret = 0, diff;
683b1e1f 1091 unsigned int best = (unsigned int) -1;
39e14550 1092 struct cpufreq_frequency_table *table = cpufreq_info.freq_table;
499f8ad5 1093 struct cpufreq_frequency_table *pos;
683b1e1f
SN		 1094
1095 rate /= 1000; /* convert to kHz */
1096
499f8ad5
SK		 1097 cpufreq_for_each_entry(pos, table) {
1098 diff = pos->frequency - rate;
683b1e1f
SN		 1099 if (diff < 0)
1100 diff = -diff;
1101
1102 if (diff < best) {
1103 best = diff;
499f8ad5 1104 ret = pos->frequency;
683b1e1f
SN		 1105 }
1106 }
1107
1108 return ret * 1000;
1109}
1110
1111static int da850_set_armrate(struct clk *clk, unsigned long index)
1112{
1113 struct clk *pllclk = &pll0_clk;
1114
1115 return clk_set_rate(pllclk, index);
1116}
1117
1118static int da850_set_pll0rate(struct clk *clk, unsigned long index)
1119{
1120 unsigned int prediv, mult, postdiv;
1121 struct da850_opp *opp;
1122 struct pll_data *pll = clk->pll_data;
683b1e1f
SN		 1123 int ret;
1124
50701588 1125 opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data;
683b1e1f
SN		 1126 prediv = opp->prediv;
1127 mult = opp->mult;
1128 postdiv = opp->postdiv;
1129
683b1e1f
SN		 1130 ret = davinci_set_pllrate(pll, prediv, mult, postdiv);
1131 if (WARN_ON(ret))
1132 return ret;
1133
1134 return 0;
1135}
1136#else
fca97b33 1137int __init da850_register_cpufreq(char *async_clk)
683b1e1f
SN		 1138{
1139 return 0;
1140}
1141
1142static int da850_set_armrate(struct clk *clk, unsigned long rate)
1143{
1144 return -EINVAL;
1145}
1146
1147static int da850_set_pll0rate(struct clk *clk, unsigned long armrate)
1148{
1149 return -EINVAL;
1150}
1151
1152static int da850_round_armrate(struct clk *clk, unsigned long rate)
1153{
1154 return clk->rate;
1155}
1156#endif
1157
30c766bd 1158int __init da850_register_pm(struct platform_device *pdev)
044ca015
SN		 1159{
1160 int ret;
1161 struct davinci_pm_config *pdata = pdev->dev.platform_data;
1162
1163 ret = davinci_cfg_reg(DA850_RTC_ALARM);
1164 if (ret)
1165 return ret;
1166
1167 pdata->ddr2_ctlr_base = da8xx_get_mem_ctlr();
1168 pdata->deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG);
1169 pdata->ddrpsc_num = DA8XX_LPSC1_EMIF3C;
1170
1171 pdata->cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K);
1172 if (!pdata->cpupll_reg_base)
1173 return -ENOMEM;
1174
e0c199d0 1175 pdata->ddrpll_reg_base = ioremap(DA850_PLL1_BASE, SZ_4K);
044ca015
SN		 1176 if (!pdata->ddrpll_reg_base) {
1177 ret = -ENOMEM;
1178 goto no_ddrpll_mem;
1179 }
1180
1181 pdata->ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K);
1182 if (!pdata->ddrpsc_reg_base) {
1183 ret = -ENOMEM;
1184 goto no_ddrpsc_mem;
1185 }
1186
1187 return platform_device_register(pdev);
1188
1189no_ddrpsc_mem:
1190 iounmap(pdata->ddrpll_reg_base);
1191no_ddrpll_mem:
1192 iounmap(pdata->cpupll_reg_base);
1193 return ret;
1194}
35f9acd8 1195
154d54a8
MH		 1196/* VPIF resource, platform data */
1197static u64 da850_vpif_dma_mask = DMA_BIT_MASK(32);
1198
1199static struct resource da850_vpif_resource[] = {
1200 {
1201 .start = DA8XX_VPIF_BASE,
1202 .end = DA8XX_VPIF_BASE + 0xfff,
1203 .flags = IORESOURCE_MEM,
1204 }
1205};
1206
1207static struct platform_device da850_vpif_dev = {
1208 .name = "vpif",
1209 .id = -1,
1210 .dev = {
1211 .dma_mask = &da850_vpif_dma_mask,
1212 .coherent_dma_mask = DMA_BIT_MASK(32),
1213 },
1214 .resource = da850_vpif_resource,
1215 .num_resources = ARRAY_SIZE(da850_vpif_resource),
1216};
1217
1218static struct resource da850_vpif_display_resource[] = {
1219 {
1220 .start = IRQ_DA850_VPIFINT,
1221 .end = IRQ_DA850_VPIFINT,
1222 .flags = IORESOURCE_IRQ,
1223 },
1224};
1225
1226static struct platform_device da850_vpif_display_dev = {
1227 .name = "vpif_display",
1228 .id = -1,
1229 .dev = {
1230 .dma_mask = &da850_vpif_dma_mask,
1231 .coherent_dma_mask = DMA_BIT_MASK(32),
1232 },
1233 .resource = da850_vpif_display_resource,
1234 .num_resources = ARRAY_SIZE(da850_vpif_display_resource),
1235};
1236
1237static struct resource da850_vpif_capture_resource[] = {
1238 {
1239 .start = IRQ_DA850_VPIFINT,
1240 .end = IRQ_DA850_VPIFINT,
1241 .flags = IORESOURCE_IRQ,
1242 },
1243 {
1244 .start = IRQ_DA850_VPIFINT,
1245 .end = IRQ_DA850_VPIFINT,
1246 .flags = IORESOURCE_IRQ,
1247 },
1248};
1249
1250static struct platform_device da850_vpif_capture_dev = {
1251 .name = "vpif_capture",
1252 .id = -1,
1253 .dev = {
1254 .dma_mask = &da850_vpif_dma_mask,
1255 .coherent_dma_mask = DMA_BIT_MASK(32),
1256 },
1257 .resource = da850_vpif_capture_resource,
1258 .num_resources = ARRAY_SIZE(da850_vpif_capture_resource),
1259};
1260
1261int __init da850_register_vpif(void)
1262{
1263 return platform_device_register(&da850_vpif_dev);
1264}
1265
1266int __init da850_register_vpif_display(struct vpif_display_config
1267 *display_config)
1268{
1269 da850_vpif_display_dev.dev.platform_data = display_config;
1270 return platform_device_register(&da850_vpif_display_dev);
1271}
1272
1273int __init da850_register_vpif_capture(struct vpif_capture_config
1274 *capture_config)
1275{
1276 da850_vpif_capture_dev.dev.platform_data = capture_config;
1277 return platform_device_register(&da850_vpif_capture_dev);
1278}
1279
f606d38d
KS		 1280static struct davinci_gpio_platform_data da850_gpio_platform_data = {
1281 .ngpio = 144,
f606d38d
KS		 1282};
1283
1284int __init da850_register_gpio(void)
1285{
1286 return da8xx_register_gpio(&da850_gpio_platform_data);
1287}
1288
e1a8d7e2
SR		 1289static struct davinci_soc_info davinci_soc_info_da850 = {
1290 .io_desc = da850_io_desc,
1291 .io_desc_num = ARRAY_SIZE(da850_io_desc),
3347db83 1292 .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
e1a8d7e2
SR		 1293 .ids = da850_ids,
1294 .ids_num = ARRAY_SIZE(da850_ids),
1295 .cpu_clks = da850_clks,
1296 .psc_bases = da850_psc_bases,
1297 .psc_bases_num = ARRAY_SIZE(da850_psc_bases),
779b0d53 1298 .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
e1a8d7e2
SR		 1299 .pinmux_pins = da850_pins,
1300 .pinmux_pins_num = ARRAY_SIZE(da850_pins),
bd808947 1301 .intc_base = DA8XX_CP_INTC_BASE,
e1a8d7e2
SR		 1302 .intc_type = DAVINCI_INTC_TYPE_CP_INTC,
1303 .intc_irq_prios = da850_default_priorities,
1304 .intc_irq_num = DA850_N_CP_INTC_IRQ,
1305 .timer_info = &da850_timer_info,
e1a8d7e2 1306 .emac_pdata = &da8xx_emac_pdata,
c94472d4
SG		 1307 .sram_dma = DA8XX_SHARED_RAM_BASE,
1308 .sram_len = SZ_128K,
e1a8d7e2
SR		 1309};
1310
1311void __init da850_init(void)
1312{
7aad472b
SN		 1313 unsigned int v;
1314
bcd6a1c6
CC		 1315 davinci_common_init(&davinci_soc_info_da850);
1316
d2de0582
SN		 1317 da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
1318 if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
1319 return;
1320
1321 da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K);
1322 if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
6a28adef
SN		 1323 return;
1324
7aad472b
SN		 1325 /* Unlock writing to PLL0 registers */
1326 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1327 v &= ~CFGCHIP0_PLL_MASTER_LOCK;
1328 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1329
1330 /* Unlock writing to PLL1 registers */
1331 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
1332 v &= ~CFGCHIP3_PLL1_MASTER_LOCK;
1333 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
6fc9ebbd
DL		 1334
1335 davinci_clk_init(davinci_soc_info_da850.cpu_clks);
e1a8d7e2 1336}
Linux kernel - Deliverables
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