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ARM: gpio: convert includes of mach/gpio.h and asm/gpio.h to linux/gpio.h
[deliverable/linux.git] / arch / arm / mach-davinci / da850.c
CommitLineData
e1a8d7e2
SR		 1/*
2 * TI DA850/OMAP-L138 chip specific setup
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Derived from: arch/arm/mach-davinci/da830.c
7 * Original Copyrights follow:
8 *
9 * 2009 (c) MontaVista Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
2f8163ba 14#include <linux/gpio.h>
e1a8d7e2
SR		 15#include <linux/init.h>
16#include <linux/clk.h>
17#include <linux/platform_device.h>
683b1e1f 18#include <linux/cpufreq.h>
35f9acd8 19#include <linux/regulator/consumer.h>
e1a8d7e2
SR		 20
21#include <asm/mach/map.h>
22
e1a8d7e2 23#include <mach/psc.h>
e1a8d7e2
SR		 24#include <mach/irqs.h>
25#include <mach/cputype.h>
26#include <mach/common.h>
27#include <mach/time.h>
28#include <mach/da8xx.h>
683b1e1f 29#include <mach/cpufreq.h>
044ca015 30#include <mach/pm.h>
e1a8d7e2
SR		 31
32#include "clock.h"
33#include "mux.h"
34
5d36a332
SN		 35/* SoC specific clock flags */
36#define DA850_CLK_ASYNC3 BIT(16)
37
e1a8d7e2
SR		 38#define DA850_PLL1_BASE 0x01e1a000
39#define DA850_TIMER64P2_BASE 0x01f0c000
40#define DA850_TIMER64P3_BASE 0x01f0d000
41
42#define DA850_REF_FREQ 24000000
43
5d36a332 44#define CFGCHIP3_ASYNC3_CLKSRC BIT(4)
7aad472b 45#define CFGCHIP3_PLL1_MASTER_LOCK BIT(5)
683b1e1f
SN		 46#define CFGCHIP0_PLL_MASTER_LOCK BIT(4)
47
48static int da850_set_armrate(struct clk *clk, unsigned long rate);
49static int da850_round_armrate(struct clk *clk, unsigned long rate);
50static int da850_set_pll0rate(struct clk *clk, unsigned long armrate);
5d36a332 51
e1a8d7e2
SR		 52static struct pll_data pll0_data = {
53 .num = 1,
54 .phys_base = DA8XX_PLL0_BASE,
55 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
56};
57
58static struct clk ref_clk = {
59 .name = "ref_clk",
60 .rate = DA850_REF_FREQ,
8d54297b 61 .set_rate = davinci_simple_set_rate,
e1a8d7e2
SR		 62};
63
64static struct clk pll0_clk = {
65 .name = "pll0",
66 .parent = &ref_clk,
67 .pll_data = &pll0_data,
68 .flags = CLK_PLL,
683b1e1f 69 .set_rate = da850_set_pll0rate,
e1a8d7e2
SR		 70};
71
72static struct clk pll0_aux_clk = {
73 .name = "pll0_aux_clk",
74 .parent = &pll0_clk,
75 .flags = CLK_PLL | PRE_PLL,
76};
77
78static struct clk pll0_sysclk2 = {
79 .name = "pll0_sysclk2",
80 .parent = &pll0_clk,
81 .flags = CLK_PLL,
82 .div_reg = PLLDIV2,
83};
84
85static struct clk pll0_sysclk3 = {
86 .name = "pll0_sysclk3",
87 .parent = &pll0_clk,
88 .flags = CLK_PLL,
89 .div_reg = PLLDIV3,
b987c4b2
SN		 90 .set_rate = davinci_set_sysclk_rate,
91 .maxrate = 100000000,
e1a8d7e2
SR		 92};
93
94static struct clk pll0_sysclk4 = {
95 .name = "pll0_sysclk4",
96 .parent = &pll0_clk,
97 .flags = CLK_PLL,
98 .div_reg = PLLDIV4,
99};
100
101static struct clk pll0_sysclk5 = {
102 .name = "pll0_sysclk5",
103 .parent = &pll0_clk,
104 .flags = CLK_PLL,
105 .div_reg = PLLDIV5,
106};
107
108static struct clk pll0_sysclk6 = {
109 .name = "pll0_sysclk6",
110 .parent = &pll0_clk,
111 .flags = CLK_PLL,
112 .div_reg = PLLDIV6,
113};
114
115static struct clk pll0_sysclk7 = {
116 .name = "pll0_sysclk7",
117 .parent = &pll0_clk,
118 .flags = CLK_PLL,
119 .div_reg = PLLDIV7,
120};
121
122static struct pll_data pll1_data = {
123 .num = 2,
124 .phys_base = DA850_PLL1_BASE,
125 .flags = PLL_HAS_POSTDIV,
126};
127
128static struct clk pll1_clk = {
129 .name = "pll1",
130 .parent = &ref_clk,
131 .pll_data = &pll1_data,
132 .flags = CLK_PLL,
133};
134
135static struct clk pll1_aux_clk = {
136 .name = "pll1_aux_clk",
137 .parent = &pll1_clk,
138 .flags = CLK_PLL | PRE_PLL,
139};
140
141static struct clk pll1_sysclk2 = {
142 .name = "pll1_sysclk2",
143 .parent = &pll1_clk,
144 .flags = CLK_PLL,
145 .div_reg = PLLDIV2,
146};
147
148static struct clk pll1_sysclk3 = {
149 .name = "pll1_sysclk3",
150 .parent = &pll1_clk,
151 .flags = CLK_PLL,
152 .div_reg = PLLDIV3,
153};
154
155static struct clk pll1_sysclk4 = {
156 .name = "pll1_sysclk4",
157 .parent = &pll1_clk,
158 .flags = CLK_PLL,
159 .div_reg = PLLDIV4,
160};
161
162static struct clk pll1_sysclk5 = {
163 .name = "pll1_sysclk5",
164 .parent = &pll1_clk,
165 .flags = CLK_PLL,
166 .div_reg = PLLDIV5,
167};
168
169static struct clk pll1_sysclk6 = {
170 .name = "pll0_sysclk6",
171 .parent = &pll0_clk,
172 .flags = CLK_PLL,
173 .div_reg = PLLDIV6,
174};
175
176static struct clk pll1_sysclk7 = {
177 .name = "pll1_sysclk7",
178 .parent = &pll1_clk,
179 .flags = CLK_PLL,
180 .div_reg = PLLDIV7,
181};
182
183static struct clk i2c0_clk = {
184 .name = "i2c0",
185 .parent = &pll0_aux_clk,
186};
187
188static struct clk timerp64_0_clk = {
189 .name = "timer0",
190 .parent = &pll0_aux_clk,
191};
192
193static struct clk timerp64_1_clk = {
194 .name = "timer1",
195 .parent = &pll0_aux_clk,
196};
197
198static struct clk arm_rom_clk = {
199 .name = "arm_rom",
200 .parent = &pll0_sysclk2,
201 .lpsc = DA8XX_LPSC0_ARM_RAM_ROM,
202 .flags = ALWAYS_ENABLED,
203};
204
205static struct clk tpcc0_clk = {
206 .name = "tpcc0",
207 .parent = &pll0_sysclk2,
208 .lpsc = DA8XX_LPSC0_TPCC,
209 .flags = ALWAYS_ENABLED | CLK_PSC,
210};
211
212static struct clk tptc0_clk = {
213 .name = "tptc0",
214 .parent = &pll0_sysclk2,
215 .lpsc = DA8XX_LPSC0_TPTC0,
216 .flags = ALWAYS_ENABLED,
217};
218
219static struct clk tptc1_clk = {
220 .name = "tptc1",
221 .parent = &pll0_sysclk2,
222 .lpsc = DA8XX_LPSC0_TPTC1,
223 .flags = ALWAYS_ENABLED,
224};
225
226static struct clk tpcc1_clk = {
227 .name = "tpcc1",
228 .parent = &pll0_sysclk2,
229 .lpsc = DA850_LPSC1_TPCC1,
789a785e 230 .gpsc = 1,
e1a8d7e2 231 .flags = CLK_PSC | ALWAYS_ENABLED,
e1a8d7e2
SR		 232};
233
234static struct clk tptc2_clk = {
235 .name = "tptc2",
236 .parent = &pll0_sysclk2,
237 .lpsc = DA850_LPSC1_TPTC2,
789a785e 238 .gpsc = 1,
e1a8d7e2 239 .flags = ALWAYS_ENABLED,
e1a8d7e2
SR		 240};
241
242static struct clk uart0_clk = {
243 .name = "uart0",
244 .parent = &pll0_sysclk2,
245 .lpsc = DA8XX_LPSC0_UART0,
246};
247
248static struct clk uart1_clk = {
249 .name = "uart1",
250 .parent = &pll0_sysclk2,
251 .lpsc = DA8XX_LPSC1_UART1,
789a785e 252 .gpsc = 1,
5d36a332 253 .flags = DA850_CLK_ASYNC3,
e1a8d7e2
SR		 254};
255
256static struct clk uart2_clk = {
257 .name = "uart2",
258 .parent = &pll0_sysclk2,
259 .lpsc = DA8XX_LPSC1_UART2,
789a785e 260 .gpsc = 1,
5d36a332 261 .flags = DA850_CLK_ASYNC3,
e1a8d7e2
SR		 262};
263
264static struct clk aintc_clk = {
265 .name = "aintc",
266 .parent = &pll0_sysclk4,
267 .lpsc = DA8XX_LPSC0_AINTC,
268 .flags = ALWAYS_ENABLED,
269};
270
271static struct clk gpio_clk = {
272 .name = "gpio",
273 .parent = &pll0_sysclk4,
274 .lpsc = DA8XX_LPSC1_GPIO,
789a785e 275 .gpsc = 1,
e1a8d7e2
SR		 276};
277
278static struct clk i2c1_clk = {
279 .name = "i2c1",
280 .parent = &pll0_sysclk4,
281 .lpsc = DA8XX_LPSC1_I2C,
789a785e 282 .gpsc = 1,
e1a8d7e2
SR		 283};
284
285static struct clk emif3_clk = {
286 .name = "emif3",
287 .parent = &pll0_sysclk5,
288 .lpsc = DA8XX_LPSC1_EMIF3C,
789a785e 289 .gpsc = 1,
e1a8d7e2 290 .flags = ALWAYS_ENABLED,
e1a8d7e2
SR		 291};
292
293static struct clk arm_clk = {
294 .name = "arm",
295 .parent = &pll0_sysclk6,
296 .lpsc = DA8XX_LPSC0_ARM,
297 .flags = ALWAYS_ENABLED,
683b1e1f
SN		 298 .set_rate = da850_set_armrate,
299 .round_rate = da850_round_armrate,
e1a8d7e2
SR		 300};
301
302static struct clk rmii_clk = {
303 .name = "rmii",
304 .parent = &pll0_sysclk7,
305};
306
5a4b1315
SR		 307static struct clk emac_clk = {
308 .name = "emac",
309 .parent = &pll0_sysclk4,
310 .lpsc = DA8XX_LPSC1_CPGMAC,
789a785e 311 .gpsc = 1,
5a4b1315
SR		 312};
313
491214e1
C		 314static struct clk mcasp_clk = {
315 .name = "mcasp",
316 .parent = &pll0_sysclk2,
317 .lpsc = DA8XX_LPSC1_McASP0,
789a785e 318 .gpsc = 1,
51157ed8 319 .flags = DA850_CLK_ASYNC3,
491214e1
C		 320};
321
5cbdf276
SR		 322static struct clk lcdc_clk = {
323 .name = "lcdc",
324 .parent = &pll0_sysclk2,
325 .lpsc = DA8XX_LPSC1_LCDC,
789a785e 326 .gpsc = 1,
5cbdf276
SR		 327};
328
051a6687
JK		 329static struct clk mmcsd0_clk = {
330 .name = "mmcsd0",
700691f2
SR		 331 .parent = &pll0_sysclk2,
332 .lpsc = DA8XX_LPSC0_MMC_SD,
333};
334
051a6687
JK		 335static struct clk mmcsd1_clk = {
336 .name = "mmcsd1",
337 .parent = &pll0_sysclk2,
338 .lpsc = DA850_LPSC1_MMC_SD1,
339 .gpsc = 1,
340};
341
38beb929
SR		 342static struct clk aemif_clk = {
343 .name = "aemif",
344 .parent = &pll0_sysclk3,
345 .lpsc = DA8XX_LPSC0_EMIF25,
346 .flags = ALWAYS_ENABLED,
347};
348
5efe330a
VR		 349static struct clk usb11_clk = {
350 .name = "usb11",
351 .parent = &pll0_sysclk4,
352 .lpsc = DA8XX_LPSC1_USB11,
353 .gpsc = 1,
354};
355
356static struct clk usb20_clk = {
357 .name = "usb20",
358 .parent = &pll0_sysclk2,
359 .lpsc = DA8XX_LPSC1_USB20,
360 .gpsc = 1,
361};
362
12d35cf3
MW		 363static struct clk spi0_clk = {
364 .name = "spi0",
365 .parent = &pll0_sysclk2,
366 .lpsc = DA8XX_LPSC0_SPI0,
367};
368
369static struct clk spi1_clk = {
370 .name = "spi1",
371 .parent = &pll0_sysclk2,
372 .lpsc = DA8XX_LPSC1_SPI1,
373 .gpsc = 1,
374 .flags = DA850_CLK_ASYNC3,
375};
376
cbb2c961
SN		 377static struct clk sata_clk = {
378 .name = "sata",
379 .parent = &pll0_sysclk2,
380 .lpsc = DA850_LPSC1_SATA,
381 .gpsc = 1,
382 .flags = PSC_FORCE,
383};
384
08aca087 385static struct clk_lookup da850_clks[] = {
e1a8d7e2
SR		 386 CLK(NULL, "ref", &ref_clk),
387 CLK(NULL, "pll0", &pll0_clk),
388 CLK(NULL, "pll0_aux", &pll0_aux_clk),
389 CLK(NULL, "pll0_sysclk2", &pll0_sysclk2),
390 CLK(NULL, "pll0_sysclk3", &pll0_sysclk3),
391 CLK(NULL, "pll0_sysclk4", &pll0_sysclk4),
392 CLK(NULL, "pll0_sysclk5", &pll0_sysclk5),
393 CLK(NULL, "pll0_sysclk6", &pll0_sysclk6),
394 CLK(NULL, "pll0_sysclk7", &pll0_sysclk7),
395 CLK(NULL, "pll1", &pll1_clk),
396 CLK(NULL, "pll1_aux", &pll1_aux_clk),
397 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
398 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
399 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
400 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
401 CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
402 CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
403 CLK("i2c_davinci.1", NULL, &i2c0_clk),
404 CLK(NULL, "timer0", &timerp64_0_clk),
405 CLK("watchdog", NULL, &timerp64_1_clk),
406 CLK(NULL, "arm_rom", &arm_rom_clk),
407 CLK(NULL, "tpcc0", &tpcc0_clk),
408 CLK(NULL, "tptc0", &tptc0_clk),
409 CLK(NULL, "tptc1", &tptc1_clk),
410 CLK(NULL, "tpcc1", &tpcc1_clk),
411 CLK(NULL, "tptc2", &tptc2_clk),
412 CLK(NULL, "uart0", &uart0_clk),
413 CLK(NULL, "uart1", &uart1_clk),
414 CLK(NULL, "uart2", &uart2_clk),
415 CLK(NULL, "aintc", &aintc_clk),
416 CLK(NULL, "gpio", &gpio_clk),
417 CLK("i2c_davinci.2", NULL, &i2c1_clk),
418 CLK(NULL, "emif3", &emif3_clk),
419 CLK(NULL, "arm", &arm_clk),
420 CLK(NULL, "rmii", &rmii_clk),
5a4b1315 421 CLK("davinci_emac.1", NULL, &emac_clk),
491214e1 422 CLK("davinci-mcasp.0", NULL, &mcasp_clk),
5cbdf276 423 CLK("da8xx_lcdc.0", NULL, &lcdc_clk),
051a6687
JK		 424 CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
425 CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
38beb929 426 CLK(NULL, "aemif", &aemif_clk),
5efe330a
VR		 427 CLK(NULL, "usb11", &usb11_clk),
428 CLK(NULL, "usb20", &usb20_clk),
12d35cf3
MW		 429 CLK("spi_davinci.0", NULL, &spi0_clk),
430 CLK("spi_davinci.1", NULL, &spi1_clk),
cbb2c961 431 CLK("ahci", NULL, &sata_clk),
e1a8d7e2
SR		 432 CLK(NULL, NULL, NULL),
433};
434
435/*
436 * Device specific mux setup
437 *
438 * soc description mux mode mode mux dbg
439 * reg offset mask mode
440 */
441static const struct mux_config da850_pins[] = {
442#ifdef CONFIG_DAVINCI_MUX
443 /* UART0 function */
444 MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false)
445 MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false)
446 MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false)
447 MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false)
448 /* UART1 function */
449 MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false)
450 MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false)
451 /* UART2 function */
452 MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false)
453 MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false)
454 /* I2C1 function */
455 MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false)
456 MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false)
457 /* I2C0 function */
458 MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false)
459 MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false)
5a4b1315
SR		 460 /* EMAC function */
461 MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false)
462 MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false)
463 MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false)
464 MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false)
465 MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false)
466 MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false)
467 MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false)
468 MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false)
469 MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false)
470 MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false)
471 MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false)
472 MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false)
473 MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false)
474 MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false)
475 MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false)
53ca5c91
SR		 476 MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false)
477 MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false)
2206771c
C		 478 MUX_CFG(DA850, RMII_TXD_0, 14, 12, 15, 8, false)
479 MUX_CFG(DA850, RMII_TXD_1, 14, 8, 15, 8, false)
480 MUX_CFG(DA850, RMII_TXEN, 14, 16, 15, 8, false)
481 MUX_CFG(DA850, RMII_CRS_DV, 15, 4, 15, 8, false)
482 MUX_CFG(DA850, RMII_RXD_0, 14, 24, 15, 8, false)
483 MUX_CFG(DA850, RMII_RXD_1, 14, 20, 15, 8, false)
484 MUX_CFG(DA850, RMII_RXER, 14, 28, 15, 8, false)
485 MUX_CFG(DA850, RMII_MHZ_50_CLK, 15, 0, 15, 0, false)
491214e1
C		 486 /* McASP function */
487 MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false)
488 MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false)
489 MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false)
490 MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false)
491 MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false)
492 MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false)
493 MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false)
494 MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false)
495 MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false)
496 MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false)
497 MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false)
498 MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false)
499 MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false)
500 MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false)
501 MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false)
502 MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false)
503 MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false)
504 MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false)
505 MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false)
506 MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false)
507 MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false)
508 MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false)
509 MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false)
5cbdf276
SR		 510 /* LCD function */
511 MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false)
512 MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false)
513 MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false)
514 MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false)
515 MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false)
516 MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false)
517 MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false)
518 MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false)
519 MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false)
520 MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false)
521 MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false)
522 MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false)
523 MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false)
524 MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false)
525 MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false)
526 MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false)
527 MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false)
528 MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false)
529 MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false)
530 MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false)
700691f2
SR		 531 /* MMC/SD0 function */
532 MUX_CFG(DA850, MMCSD0_DAT_0, 10, 8, 15, 2, false)
533 MUX_CFG(DA850, MMCSD0_DAT_1, 10, 12, 15, 2, false)
534 MUX_CFG(DA850, MMCSD0_DAT_2, 10, 16, 15, 2, false)
535 MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false)
536 MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false)
537 MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false)
38beb929
SR		 538 /* EMIF2.5/EMIFA function */
539 MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false)
540 MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false)
541 MUX_CFG(DA850, EMA_D_5, 9, 8, 15, 1, false)
542 MUX_CFG(DA850, EMA_D_4, 9, 12, 15, 1, false)
543 MUX_CFG(DA850, EMA_D_3, 9, 16, 15, 1, false)
544 MUX_CFG(DA850, EMA_D_2, 9, 20, 15, 1, false)
545 MUX_CFG(DA850, EMA_D_1, 9, 24, 15, 1, false)
546 MUX_CFG(DA850, EMA_D_0, 9, 28, 15, 1, false)
547 MUX_CFG(DA850, EMA_A_1, 12, 24, 15, 1, false)
548 MUX_CFG(DA850, EMA_A_2, 12, 20, 15, 1, false)
549 MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false)
550 MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false)
551 MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false)
552 MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false)
7c5ec609
SR		 553 MUX_CFG(DA850, EMA_A_0, 12, 28, 15, 1, false)
554 MUX_CFG(DA850, EMA_A_3, 12, 16, 15, 1, false)
555 MUX_CFG(DA850, EMA_A_4, 12, 12, 15, 1, false)
556 MUX_CFG(DA850, EMA_A_5, 12, 8, 15, 1, false)
557 MUX_CFG(DA850, EMA_A_6, 12, 4, 15, 1, false)
558 MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false)
559 MUX_CFG(DA850, EMA_A_8, 11, 28, 15, 1, false)
560 MUX_CFG(DA850, EMA_A_9, 11, 24, 15, 1, false)
561 MUX_CFG(DA850, EMA_A_10, 11, 20, 15, 1, false)
562 MUX_CFG(DA850, EMA_A_11, 11, 16, 15, 1, false)
563 MUX_CFG(DA850, EMA_A_12, 11, 12, 15, 1, false)
564 MUX_CFG(DA850, EMA_A_13, 11, 8, 15, 1, false)
565 MUX_CFG(DA850, EMA_A_14, 11, 4, 15, 1, false)
566 MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false)
567 MUX_CFG(DA850, EMA_A_16, 10, 28, 15, 1, false)
568 MUX_CFG(DA850, EMA_A_17, 10, 24, 15, 1, false)
569 MUX_CFG(DA850, EMA_A_18, 10, 20, 15, 1, false)
570 MUX_CFG(DA850, EMA_A_19, 10, 16, 15, 1, false)
571 MUX_CFG(DA850, EMA_A_20, 10, 12, 15, 1, false)
572 MUX_CFG(DA850, EMA_A_21, 10, 8, 15, 1, false)
573 MUX_CFG(DA850, EMA_A_22, 10, 4, 15, 1, false)
574 MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false)
575 MUX_CFG(DA850, EMA_D_8, 8, 28, 15, 1, false)
576 MUX_CFG(DA850, EMA_D_9, 8, 24, 15, 1, false)
577 MUX_CFG(DA850, EMA_D_10, 8, 20, 15, 1, false)
578 MUX_CFG(DA850, EMA_D_11, 8, 16, 15, 1, false)
579 MUX_CFG(DA850, EMA_D_12, 8, 12, 15, 1, false)
580 MUX_CFG(DA850, EMA_D_13, 8, 8, 15, 1, false)
581 MUX_CFG(DA850, EMA_D_14, 8, 4, 15, 1, false)
582 MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false)
583 MUX_CFG(DA850, EMA_BA_1, 5, 24, 15, 1, false)
584 MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false)
585 MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false)
586 MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false)
5cbdf276 587 /* GPIO function */
fe358d6a 588 MUX_CFG(DA850, GPIO2_4, 6, 12, 15, 8, false)
2206771c 589 MUX_CFG(DA850, GPIO2_6, 6, 4, 15, 8, false)
7761ef67 590 MUX_CFG(DA850, GPIO2_8, 5, 28, 15, 8, false)
5cbdf276 591 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false)
fe358d6a
VR		 592 MUX_CFG(DA850, GPIO3_12, 7, 12, 15, 8, false)
593 MUX_CFG(DA850, GPIO3_13, 7, 8, 15, 8, false)
700691f2
SR		 594 MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false)
595 MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false)
fe358d6a 596 MUX_CFG(DA850, GPIO6_13, 13, 8, 15, 8, false)
044ca015 597 MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false)
e1a8d7e2
SR		 598#endif
599};
600
e1a8d7e2
SR		 601const short da850_i2c0_pins[] __initdata = {
602 DA850_I2C0_SDA, DA850_I2C0_SCL,
603 -1
604};
605
606const short da850_i2c1_pins[] __initdata = {
607 DA850_I2C1_SCL, DA850_I2C1_SDA,
608 -1
609};
610
5cbdf276 611const short da850_lcdcntl_pins[] __initdata = {
7761ef67
SR		 612 DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
613 DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
614 DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11,
615 DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15,
616 DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS,
5cbdf276
SR		 617 -1
618};
619
e1a8d7e2
SR		 620/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
621static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
622 [IRQ_DA8XX_COMMTX] = 7,
623 [IRQ_DA8XX_COMMRX] = 7,
624 [IRQ_DA8XX_NINT] = 7,
625 [IRQ_DA8XX_EVTOUT0] = 7,
626 [IRQ_DA8XX_EVTOUT1] = 7,
627 [IRQ_DA8XX_EVTOUT2] = 7,
628 [IRQ_DA8XX_EVTOUT3] = 7,
629 [IRQ_DA8XX_EVTOUT4] = 7,
630 [IRQ_DA8XX_EVTOUT5] = 7,
631 [IRQ_DA8XX_EVTOUT6] = 7,
e1a8d7e2
SR		 632 [IRQ_DA8XX_EVTOUT7] = 7,
633 [IRQ_DA8XX_CCINT0] = 7,
634 [IRQ_DA8XX_CCERRINT] = 7,
635 [IRQ_DA8XX_TCERRINT0] = 7,
636 [IRQ_DA8XX_AEMIFINT] = 7,
637 [IRQ_DA8XX_I2CINT0] = 7,
638 [IRQ_DA8XX_MMCSDINT0] = 7,
639 [IRQ_DA8XX_MMCSDINT1] = 7,
640 [IRQ_DA8XX_ALLINT0] = 7,
641 [IRQ_DA8XX_RTC] = 7,
642 [IRQ_DA8XX_SPINT0] = 7,
643 [IRQ_DA8XX_TINT12_0] = 7,
644 [IRQ_DA8XX_TINT34_0] = 7,
645 [IRQ_DA8XX_TINT12_1] = 7,
646 [IRQ_DA8XX_TINT34_1] = 7,
647 [IRQ_DA8XX_UARTINT0] = 7,
648 [IRQ_DA8XX_KEYMGRINT] = 7,
e1a8d7e2 649 [IRQ_DA850_MPUADDRERR0] = 7,
e1a8d7e2
SR		 650 [IRQ_DA8XX_CHIPINT0] = 7,
651 [IRQ_DA8XX_CHIPINT1] = 7,
652 [IRQ_DA8XX_CHIPINT2] = 7,
653 [IRQ_DA8XX_CHIPINT3] = 7,
654 [IRQ_DA8XX_TCERRINT1] = 7,
655 [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7,
656 [IRQ_DA8XX_C0_RX_PULSE] = 7,
657 [IRQ_DA8XX_C0_TX_PULSE] = 7,
658 [IRQ_DA8XX_C0_MISC_PULSE] = 7,
659 [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7,
660 [IRQ_DA8XX_C1_RX_PULSE] = 7,
661 [IRQ_DA8XX_C1_TX_PULSE] = 7,
662 [IRQ_DA8XX_C1_MISC_PULSE] = 7,
663 [IRQ_DA8XX_MEMERR] = 7,
664 [IRQ_DA8XX_GPIO0] = 7,
665 [IRQ_DA8XX_GPIO1] = 7,
666 [IRQ_DA8XX_GPIO2] = 7,
667 [IRQ_DA8XX_GPIO3] = 7,
668 [IRQ_DA8XX_GPIO4] = 7,
669 [IRQ_DA8XX_GPIO5] = 7,
670 [IRQ_DA8XX_GPIO6] = 7,
671 [IRQ_DA8XX_GPIO7] = 7,
672 [IRQ_DA8XX_GPIO8] = 7,
673 [IRQ_DA8XX_I2CINT1] = 7,
674 [IRQ_DA8XX_LCDINT] = 7,
675 [IRQ_DA8XX_UARTINT1] = 7,
676 [IRQ_DA8XX_MCASPINT] = 7,
677 [IRQ_DA8XX_ALLINT1] = 7,
678 [IRQ_DA8XX_SPINT1] = 7,
679 [IRQ_DA8XX_UHPI_INT1] = 7,
680 [IRQ_DA8XX_USB_INT] = 7,
681 [IRQ_DA8XX_IRQN] = 7,
682 [IRQ_DA8XX_RWAKEUP] = 7,
683 [IRQ_DA8XX_UARTINT2] = 7,
684 [IRQ_DA8XX_DFTSSINT] = 7,
685 [IRQ_DA8XX_EHRPWM0] = 7,
686 [IRQ_DA8XX_EHRPWM0TZ] = 7,
687 [IRQ_DA8XX_EHRPWM1] = 7,
688 [IRQ_DA8XX_EHRPWM1TZ] = 7,
689 [IRQ_DA850_SATAINT] = 7,
e1a8d7e2
SR		 690 [IRQ_DA850_TINTALL_2] = 7,
691 [IRQ_DA8XX_ECAP0] = 7,
692 [IRQ_DA8XX_ECAP1] = 7,
693 [IRQ_DA8XX_ECAP2] = 7,
694 [IRQ_DA850_MMCSDINT0_1] = 7,
695 [IRQ_DA850_MMCSDINT1_1] = 7,
696 [IRQ_DA850_T12CMPINT0_2] = 7,
697 [IRQ_DA850_T12CMPINT1_2] = 7,
698 [IRQ_DA850_T12CMPINT2_2] = 7,
699 [IRQ_DA850_T12CMPINT3_2] = 7,
700 [IRQ_DA850_T12CMPINT4_2] = 7,
701 [IRQ_DA850_T12CMPINT5_2] = 7,
702 [IRQ_DA850_T12CMPINT6_2] = 7,
703 [IRQ_DA850_T12CMPINT7_2] = 7,
704 [IRQ_DA850_T12CMPINT0_3] = 7,
705 [IRQ_DA850_T12CMPINT1_3] = 7,
706 [IRQ_DA850_T12CMPINT2_3] = 7,
707 [IRQ_DA850_T12CMPINT3_3] = 7,
708 [IRQ_DA850_T12CMPINT4_3] = 7,
709 [IRQ_DA850_T12CMPINT5_3] = 7,
710 [IRQ_DA850_T12CMPINT6_3] = 7,
711 [IRQ_DA850_T12CMPINT7_3] = 7,
712 [IRQ_DA850_RPIINT] = 7,
713 [IRQ_DA850_VPIFINT] = 7,
714 [IRQ_DA850_CCINT1] = 7,
715 [IRQ_DA850_CCERRINT1] = 7,
716 [IRQ_DA850_TCERRINT2] = 7,
e1a8d7e2
SR		 717 [IRQ_DA850_TINTALL_3] = 7,
718 [IRQ_DA850_MCBSP0RINT] = 7,
719 [IRQ_DA850_MCBSP0XINT] = 7,
720 [IRQ_DA850_MCBSP1RINT] = 7,
721 [IRQ_DA850_MCBSP1XINT] = 7,
722 [IRQ_DA8XX_ARMCLKSTOPREQ] = 7,
723};
724
725static struct map_desc da850_io_desc[] = {
726 {
727 .virtual = IO_VIRT,
728 .pfn = __phys_to_pfn(IO_PHYS),
729 .length = IO_SIZE,
730 .type = MT_DEVICE
731 },
732 {
733 .virtual = DA8XX_CP_INTC_VIRT,
734 .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE),
735 .length = DA8XX_CP_INTC_SIZE,
736 .type = MT_DEVICE
737 },
60cd02e1
SN		 738 {
739 .virtual = SRAM_VIRT,
740 .pfn = __phys_to_pfn(DA8XX_ARM_RAM_BASE),
741 .length = SZ_8K,
742 .type = MT_DEVICE
743 },
e1a8d7e2
SR		 744};
745
e4c822c7 746static u32 da850_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE };
e1a8d7e2
SR		 747
748/* Contents of JTAG ID register used to identify exact cpu type */
749static struct davinci_id da850_ids[] = {
750 {
751 .variant = 0x0,
752 .part_no = 0xb7d1,
753 .manufacturer = 0x017, /* 0x02f >> 1 */
754 .cpu_id = DAVINCI_CPU_ID_DA850,
755 .name = "da850/omap-l138",
756 },
cbb691fb
SR		 757 {
758 .variant = 0x1,
759 .part_no = 0xb7d1,
760 .manufacturer = 0x017, /* 0x02f >> 1 */
761 .cpu_id = DAVINCI_CPU_ID_DA850,
762 .name = "da850/omap-l138/am18x",
763 },
e1a8d7e2
SR		 764};
765
766static struct davinci_timer_instance da850_timer_instance[4] = {
767 {
1bcd38ad 768 .base = DA8XX_TIMER64P0_BASE,
e1a8d7e2
SR		 769 .bottom_irq = IRQ_DA8XX_TINT12_0,
770 .top_irq = IRQ_DA8XX_TINT34_0,
771 },
772 {
1bcd38ad 773 .base = DA8XX_TIMER64P1_BASE,
e1a8d7e2
SR		 774 .bottom_irq = IRQ_DA8XX_TINT12_1,
775 .top_irq = IRQ_DA8XX_TINT34_1,
776 },
777 {
1bcd38ad 778 .base = DA850_TIMER64P2_BASE,
e1a8d7e2
SR		 779 .bottom_irq = IRQ_DA850_TINT12_2,
780 .top_irq = IRQ_DA850_TINT34_2,
781 },
782 {
1bcd38ad 783 .base = DA850_TIMER64P3_BASE,
e1a8d7e2
SR		 784 .bottom_irq = IRQ_DA850_TINT12_3,
785 .top_irq = IRQ_DA850_TINT34_3,
786 },
787};
788
789/*
790 * T0_BOT: Timer 0, bottom : Used for clock_event
791 * T0_TOP: Timer 0, top : Used for clocksource
792 * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
793 */
794static struct davinci_timer_info da850_timer_info = {
795 .timers = da850_timer_instance,
796 .clockevent_id = T0_BOT,
797 .clocksource_id = T0_TOP,
798};
799
5d36a332
SN		 800static void da850_set_async3_src(int pllnum)
801{
802 struct clk *clk, *newparent = pllnum ? &pll1_sysclk2 : &pll0_sysclk2;
08aca087 803 struct clk_lookup *c;
5d36a332
SN		 804 unsigned int v;
805 int ret;
806
08aca087
KH		 807 for (c = da850_clks; c->clk; c++) {
808 clk = c->clk;
5d36a332
SN		 809 if (clk->flags & DA850_CLK_ASYNC3) {
810 ret = clk_set_parent(clk, newparent);
811 WARN(ret, "DA850: unable to re-parent clock %s",
812 clk->name);
813 }
814 }
815
d2de0582 816 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
5d36a332
SN		 817 if (pllnum)
818 v |= CFGCHIP3_ASYNC3_CLKSRC;
819 else
820 v &= ~CFGCHIP3_ASYNC3_CLKSRC;
d2de0582 821 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
5d36a332
SN		 822}
823
683b1e1f
SN		 824#ifdef CONFIG_CPU_FREQ
825/*
826 * Notes:
827 * According to the TRM, minimum PLLM results in maximum power savings.
828 * The OPP definitions below should keep the PLLM as low as possible.
829 *
39e14550 830 * The output of the PLLM must be between 300 to 600 MHz.
683b1e1f
SN		 831 */
832struct da850_opp {
833 unsigned int freq; /* in KHz */
834 unsigned int prediv;
835 unsigned int mult;
836 unsigned int postdiv;
35f9acd8
SN		 837 unsigned int cvdd_min; /* in uV */
838 unsigned int cvdd_max; /* in uV */
683b1e1f
SN		 839};
840
39e14550
SN		 841static const struct da850_opp da850_opp_456 = {
842 .freq = 456000,
843 .prediv = 1,
844 .mult = 19,
845 .postdiv = 1,
846 .cvdd_min = 1300000,
847 .cvdd_max = 1350000,
848};
849
850static const struct da850_opp da850_opp_408 = {
851 .freq = 408000,
852 .prediv = 1,
853 .mult = 17,
854 .postdiv = 1,
855 .cvdd_min = 1300000,
856 .cvdd_max = 1350000,
857};
858
859static const struct da850_opp da850_opp_372 = {
860 .freq = 372000,
861 .prediv = 2,
862 .mult = 31,
863 .postdiv = 1,
864 .cvdd_min = 1200000,
865 .cvdd_max = 1320000,
866};
867
683b1e1f
SN		 868static const struct da850_opp da850_opp_300 = {
869 .freq = 300000,
870 .prediv = 1,
871 .mult = 25,
872 .postdiv = 2,
6ef62f82 873 .cvdd_min = 1200000,
35f9acd8 874 .cvdd_max = 1320000,
683b1e1f
SN		 875};
876
877static const struct da850_opp da850_opp_200 = {
878 .freq = 200000,
879 .prediv = 1,
880 .mult = 25,
881 .postdiv = 3,
6ef62f82 882 .cvdd_min = 1100000,
35f9acd8 883 .cvdd_max = 1160000,
683b1e1f
SN		 884};
885
886static const struct da850_opp da850_opp_96 = {
887 .freq = 96000,
888 .prediv = 1,
889 .mult = 20,
890 .postdiv = 5,
6ef62f82 891 .cvdd_min = 1000000,
35f9acd8 892 .cvdd_max = 1050000,
683b1e1f
SN		 893};
894
895#define OPP(freq) \
896 { \
897 .index = (unsigned int) &da850_opp_##freq, \
898 .frequency = freq * 1000, \
899 }
900
901static struct cpufreq_frequency_table da850_freq_table[] = {
39e14550
SN		 902 OPP(456),
903 OPP(408),
904 OPP(372),
683b1e1f
SN		 905 OPP(300),
906 OPP(200),
907 OPP(96),
908 {
909 .index = 0,
910 .frequency = CPUFREQ_TABLE_END,
911 },
912};
913
39e14550
SN		 914#ifdef CONFIG_REGULATOR
915static int da850_set_voltage(unsigned int index);
916static int da850_regulator_init(void);
917#endif
918
919static struct davinci_cpufreq_config cpufreq_info = {
920 .freq_table = da850_freq_table,
921#ifdef CONFIG_REGULATOR
922 .init = da850_regulator_init,
923 .set_voltage = da850_set_voltage,
924#endif
925};
926
13d5e27a
SN		 927#ifdef CONFIG_REGULATOR
928static struct regulator *cvdd;
929
930static int da850_set_voltage(unsigned int index)
931{
932 struct da850_opp *opp;
933
934 if (!cvdd)
935 return -ENODEV;
936
39e14550 937 opp = (struct da850_opp *) cpufreq_info.freq_table[index].index;
13d5e27a
SN		 938
939 return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
940}
941
942static int da850_regulator_init(void)
943{
944 cvdd = regulator_get(NULL, "cvdd");
945 if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;"
946 " voltage scaling unsupported\n")) {
947 return PTR_ERR(cvdd);
948 }
949
950 return 0;
951}
952#endif
953
683b1e1f
SN		 954static struct platform_device da850_cpufreq_device = {
955 .name = "cpufreq-davinci",
956 .dev = {
957 .platform_data = &cpufreq_info,
958 },
b987c4b2 959 .id = -1,
683b1e1f
SN		 960};
961
39e14550
SN		 962unsigned int da850_max_speed = 300000;
963
b987c4b2 964int __init da850_register_cpufreq(char *async_clk)
683b1e1f 965{
39e14550
SN		 966 int i;
967
b987c4b2
SN		 968 /* cpufreq driver can help keep an "async" clock constant */
969 if (async_clk)
970 clk_add_alias("async", da850_cpufreq_device.name,
971 async_clk, NULL);
39e14550
SN		 972 for (i = 0; i < ARRAY_SIZE(da850_freq_table); i++) {
973 if (da850_freq_table[i].frequency <= da850_max_speed) {
974 cpufreq_info.freq_table = &da850_freq_table[i];
975 break;
976 }
977 }
b987c4b2 978
683b1e1f
SN		 979 return platform_device_register(&da850_cpufreq_device);
980}
981
982static int da850_round_armrate(struct clk *clk, unsigned long rate)
983{
984 int i, ret = 0, diff;
985 unsigned int best = (unsigned int) -1;
39e14550 986 struct cpufreq_frequency_table *table = cpufreq_info.freq_table;
683b1e1f
SN		 987
988 rate /= 1000; /* convert to kHz */
989
39e14550
SN		 990 for (i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++) {
991 diff = table[i].frequency - rate;
683b1e1f
SN		 992 if (diff < 0)
993 diff = -diff;
994
995 if (diff < best) {
996 best = diff;
39e14550 997 ret = table[i].frequency;
683b1e1f
SN		 998 }
999 }
1000
1001 return ret * 1000;
1002}
1003
1004static int da850_set_armrate(struct clk *clk, unsigned long index)
1005{
1006 struct clk *pllclk = &pll0_clk;
1007
1008 return clk_set_rate(pllclk, index);
1009}
1010
1011static int da850_set_pll0rate(struct clk *clk, unsigned long index)
1012{
1013 unsigned int prediv, mult, postdiv;
1014 struct da850_opp *opp;
1015 struct pll_data *pll = clk->pll_data;
683b1e1f
SN		 1016 int ret;
1017
39e14550 1018 opp = (struct da850_opp *) cpufreq_info.freq_table[index].index;
683b1e1f
SN		 1019 prediv = opp->prediv;
1020 mult = opp->mult;
1021 postdiv = opp->postdiv;
1022
683b1e1f
SN		 1023 ret = davinci_set_pllrate(pll, prediv, mult, postdiv);
1024 if (WARN_ON(ret))
1025 return ret;
1026
1027 return 0;
1028}
1029#else
fca97b33 1030int __init da850_register_cpufreq(char *async_clk)
683b1e1f
SN		 1031{
1032 return 0;
1033}
1034
1035static int da850_set_armrate(struct clk *clk, unsigned long rate)
1036{
1037 return -EINVAL;
1038}
1039
1040static int da850_set_pll0rate(struct clk *clk, unsigned long armrate)
1041{
1042 return -EINVAL;
1043}
1044
1045static int da850_round_armrate(struct clk *clk, unsigned long rate)
1046{
1047 return clk->rate;
1048}
1049#endif
1050
044ca015
SN		 1051int da850_register_pm(struct platform_device *pdev)
1052{
1053 int ret;
1054 struct davinci_pm_config *pdata = pdev->dev.platform_data;
1055
1056 ret = davinci_cfg_reg(DA850_RTC_ALARM);
1057 if (ret)
1058 return ret;
1059
1060 pdata->ddr2_ctlr_base = da8xx_get_mem_ctlr();
1061 pdata->deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG);
1062 pdata->ddrpsc_num = DA8XX_LPSC1_EMIF3C;
1063
1064 pdata->cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K);
1065 if (!pdata->cpupll_reg_base)
1066 return -ENOMEM;
1067
e0c199d0 1068 pdata->ddrpll_reg_base = ioremap(DA850_PLL1_BASE, SZ_4K);
044ca015
SN		 1069 if (!pdata->ddrpll_reg_base) {
1070 ret = -ENOMEM;
1071 goto no_ddrpll_mem;
1072 }
1073
1074 pdata->ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K);
1075 if (!pdata->ddrpsc_reg_base) {
1076 ret = -ENOMEM;
1077 goto no_ddrpsc_mem;
1078 }
1079
1080 return platform_device_register(pdev);
1081
1082no_ddrpsc_mem:
1083 iounmap(pdata->ddrpll_reg_base);
1084no_ddrpll_mem:
1085 iounmap(pdata->cpupll_reg_base);
1086 return ret;
1087}
35f9acd8 1088
e1a8d7e2
SR		 1089static struct davinci_soc_info davinci_soc_info_da850 = {
1090 .io_desc = da850_io_desc,
1091 .io_desc_num = ARRAY_SIZE(da850_io_desc),
3347db83 1092 .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
e1a8d7e2
SR		 1093 .ids = da850_ids,
1094 .ids_num = ARRAY_SIZE(da850_ids),
1095 .cpu_clks = da850_clks,
1096 .psc_bases = da850_psc_bases,
1097 .psc_bases_num = ARRAY_SIZE(da850_psc_bases),
779b0d53 1098 .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
e1a8d7e2
SR		 1099 .pinmux_pins = da850_pins,
1100 .pinmux_pins_num = ARRAY_SIZE(da850_pins),
bd808947 1101 .intc_base = DA8XX_CP_INTC_BASE,
e1a8d7e2
SR		 1102 .intc_type = DAVINCI_INTC_TYPE_CP_INTC,
1103 .intc_irq_prios = da850_default_priorities,
1104 .intc_irq_num = DA850_N_CP_INTC_IRQ,
1105 .timer_info = &da850_timer_info,
686b634a 1106 .gpio_type = GPIO_TYPE_DAVINCI,
b8d44293 1107 .gpio_base = DA8XX_GPIO_BASE,
5a8d5441 1108 .gpio_num = 144,
e1a8d7e2
SR		 1109 .gpio_irq = IRQ_DA8XX_GPIO0,
1110 .serial_dev = &da8xx_serial_device,
1111 .emac_pdata = &da8xx_emac_pdata,
60cd02e1
SN		 1112 .sram_dma = DA8XX_ARM_RAM_BASE,
1113 .sram_len = SZ_8K,
c78a5bc2 1114 .reset_device = &da8xx_wdt_device,
e1a8d7e2
SR		 1115};
1116
1117void __init da850_init(void)
1118{
7aad472b
SN		 1119 unsigned int v;
1120
bcd6a1c6
CC		 1121 davinci_common_init(&davinci_soc_info_da850);
1122
d2de0582
SN		 1123 da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
1124 if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
1125 return;
1126
1127 da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K);
1128 if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
6a28adef
SN		 1129 return;
1130
5d36a332
SN		 1131 /*
1132 * Move the clock source of Async3 domain to PLL1 SYSCLK2.
1133 * This helps keeping the peripherals on this domain insulated
1134 * from CPU frequency changes caused by DVFS. The firmware sets
1135 * both PLL0 and PLL1 to the same frequency so, there should not
25985edc 1136 * be any noticeable change even in non-DVFS use cases.
5d36a332
SN		 1137 */
1138 da850_set_async3_src(1);
7aad472b
SN		 1139
1140 /* Unlock writing to PLL0 registers */
1141 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1142 v &= ~CFGCHIP0_PLL_MASTER_LOCK;
1143 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1144
1145 /* Unlock writing to PLL1 registers */
1146 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
1147 v &= ~CFGCHIP3_PLL1_MASTER_LOCK;
1148 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
e1a8d7e2 1149}
Linux kernel - Deliverables
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