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davinci: da850/omap-l138: unlock PLL registers during init
[deliverable/linux.git] / arch / arm / mach-davinci / da850.c
CommitLineData
e1a8d7e2
SR		 1/*
2 * TI DA850/OMAP-L138 chip specific setup
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Derived from: arch/arm/mach-davinci/da830.c
7 * Original Copyrights follow:
8 *
9 * 2009 (c) MontaVista Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
e1a8d7e2
SR		 14#include <linux/init.h>
15#include <linux/clk.h>
16#include <linux/platform_device.h>
683b1e1f 17#include <linux/cpufreq.h>
35f9acd8 18#include <linux/regulator/consumer.h>
e1a8d7e2
SR		 19
20#include <asm/mach/map.h>
21
e1a8d7e2 22#include <mach/psc.h>
e1a8d7e2
SR		 23#include <mach/irqs.h>
24#include <mach/cputype.h>
25#include <mach/common.h>
26#include <mach/time.h>
27#include <mach/da8xx.h>
683b1e1f 28#include <mach/cpufreq.h>
e1a8d7e2
SR		 29
30#include "clock.h"
31#include "mux.h"
32
5d36a332
SN		 33/* SoC specific clock flags */
34#define DA850_CLK_ASYNC3 BIT(16)
35
e1a8d7e2
SR		 36#define DA850_PLL1_BASE 0x01e1a000
37#define DA850_TIMER64P2_BASE 0x01f0c000
38#define DA850_TIMER64P3_BASE 0x01f0d000
39
40#define DA850_REF_FREQ 24000000
41
5d36a332 42#define CFGCHIP3_ASYNC3_CLKSRC BIT(4)
7aad472b 43#define CFGCHIP3_PLL1_MASTER_LOCK BIT(5)
683b1e1f
SN		 44#define CFGCHIP0_PLL_MASTER_LOCK BIT(4)
45
46static int da850_set_armrate(struct clk *clk, unsigned long rate);
47static int da850_round_armrate(struct clk *clk, unsigned long rate);
48static int da850_set_pll0rate(struct clk *clk, unsigned long armrate);
5d36a332 49
e1a8d7e2
SR		 50static struct pll_data pll0_data = {
51 .num = 1,
52 .phys_base = DA8XX_PLL0_BASE,
53 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
54};
55
56static struct clk ref_clk = {
57 .name = "ref_clk",
58 .rate = DA850_REF_FREQ,
59};
60
61static struct clk pll0_clk = {
62 .name = "pll0",
63 .parent = &ref_clk,
64 .pll_data = &pll0_data,
65 .flags = CLK_PLL,
683b1e1f 66 .set_rate = da850_set_pll0rate,
e1a8d7e2
SR		 67};
68
69static struct clk pll0_aux_clk = {
70 .name = "pll0_aux_clk",
71 .parent = &pll0_clk,
72 .flags = CLK_PLL | PRE_PLL,
73};
74
75static struct clk pll0_sysclk2 = {
76 .name = "pll0_sysclk2",
77 .parent = &pll0_clk,
78 .flags = CLK_PLL,
79 .div_reg = PLLDIV2,
80};
81
82static struct clk pll0_sysclk3 = {
83 .name = "pll0_sysclk3",
84 .parent = &pll0_clk,
85 .flags = CLK_PLL,
86 .div_reg = PLLDIV3,
87};
88
89static struct clk pll0_sysclk4 = {
90 .name = "pll0_sysclk4",
91 .parent = &pll0_clk,
92 .flags = CLK_PLL,
93 .div_reg = PLLDIV4,
94};
95
96static struct clk pll0_sysclk5 = {
97 .name = "pll0_sysclk5",
98 .parent = &pll0_clk,
99 .flags = CLK_PLL,
100 .div_reg = PLLDIV5,
101};
102
103static struct clk pll0_sysclk6 = {
104 .name = "pll0_sysclk6",
105 .parent = &pll0_clk,
106 .flags = CLK_PLL,
107 .div_reg = PLLDIV6,
108};
109
110static struct clk pll0_sysclk7 = {
111 .name = "pll0_sysclk7",
112 .parent = &pll0_clk,
113 .flags = CLK_PLL,
114 .div_reg = PLLDIV7,
115};
116
117static struct pll_data pll1_data = {
118 .num = 2,
119 .phys_base = DA850_PLL1_BASE,
120 .flags = PLL_HAS_POSTDIV,
121};
122
123static struct clk pll1_clk = {
124 .name = "pll1",
125 .parent = &ref_clk,
126 .pll_data = &pll1_data,
127 .flags = CLK_PLL,
128};
129
130static struct clk pll1_aux_clk = {
131 .name = "pll1_aux_clk",
132 .parent = &pll1_clk,
133 .flags = CLK_PLL | PRE_PLL,
134};
135
136static struct clk pll1_sysclk2 = {
137 .name = "pll1_sysclk2",
138 .parent = &pll1_clk,
139 .flags = CLK_PLL,
140 .div_reg = PLLDIV2,
141};
142
143static struct clk pll1_sysclk3 = {
144 .name = "pll1_sysclk3",
145 .parent = &pll1_clk,
146 .flags = CLK_PLL,
147 .div_reg = PLLDIV3,
148};
149
150static struct clk pll1_sysclk4 = {
151 .name = "pll1_sysclk4",
152 .parent = &pll1_clk,
153 .flags = CLK_PLL,
154 .div_reg = PLLDIV4,
155};
156
157static struct clk pll1_sysclk5 = {
158 .name = "pll1_sysclk5",
159 .parent = &pll1_clk,
160 .flags = CLK_PLL,
161 .div_reg = PLLDIV5,
162};
163
164static struct clk pll1_sysclk6 = {
165 .name = "pll0_sysclk6",
166 .parent = &pll0_clk,
167 .flags = CLK_PLL,
168 .div_reg = PLLDIV6,
169};
170
171static struct clk pll1_sysclk7 = {
172 .name = "pll1_sysclk7",
173 .parent = &pll1_clk,
174 .flags = CLK_PLL,
175 .div_reg = PLLDIV7,
176};
177
178static struct clk i2c0_clk = {
179 .name = "i2c0",
180 .parent = &pll0_aux_clk,
181};
182
183static struct clk timerp64_0_clk = {
184 .name = "timer0",
185 .parent = &pll0_aux_clk,
186};
187
188static struct clk timerp64_1_clk = {
189 .name = "timer1",
190 .parent = &pll0_aux_clk,
191};
192
193static struct clk arm_rom_clk = {
194 .name = "arm_rom",
195 .parent = &pll0_sysclk2,
196 .lpsc = DA8XX_LPSC0_ARM_RAM_ROM,
197 .flags = ALWAYS_ENABLED,
198};
199
200static struct clk tpcc0_clk = {
201 .name = "tpcc0",
202 .parent = &pll0_sysclk2,
203 .lpsc = DA8XX_LPSC0_TPCC,
204 .flags = ALWAYS_ENABLED | CLK_PSC,
205};
206
207static struct clk tptc0_clk = {
208 .name = "tptc0",
209 .parent = &pll0_sysclk2,
210 .lpsc = DA8XX_LPSC0_TPTC0,
211 .flags = ALWAYS_ENABLED,
212};
213
214static struct clk tptc1_clk = {
215 .name = "tptc1",
216 .parent = &pll0_sysclk2,
217 .lpsc = DA8XX_LPSC0_TPTC1,
218 .flags = ALWAYS_ENABLED,
219};
220
221static struct clk tpcc1_clk = {
222 .name = "tpcc1",
223 .parent = &pll0_sysclk2,
224 .lpsc = DA850_LPSC1_TPCC1,
789a785e 225 .gpsc = 1,
e1a8d7e2 226 .flags = CLK_PSC | ALWAYS_ENABLED,
e1a8d7e2
SR		 227};
228
229static struct clk tptc2_clk = {
230 .name = "tptc2",
231 .parent = &pll0_sysclk2,
232 .lpsc = DA850_LPSC1_TPTC2,
789a785e 233 .gpsc = 1,
e1a8d7e2 234 .flags = ALWAYS_ENABLED,
e1a8d7e2
SR		 235};
236
237static struct clk uart0_clk = {
238 .name = "uart0",
239 .parent = &pll0_sysclk2,
240 .lpsc = DA8XX_LPSC0_UART0,
241};
242
243static struct clk uart1_clk = {
244 .name = "uart1",
245 .parent = &pll0_sysclk2,
246 .lpsc = DA8XX_LPSC1_UART1,
789a785e 247 .gpsc = 1,
5d36a332 248 .flags = DA850_CLK_ASYNC3,
e1a8d7e2
SR		 249};
250
251static struct clk uart2_clk = {
252 .name = "uart2",
253 .parent = &pll0_sysclk2,
254 .lpsc = DA8XX_LPSC1_UART2,
789a785e 255 .gpsc = 1,
5d36a332 256 .flags = DA850_CLK_ASYNC3,
e1a8d7e2
SR		 257};
258
259static struct clk aintc_clk = {
260 .name = "aintc",
261 .parent = &pll0_sysclk4,
262 .lpsc = DA8XX_LPSC0_AINTC,
263 .flags = ALWAYS_ENABLED,
264};
265
266static struct clk gpio_clk = {
267 .name = "gpio",
268 .parent = &pll0_sysclk4,
269 .lpsc = DA8XX_LPSC1_GPIO,
789a785e 270 .gpsc = 1,
e1a8d7e2
SR		 271};
272
273static struct clk i2c1_clk = {
274 .name = "i2c1",
275 .parent = &pll0_sysclk4,
276 .lpsc = DA8XX_LPSC1_I2C,
789a785e 277 .gpsc = 1,
e1a8d7e2
SR		 278};
279
280static struct clk emif3_clk = {
281 .name = "emif3",
282 .parent = &pll0_sysclk5,
283 .lpsc = DA8XX_LPSC1_EMIF3C,
789a785e 284 .gpsc = 1,
e1a8d7e2 285 .flags = ALWAYS_ENABLED,
e1a8d7e2
SR		 286};
287
288static struct clk arm_clk = {
289 .name = "arm",
290 .parent = &pll0_sysclk6,
291 .lpsc = DA8XX_LPSC0_ARM,
292 .flags = ALWAYS_ENABLED,
683b1e1f
SN		 293 .set_rate = da850_set_armrate,
294 .round_rate = da850_round_armrate,
e1a8d7e2
SR		 295};
296
297static struct clk rmii_clk = {
298 .name = "rmii",
299 .parent = &pll0_sysclk7,
300};
301
5a4b1315
SR		 302static struct clk emac_clk = {
303 .name = "emac",
304 .parent = &pll0_sysclk4,
305 .lpsc = DA8XX_LPSC1_CPGMAC,
789a785e 306 .gpsc = 1,
5a4b1315
SR		 307};
308
491214e1
C		 309static struct clk mcasp_clk = {
310 .name = "mcasp",
311 .parent = &pll0_sysclk2,
312 .lpsc = DA8XX_LPSC1_McASP0,
789a785e 313 .gpsc = 1,
51157ed8 314 .flags = DA850_CLK_ASYNC3,
491214e1
C		 315};
316
5cbdf276
SR		 317static struct clk lcdc_clk = {
318 .name = "lcdc",
319 .parent = &pll0_sysclk2,
320 .lpsc = DA8XX_LPSC1_LCDC,
789a785e 321 .gpsc = 1,
5cbdf276
SR		 322};
323
700691f2
SR		 324static struct clk mmcsd_clk = {
325 .name = "mmcsd",
326 .parent = &pll0_sysclk2,
327 .lpsc = DA8XX_LPSC0_MMC_SD,
328};
329
38beb929
SR		 330static struct clk aemif_clk = {
331 .name = "aemif",
332 .parent = &pll0_sysclk3,
333 .lpsc = DA8XX_LPSC0_EMIF25,
334 .flags = ALWAYS_ENABLED,
335};
336
e1a8d7e2
SR		 337static struct davinci_clk da850_clks[] = {
338 CLK(NULL, "ref", &ref_clk),
339 CLK(NULL, "pll0", &pll0_clk),
340 CLK(NULL, "pll0_aux", &pll0_aux_clk),
341 CLK(NULL, "pll0_sysclk2", &pll0_sysclk2),
342 CLK(NULL, "pll0_sysclk3", &pll0_sysclk3),
343 CLK(NULL, "pll0_sysclk4", &pll0_sysclk4),
344 CLK(NULL, "pll0_sysclk5", &pll0_sysclk5),
345 CLK(NULL, "pll0_sysclk6", &pll0_sysclk6),
346 CLK(NULL, "pll0_sysclk7", &pll0_sysclk7),
347 CLK(NULL, "pll1", &pll1_clk),
348 CLK(NULL, "pll1_aux", &pll1_aux_clk),
349 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
350 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
351 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
352 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
353 CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
354 CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
355 CLK("i2c_davinci.1", NULL, &i2c0_clk),
356 CLK(NULL, "timer0", &timerp64_0_clk),
357 CLK("watchdog", NULL, &timerp64_1_clk),
358 CLK(NULL, "arm_rom", &arm_rom_clk),
359 CLK(NULL, "tpcc0", &tpcc0_clk),
360 CLK(NULL, "tptc0", &tptc0_clk),
361 CLK(NULL, "tptc1", &tptc1_clk),
362 CLK(NULL, "tpcc1", &tpcc1_clk),
363 CLK(NULL, "tptc2", &tptc2_clk),
364 CLK(NULL, "uart0", &uart0_clk),
365 CLK(NULL, "uart1", &uart1_clk),
366 CLK(NULL, "uart2", &uart2_clk),
367 CLK(NULL, "aintc", &aintc_clk),
368 CLK(NULL, "gpio", &gpio_clk),
369 CLK("i2c_davinci.2", NULL, &i2c1_clk),
370 CLK(NULL, "emif3", &emif3_clk),
371 CLK(NULL, "arm", &arm_clk),
372 CLK(NULL, "rmii", &rmii_clk),
5a4b1315 373 CLK("davinci_emac.1", NULL, &emac_clk),
491214e1 374 CLK("davinci-mcasp.0", NULL, &mcasp_clk),
5cbdf276 375 CLK("da8xx_lcdc.0", NULL, &lcdc_clk),
700691f2 376 CLK("davinci_mmc.0", NULL, &mmcsd_clk),
38beb929 377 CLK(NULL, "aemif", &aemif_clk),
e1a8d7e2
SR		 378 CLK(NULL, NULL, NULL),
379};
380
381/*
382 * Device specific mux setup
383 *
384 * soc description mux mode mode mux dbg
385 * reg offset mask mode
386 */
387static const struct mux_config da850_pins[] = {
388#ifdef CONFIG_DAVINCI_MUX
389 /* UART0 function */
390 MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false)
391 MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false)
392 MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false)
393 MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false)
394 /* UART1 function */
395 MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false)
396 MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false)
397 /* UART2 function */
398 MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false)
399 MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false)
400 /* I2C1 function */
401 MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false)
402 MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false)
403 /* I2C0 function */
404 MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false)
405 MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false)
5a4b1315
SR		 406 /* EMAC function */
407 MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false)
408 MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false)
409 MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false)
410 MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false)
411 MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false)
412 MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false)
413 MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false)
414 MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false)
415 MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false)
416 MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false)
417 MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false)
418 MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false)
419 MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false)
420 MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false)
421 MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false)
53ca5c91
SR		 422 MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false)
423 MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false)
2206771c
C		 424 MUX_CFG(DA850, RMII_TXD_0, 14, 12, 15, 8, false)
425 MUX_CFG(DA850, RMII_TXD_1, 14, 8, 15, 8, false)
426 MUX_CFG(DA850, RMII_TXEN, 14, 16, 15, 8, false)
427 MUX_CFG(DA850, RMII_CRS_DV, 15, 4, 15, 8, false)
428 MUX_CFG(DA850, RMII_RXD_0, 14, 24, 15, 8, false)
429 MUX_CFG(DA850, RMII_RXD_1, 14, 20, 15, 8, false)
430 MUX_CFG(DA850, RMII_RXER, 14, 28, 15, 8, false)
431 MUX_CFG(DA850, RMII_MHZ_50_CLK, 15, 0, 15, 0, false)
491214e1
C		 432 /* McASP function */
433 MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false)
434 MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false)
435 MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false)
436 MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false)
437 MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false)
438 MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false)
439 MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false)
440 MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false)
441 MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false)
442 MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false)
443 MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false)
444 MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false)
445 MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false)
446 MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false)
447 MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false)
448 MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false)
449 MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false)
450 MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false)
451 MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false)
452 MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false)
453 MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false)
454 MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false)
455 MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false)
5cbdf276
SR		 456 /* LCD function */
457 MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false)
458 MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false)
459 MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false)
460 MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false)
461 MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false)
462 MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false)
463 MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false)
464 MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false)
465 MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false)
466 MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false)
467 MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false)
468 MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false)
469 MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false)
470 MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false)
471 MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false)
472 MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false)
473 MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false)
474 MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false)
475 MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false)
476 MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false)
700691f2
SR		 477 /* MMC/SD0 function */
478 MUX_CFG(DA850, MMCSD0_DAT_0, 10, 8, 15, 2, false)
479 MUX_CFG(DA850, MMCSD0_DAT_1, 10, 12, 15, 2, false)
480 MUX_CFG(DA850, MMCSD0_DAT_2, 10, 16, 15, 2, false)
481 MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false)
482 MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false)
483 MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false)
38beb929
SR		 484 /* EMIF2.5/EMIFA function */
485 MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false)
486 MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false)
487 MUX_CFG(DA850, EMA_D_5, 9, 8, 15, 1, false)
488 MUX_CFG(DA850, EMA_D_4, 9, 12, 15, 1, false)
489 MUX_CFG(DA850, EMA_D_3, 9, 16, 15, 1, false)
490 MUX_CFG(DA850, EMA_D_2, 9, 20, 15, 1, false)
491 MUX_CFG(DA850, EMA_D_1, 9, 24, 15, 1, false)
492 MUX_CFG(DA850, EMA_D_0, 9, 28, 15, 1, false)
493 MUX_CFG(DA850, EMA_A_1, 12, 24, 15, 1, false)
494 MUX_CFG(DA850, EMA_A_2, 12, 20, 15, 1, false)
495 MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false)
496 MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false)
497 MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false)
498 MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false)
7c5ec609
SR		 499 MUX_CFG(DA850, EMA_A_0, 12, 28, 15, 1, false)
500 MUX_CFG(DA850, EMA_A_3, 12, 16, 15, 1, false)
501 MUX_CFG(DA850, EMA_A_4, 12, 12, 15, 1, false)
502 MUX_CFG(DA850, EMA_A_5, 12, 8, 15, 1, false)
503 MUX_CFG(DA850, EMA_A_6, 12, 4, 15, 1, false)
504 MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false)
505 MUX_CFG(DA850, EMA_A_8, 11, 28, 15, 1, false)
506 MUX_CFG(DA850, EMA_A_9, 11, 24, 15, 1, false)
507 MUX_CFG(DA850, EMA_A_10, 11, 20, 15, 1, false)
508 MUX_CFG(DA850, EMA_A_11, 11, 16, 15, 1, false)
509 MUX_CFG(DA850, EMA_A_12, 11, 12, 15, 1, false)
510 MUX_CFG(DA850, EMA_A_13, 11, 8, 15, 1, false)
511 MUX_CFG(DA850, EMA_A_14, 11, 4, 15, 1, false)
512 MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false)
513 MUX_CFG(DA850, EMA_A_16, 10, 28, 15, 1, false)
514 MUX_CFG(DA850, EMA_A_17, 10, 24, 15, 1, false)
515 MUX_CFG(DA850, EMA_A_18, 10, 20, 15, 1, false)
516 MUX_CFG(DA850, EMA_A_19, 10, 16, 15, 1, false)
517 MUX_CFG(DA850, EMA_A_20, 10, 12, 15, 1, false)
518 MUX_CFG(DA850, EMA_A_21, 10, 8, 15, 1, false)
519 MUX_CFG(DA850, EMA_A_22, 10, 4, 15, 1, false)
520 MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false)
521 MUX_CFG(DA850, EMA_D_8, 8, 28, 15, 1, false)
522 MUX_CFG(DA850, EMA_D_9, 8, 24, 15, 1, false)
523 MUX_CFG(DA850, EMA_D_10, 8, 20, 15, 1, false)
524 MUX_CFG(DA850, EMA_D_11, 8, 16, 15, 1, false)
525 MUX_CFG(DA850, EMA_D_12, 8, 12, 15, 1, false)
526 MUX_CFG(DA850, EMA_D_13, 8, 8, 15, 1, false)
527 MUX_CFG(DA850, EMA_D_14, 8, 4, 15, 1, false)
528 MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false)
529 MUX_CFG(DA850, EMA_BA_1, 5, 24, 15, 1, false)
530 MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false)
531 MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false)
532 MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false)
5cbdf276 533 /* GPIO function */
2206771c 534 MUX_CFG(DA850, GPIO2_6, 6, 4, 15, 8, false)
7761ef67 535 MUX_CFG(DA850, GPIO2_8, 5, 28, 15, 8, false)
5cbdf276 536 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false)
700691f2
SR		 537 MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false)
538 MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false)
e1a8d7e2
SR		 539#endif
540};
541
542const short da850_uart0_pins[] __initdata = {
543 DA850_NUART0_CTS, DA850_NUART0_RTS, DA850_UART0_RXD, DA850_UART0_TXD,
544 -1
545};
546
547const short da850_uart1_pins[] __initdata = {
548 DA850_UART1_RXD, DA850_UART1_TXD,
549 -1
550};
551
552const short da850_uart2_pins[] __initdata = {
553 DA850_UART2_RXD, DA850_UART2_TXD,
554 -1
555};
556
557const short da850_i2c0_pins[] __initdata = {
558 DA850_I2C0_SDA, DA850_I2C0_SCL,
559 -1
560};
561
562const short da850_i2c1_pins[] __initdata = {
563 DA850_I2C1_SCL, DA850_I2C1_SDA,
564 -1
565};
566
5a4b1315
SR		 567const short da850_cpgmac_pins[] __initdata = {
568 DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
569 DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
570 DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
53ca5c91
SR		 571 DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
572 DA850_MDIO_D,
5a4b1315
SR		 573 -1
574};
575
2206771c
C		 576const short da850_rmii_pins[] __initdata = {
577 DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
578 DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
579 DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
580 DA850_MDIO_D,
581 -1
582};
583
491214e1
C		 584const short da850_mcasp_pins[] __initdata = {
585 DA850_AHCLKX, DA850_ACLKX, DA850_AFSX,
586 DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE,
587 DA850_AXR_11, DA850_AXR_12,
588 -1
589};
590
5cbdf276 591const short da850_lcdcntl_pins[] __initdata = {
7761ef67
SR		 592 DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
593 DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
594 DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11,
595 DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15,
596 DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS,
5cbdf276
SR		 597 -1
598};
599
700691f2
SR		 600const short da850_mmcsd0_pins[] __initdata = {
601 DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2,
602 DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD,
603 DA850_GPIO4_0, DA850_GPIO4_1,
604 -1
605};
606
38beb929
SR		 607const short da850_nand_pins[] __initdata = {
608 DA850_EMA_D_7, DA850_EMA_D_6, DA850_EMA_D_5, DA850_EMA_D_4,
609 DA850_EMA_D_3, DA850_EMA_D_2, DA850_EMA_D_1, DA850_EMA_D_0,
610 DA850_EMA_A_1, DA850_EMA_A_2, DA850_NEMA_CS_3, DA850_NEMA_CS_4,
611 DA850_NEMA_WE, DA850_NEMA_OE,
612 -1
613};
614
7c5ec609
SR		 615const short da850_nor_pins[] __initdata = {
616 DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2,
617 DA850_NEMA_WE, DA850_NEMA_OE, DA850_EMA_D_0, DA850_EMA_D_1,
618 DA850_EMA_D_2, DA850_EMA_D_3, DA850_EMA_D_4, DA850_EMA_D_5,
619 DA850_EMA_D_6, DA850_EMA_D_7, DA850_EMA_D_8, DA850_EMA_D_9,
620 DA850_EMA_D_10, DA850_EMA_D_11, DA850_EMA_D_12, DA850_EMA_D_13,
621 DA850_EMA_D_14, DA850_EMA_D_15, DA850_EMA_A_0, DA850_EMA_A_1,
622 DA850_EMA_A_2, DA850_EMA_A_3, DA850_EMA_A_4, DA850_EMA_A_5,
623 DA850_EMA_A_6, DA850_EMA_A_7, DA850_EMA_A_8, DA850_EMA_A_9,
624 DA850_EMA_A_10, DA850_EMA_A_11, DA850_EMA_A_12, DA850_EMA_A_13,
625 DA850_EMA_A_14, DA850_EMA_A_15, DA850_EMA_A_16, DA850_EMA_A_17,
626 DA850_EMA_A_18, DA850_EMA_A_19, DA850_EMA_A_20, DA850_EMA_A_21,
627 DA850_EMA_A_22, DA850_EMA_A_23,
628 -1
629};
630
e1a8d7e2
SR		 631/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
632static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
633 [IRQ_DA8XX_COMMTX] = 7,
634 [IRQ_DA8XX_COMMRX] = 7,
635 [IRQ_DA8XX_NINT] = 7,
636 [IRQ_DA8XX_EVTOUT0] = 7,
637 [IRQ_DA8XX_EVTOUT1] = 7,
638 [IRQ_DA8XX_EVTOUT2] = 7,
639 [IRQ_DA8XX_EVTOUT3] = 7,
640 [IRQ_DA8XX_EVTOUT4] = 7,
641 [IRQ_DA8XX_EVTOUT5] = 7,
642 [IRQ_DA8XX_EVTOUT6] = 7,
643 [IRQ_DA8XX_EVTOUT6] = 7,
644 [IRQ_DA8XX_EVTOUT7] = 7,
645 [IRQ_DA8XX_CCINT0] = 7,
646 [IRQ_DA8XX_CCERRINT] = 7,
647 [IRQ_DA8XX_TCERRINT0] = 7,
648 [IRQ_DA8XX_AEMIFINT] = 7,
649 [IRQ_DA8XX_I2CINT0] = 7,
650 [IRQ_DA8XX_MMCSDINT0] = 7,
651 [IRQ_DA8XX_MMCSDINT1] = 7,
652 [IRQ_DA8XX_ALLINT0] = 7,
653 [IRQ_DA8XX_RTC] = 7,
654 [IRQ_DA8XX_SPINT0] = 7,
655 [IRQ_DA8XX_TINT12_0] = 7,
656 [IRQ_DA8XX_TINT34_0] = 7,
657 [IRQ_DA8XX_TINT12_1] = 7,
658 [IRQ_DA8XX_TINT34_1] = 7,
659 [IRQ_DA8XX_UARTINT0] = 7,
660 [IRQ_DA8XX_KEYMGRINT] = 7,
661 [IRQ_DA8XX_SECINT] = 7,
662 [IRQ_DA8XX_SECKEYERR] = 7,
663 [IRQ_DA850_MPUADDRERR0] = 7,
664 [IRQ_DA850_MPUPROTERR0] = 7,
665 [IRQ_DA850_IOPUADDRERR0] = 7,
666 [IRQ_DA850_IOPUPROTERR0] = 7,
667 [IRQ_DA850_IOPUADDRERR1] = 7,
668 [IRQ_DA850_IOPUPROTERR1] = 7,
669 [IRQ_DA850_IOPUADDRERR2] = 7,
670 [IRQ_DA850_IOPUPROTERR2] = 7,
671 [IRQ_DA850_BOOTCFG_ADDR_ERR] = 7,
672 [IRQ_DA850_BOOTCFG_PROT_ERR] = 7,
673 [IRQ_DA850_MPUADDRERR1] = 7,
674 [IRQ_DA850_MPUPROTERR1] = 7,
675 [IRQ_DA850_IOPUADDRERR3] = 7,
676 [IRQ_DA850_IOPUPROTERR3] = 7,
677 [IRQ_DA850_IOPUADDRERR4] = 7,
678 [IRQ_DA850_IOPUPROTERR4] = 7,
679 [IRQ_DA850_IOPUADDRERR5] = 7,
680 [IRQ_DA850_IOPUPROTERR5] = 7,
681 [IRQ_DA850_MIOPU_BOOTCFG_ERR] = 7,
682 [IRQ_DA8XX_CHIPINT0] = 7,
683 [IRQ_DA8XX_CHIPINT1] = 7,
684 [IRQ_DA8XX_CHIPINT2] = 7,
685 [IRQ_DA8XX_CHIPINT3] = 7,
686 [IRQ_DA8XX_TCERRINT1] = 7,
687 [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7,
688 [IRQ_DA8XX_C0_RX_PULSE] = 7,
689 [IRQ_DA8XX_C0_TX_PULSE] = 7,
690 [IRQ_DA8XX_C0_MISC_PULSE] = 7,
691 [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7,
692 [IRQ_DA8XX_C1_RX_PULSE] = 7,
693 [IRQ_DA8XX_C1_TX_PULSE] = 7,
694 [IRQ_DA8XX_C1_MISC_PULSE] = 7,
695 [IRQ_DA8XX_MEMERR] = 7,
696 [IRQ_DA8XX_GPIO0] = 7,
697 [IRQ_DA8XX_GPIO1] = 7,
698 [IRQ_DA8XX_GPIO2] = 7,
699 [IRQ_DA8XX_GPIO3] = 7,
700 [IRQ_DA8XX_GPIO4] = 7,
701 [IRQ_DA8XX_GPIO5] = 7,
702 [IRQ_DA8XX_GPIO6] = 7,
703 [IRQ_DA8XX_GPIO7] = 7,
704 [IRQ_DA8XX_GPIO8] = 7,
705 [IRQ_DA8XX_I2CINT1] = 7,
706 [IRQ_DA8XX_LCDINT] = 7,
707 [IRQ_DA8XX_UARTINT1] = 7,
708 [IRQ_DA8XX_MCASPINT] = 7,
709 [IRQ_DA8XX_ALLINT1] = 7,
710 [IRQ_DA8XX_SPINT1] = 7,
711 [IRQ_DA8XX_UHPI_INT1] = 7,
712 [IRQ_DA8XX_USB_INT] = 7,
713 [IRQ_DA8XX_IRQN] = 7,
714 [IRQ_DA8XX_RWAKEUP] = 7,
715 [IRQ_DA8XX_UARTINT2] = 7,
716 [IRQ_DA8XX_DFTSSINT] = 7,
717 [IRQ_DA8XX_EHRPWM0] = 7,
718 [IRQ_DA8XX_EHRPWM0TZ] = 7,
719 [IRQ_DA8XX_EHRPWM1] = 7,
720 [IRQ_DA8XX_EHRPWM1TZ] = 7,
721 [IRQ_DA850_SATAINT] = 7,
722 [IRQ_DA850_TINT12_2] = 7,
723 [IRQ_DA850_TINT34_2] = 7,
724 [IRQ_DA850_TINTALL_2] = 7,
725 [IRQ_DA8XX_ECAP0] = 7,
726 [IRQ_DA8XX_ECAP1] = 7,
727 [IRQ_DA8XX_ECAP2] = 7,
728 [IRQ_DA850_MMCSDINT0_1] = 7,
729 [IRQ_DA850_MMCSDINT1_1] = 7,
730 [IRQ_DA850_T12CMPINT0_2] = 7,
731 [IRQ_DA850_T12CMPINT1_2] = 7,
732 [IRQ_DA850_T12CMPINT2_2] = 7,
733 [IRQ_DA850_T12CMPINT3_2] = 7,
734 [IRQ_DA850_T12CMPINT4_2] = 7,
735 [IRQ_DA850_T12CMPINT5_2] = 7,
736 [IRQ_DA850_T12CMPINT6_2] = 7,
737 [IRQ_DA850_T12CMPINT7_2] = 7,
738 [IRQ_DA850_T12CMPINT0_3] = 7,
739 [IRQ_DA850_T12CMPINT1_3] = 7,
740 [IRQ_DA850_T12CMPINT2_3] = 7,
741 [IRQ_DA850_T12CMPINT3_3] = 7,
742 [IRQ_DA850_T12CMPINT4_3] = 7,
743 [IRQ_DA850_T12CMPINT5_3] = 7,
744 [IRQ_DA850_T12CMPINT6_3] = 7,
745 [IRQ_DA850_T12CMPINT7_3] = 7,
746 [IRQ_DA850_RPIINT] = 7,
747 [IRQ_DA850_VPIFINT] = 7,
748 [IRQ_DA850_CCINT1] = 7,
749 [IRQ_DA850_CCERRINT1] = 7,
750 [IRQ_DA850_TCERRINT2] = 7,
751 [IRQ_DA850_TINT12_3] = 7,
752 [IRQ_DA850_TINT34_3] = 7,
753 [IRQ_DA850_TINTALL_3] = 7,
754 [IRQ_DA850_MCBSP0RINT] = 7,
755 [IRQ_DA850_MCBSP0XINT] = 7,
756 [IRQ_DA850_MCBSP1RINT] = 7,
757 [IRQ_DA850_MCBSP1XINT] = 7,
758 [IRQ_DA8XX_ARMCLKSTOPREQ] = 7,
759};
760
761static struct map_desc da850_io_desc[] = {
762 {
763 .virtual = IO_VIRT,
764 .pfn = __phys_to_pfn(IO_PHYS),
765 .length = IO_SIZE,
766 .type = MT_DEVICE
767 },
768 {
769 .virtual = DA8XX_CP_INTC_VIRT,
770 .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE),
771 .length = DA8XX_CP_INTC_SIZE,
772 .type = MT_DEVICE
773 },
774};
775
776static void __iomem *da850_psc_bases[] = {
777 IO_ADDRESS(DA8XX_PSC0_BASE),
778 IO_ADDRESS(DA8XX_PSC1_BASE),
779};
780
781/* Contents of JTAG ID register used to identify exact cpu type */
782static struct davinci_id da850_ids[] = {
783 {
784 .variant = 0x0,
785 .part_no = 0xb7d1,
786 .manufacturer = 0x017, /* 0x02f >> 1 */
787 .cpu_id = DAVINCI_CPU_ID_DA850,
788 .name = "da850/omap-l138",
789 },
790};
791
792static struct davinci_timer_instance da850_timer_instance[4] = {
793 {
794 .base = IO_ADDRESS(DA8XX_TIMER64P0_BASE),
795 .bottom_irq = IRQ_DA8XX_TINT12_0,
796 .top_irq = IRQ_DA8XX_TINT34_0,
797 },
798 {
799 .base = IO_ADDRESS(DA8XX_TIMER64P1_BASE),
800 .bottom_irq = IRQ_DA8XX_TINT12_1,
801 .top_irq = IRQ_DA8XX_TINT34_1,
802 },
803 {
804 .base = IO_ADDRESS(DA850_TIMER64P2_BASE),
805 .bottom_irq = IRQ_DA850_TINT12_2,
806 .top_irq = IRQ_DA850_TINT34_2,
807 },
808 {
809 .base = IO_ADDRESS(DA850_TIMER64P3_BASE),
810 .bottom_irq = IRQ_DA850_TINT12_3,
811 .top_irq = IRQ_DA850_TINT34_3,
812 },
813};
814
815/*
816 * T0_BOT: Timer 0, bottom : Used for clock_event
817 * T0_TOP: Timer 0, top : Used for clocksource
818 * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
819 */
820static struct davinci_timer_info da850_timer_info = {
821 .timers = da850_timer_instance,
822 .clockevent_id = T0_BOT,
823 .clocksource_id = T0_TOP,
824};
825
5d36a332
SN		 826static void da850_set_async3_src(int pllnum)
827{
828 struct clk *clk, *newparent = pllnum ? &pll1_sysclk2 : &pll0_sysclk2;
829 struct davinci_clk *c;
830 unsigned int v;
831 int ret;
832
833 for (c = da850_clks; c->lk.clk; c++) {
834 clk = c->lk.clk;
835 if (clk->flags & DA850_CLK_ASYNC3) {
836 ret = clk_set_parent(clk, newparent);
837 WARN(ret, "DA850: unable to re-parent clock %s",
838 clk->name);
839 }
840 }
841
d2de0582 842 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
5d36a332
SN		 843 if (pllnum)
844 v |= CFGCHIP3_ASYNC3_CLKSRC;
845 else
846 v &= ~CFGCHIP3_ASYNC3_CLKSRC;
d2de0582 847 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
5d36a332
SN		 848}
849
683b1e1f
SN		 850#ifdef CONFIG_CPU_FREQ
851/*
852 * Notes:
853 * According to the TRM, minimum PLLM results in maximum power savings.
854 * The OPP definitions below should keep the PLLM as low as possible.
855 *
856 * The output of the PLLM must be between 400 to 600 MHz.
857 * This rules out prediv of anything but divide-by-one for 24Mhz OSC input.
858 */
859struct da850_opp {
860 unsigned int freq; /* in KHz */
861 unsigned int prediv;
862 unsigned int mult;
863 unsigned int postdiv;
35f9acd8
SN		 864 unsigned int cvdd_min; /* in uV */
865 unsigned int cvdd_max; /* in uV */
683b1e1f
SN		 866};
867
868static const struct da850_opp da850_opp_300 = {
869 .freq = 300000,
870 .prediv = 1,
871 .mult = 25,
872 .postdiv = 2,
35f9acd8
SN		 873 .cvdd_min = 1140000,
874 .cvdd_max = 1320000,
683b1e1f
SN		 875};
876
877static const struct da850_opp da850_opp_200 = {
878 .freq = 200000,
879 .prediv = 1,
880 .mult = 25,
881 .postdiv = 3,
35f9acd8
SN		 882 .cvdd_min = 1050000,
883 .cvdd_max = 1160000,
683b1e1f
SN		 884};
885
886static const struct da850_opp da850_opp_96 = {
887 .freq = 96000,
888 .prediv = 1,
889 .mult = 20,
890 .postdiv = 5,
35f9acd8
SN		 891 .cvdd_min = 950000,
892 .cvdd_max = 1050000,
683b1e1f
SN		 893};
894
895#define OPP(freq) \
896 { \
897 .index = (unsigned int) &da850_opp_##freq, \
898 .frequency = freq * 1000, \
899 }
900
901static struct cpufreq_frequency_table da850_freq_table[] = {
902 OPP(300),
903 OPP(200),
904 OPP(96),
905 {
906 .index = 0,
907 .frequency = CPUFREQ_TABLE_END,
908 },
909};
910
13d5e27a
SN		 911#ifdef CONFIG_REGULATOR
912static struct regulator *cvdd;
913
914static int da850_set_voltage(unsigned int index)
915{
916 struct da850_opp *opp;
917
918 if (!cvdd)
919 return -ENODEV;
920
921 opp = (struct da850_opp *) da850_freq_table[index].index;
922
923 return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
924}
925
926static int da850_regulator_init(void)
927{
928 cvdd = regulator_get(NULL, "cvdd");
929 if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;"
930 " voltage scaling unsupported\n")) {
931 return PTR_ERR(cvdd);
932 }
933
934 return 0;
935}
936#endif
937
683b1e1f
SN		 938static struct davinci_cpufreq_config cpufreq_info = {
939 .freq_table = &da850_freq_table[0],
13d5e27a
SN		 940#ifdef CONFIG_REGULATOR
941 .init = da850_regulator_init,
942 .set_voltage = da850_set_voltage,
943#endif
683b1e1f
SN		 944};
945
946static struct platform_device da850_cpufreq_device = {
947 .name = "cpufreq-davinci",
948 .dev = {
949 .platform_data = &cpufreq_info,
950 },
951};
952
953int __init da850_register_cpufreq(void)
954{
955 return platform_device_register(&da850_cpufreq_device);
956}
957
958static int da850_round_armrate(struct clk *clk, unsigned long rate)
959{
960 int i, ret = 0, diff;
961 unsigned int best = (unsigned int) -1;
962
963 rate /= 1000; /* convert to kHz */
964
965 for (i = 0; da850_freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
966 diff = da850_freq_table[i].frequency - rate;
967 if (diff < 0)
968 diff = -diff;
969
970 if (diff < best) {
971 best = diff;
972 ret = da850_freq_table[i].frequency;
973 }
974 }
975
976 return ret * 1000;
977}
978
979static int da850_set_armrate(struct clk *clk, unsigned long index)
980{
981 struct clk *pllclk = &pll0_clk;
982
983 return clk_set_rate(pllclk, index);
984}
985
986static int da850_set_pll0rate(struct clk *clk, unsigned long index)
987{
988 unsigned int prediv, mult, postdiv;
989 struct da850_opp *opp;
990 struct pll_data *pll = clk->pll_data;
683b1e1f
SN		 991 int ret;
992
993 opp = (struct da850_opp *) da850_freq_table[index].index;
994 prediv = opp->prediv;
995 mult = opp->mult;
996 postdiv = opp->postdiv;
997
683b1e1f
SN		 998 ret = davinci_set_pllrate(pll, prediv, mult, postdiv);
999 if (WARN_ON(ret))
1000 return ret;
1001
1002 return 0;
1003}
1004#else
1005int __init da850_register_cpufreq(void)
1006{
1007 return 0;
1008}
1009
1010static int da850_set_armrate(struct clk *clk, unsigned long rate)
1011{
1012 return -EINVAL;
1013}
1014
1015static int da850_set_pll0rate(struct clk *clk, unsigned long armrate)
1016{
1017 return -EINVAL;
1018}
1019
1020static int da850_round_armrate(struct clk *clk, unsigned long rate)
1021{
1022 return clk->rate;
1023}
1024#endif
1025
35f9acd8 1026
e1a8d7e2
SR		 1027static struct davinci_soc_info davinci_soc_info_da850 = {
1028 .io_desc = da850_io_desc,
1029 .io_desc_num = ARRAY_SIZE(da850_io_desc),
e1a8d7e2
SR		 1030 .ids = da850_ids,
1031 .ids_num = ARRAY_SIZE(da850_ids),
1032 .cpu_clks = da850_clks,
1033 .psc_bases = da850_psc_bases,
1034 .psc_bases_num = ARRAY_SIZE(da850_psc_bases),
e1a8d7e2
SR		 1035 .pinmux_pins = da850_pins,
1036 .pinmux_pins_num = ARRAY_SIZE(da850_pins),
1037 .intc_base = (void __iomem *)DA8XX_CP_INTC_VIRT,
1038 .intc_type = DAVINCI_INTC_TYPE_CP_INTC,
1039 .intc_irq_prios = da850_default_priorities,
1040 .intc_irq_num = DA850_N_CP_INTC_IRQ,
1041 .timer_info = &da850_timer_info,
1042 .gpio_base = IO_ADDRESS(DA8XX_GPIO_BASE),
5a8d5441 1043 .gpio_num = 144,
e1a8d7e2
SR		 1044 .gpio_irq = IRQ_DA8XX_GPIO0,
1045 .serial_dev = &da8xx_serial_device,
1046 .emac_pdata = &da8xx_emac_pdata,
1047};
1048
1049void __init da850_init(void)
1050{
7aad472b
SN		 1051 unsigned int v;
1052
d2de0582
SN		 1053 da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
1054 if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
1055 return;
1056
1057 da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K);
1058 if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
6a28adef
SN		 1059 return;
1060
cd874448 1061 davinci_soc_info_da850.jtag_id_base =
d2de0582
SN		 1062 DA8XX_SYSCFG0_VIRT(DA8XX_JTAG_ID_REG);
1063 davinci_soc_info_da850.pinmux_base = DA8XX_SYSCFG0_VIRT(0x120);
6a28adef 1064
e1a8d7e2 1065 davinci_common_init(&davinci_soc_info_da850);
5d36a332
SN		 1066
1067 /*
1068 * Move the clock source of Async3 domain to PLL1 SYSCLK2.
1069 * This helps keeping the peripherals on this domain insulated
1070 * from CPU frequency changes caused by DVFS. The firmware sets
1071 * both PLL0 and PLL1 to the same frequency so, there should not
1072 * be any noticible change even in non-DVFS use cases.
1073 */
1074 da850_set_async3_src(1);
7aad472b
SN		 1075
1076 /* Unlock writing to PLL0 registers */
1077 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1078 v &= ~CFGCHIP0_PLL_MASTER_LOCK;
1079 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1080
1081 /* Unlock writing to PLL1 registers */
1082 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
1083 v &= ~CFGCHIP3_PLL1_MASTER_LOCK;
1084 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
e1a8d7e2 1085}
Linux kernel - Deliverables
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