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davinci: clock: make 'disable unused clocks' printk debug only
[deliverable/linux.git] / arch / arm / mach-davinci / da850.c
CommitLineData
e1a8d7e2
SR		 1/*
2 * TI DA850/OMAP-L138 chip specific setup
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Derived from: arch/arm/mach-davinci/da830.c
7 * Original Copyrights follow:
8 *
9 * 2009 (c) MontaVista Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
e1a8d7e2
SR		 14#include <linux/init.h>
15#include <linux/clk.h>
16#include <linux/platform_device.h>
683b1e1f 17#include <linux/cpufreq.h>
35f9acd8 18#include <linux/regulator/consumer.h>
e1a8d7e2
SR		 19
20#include <asm/mach/map.h>
21
e1a8d7e2 22#include <mach/psc.h>
e1a8d7e2
SR		 23#include <mach/irqs.h>
24#include <mach/cputype.h>
25#include <mach/common.h>
26#include <mach/time.h>
27#include <mach/da8xx.h>
683b1e1f 28#include <mach/cpufreq.h>
044ca015 29#include <mach/pm.h>
686b634a 30#include <mach/gpio.h>
e1a8d7e2
SR		 31
32#include "clock.h"
33#include "mux.h"
34
5d36a332
SN		 35/* SoC specific clock flags */
36#define DA850_CLK_ASYNC3 BIT(16)
37
e1a8d7e2
SR		 38#define DA850_PLL1_BASE 0x01e1a000
39#define DA850_TIMER64P2_BASE 0x01f0c000
40#define DA850_TIMER64P3_BASE 0x01f0d000
41
42#define DA850_REF_FREQ 24000000
43
5d36a332 44#define CFGCHIP3_ASYNC3_CLKSRC BIT(4)
7aad472b 45#define CFGCHIP3_PLL1_MASTER_LOCK BIT(5)
683b1e1f
SN		 46#define CFGCHIP0_PLL_MASTER_LOCK BIT(4)
47
48static int da850_set_armrate(struct clk *clk, unsigned long rate);
49static int da850_round_armrate(struct clk *clk, unsigned long rate);
50static int da850_set_pll0rate(struct clk *clk, unsigned long armrate);
5d36a332 51
e1a8d7e2
SR		 52static struct pll_data pll0_data = {
53 .num = 1,
54 .phys_base = DA8XX_PLL0_BASE,
55 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
56};
57
58static struct clk ref_clk = {
59 .name = "ref_clk",
60 .rate = DA850_REF_FREQ,
61};
62
63static struct clk pll0_clk = {
64 .name = "pll0",
65 .parent = &ref_clk,
66 .pll_data = &pll0_data,
67 .flags = CLK_PLL,
683b1e1f 68 .set_rate = da850_set_pll0rate,
e1a8d7e2
SR		 69};
70
71static struct clk pll0_aux_clk = {
72 .name = "pll0_aux_clk",
73 .parent = &pll0_clk,
74 .flags = CLK_PLL | PRE_PLL,
75};
76
77static struct clk pll0_sysclk2 = {
78 .name = "pll0_sysclk2",
79 .parent = &pll0_clk,
80 .flags = CLK_PLL,
81 .div_reg = PLLDIV2,
82};
83
84static struct clk pll0_sysclk3 = {
85 .name = "pll0_sysclk3",
86 .parent = &pll0_clk,
87 .flags = CLK_PLL,
88 .div_reg = PLLDIV3,
89};
90
91static struct clk pll0_sysclk4 = {
92 .name = "pll0_sysclk4",
93 .parent = &pll0_clk,
94 .flags = CLK_PLL,
95 .div_reg = PLLDIV4,
96};
97
98static struct clk pll0_sysclk5 = {
99 .name = "pll0_sysclk5",
100 .parent = &pll0_clk,
101 .flags = CLK_PLL,
102 .div_reg = PLLDIV5,
103};
104
105static struct clk pll0_sysclk6 = {
106 .name = "pll0_sysclk6",
107 .parent = &pll0_clk,
108 .flags = CLK_PLL,
109 .div_reg = PLLDIV6,
110};
111
112static struct clk pll0_sysclk7 = {
113 .name = "pll0_sysclk7",
114 .parent = &pll0_clk,
115 .flags = CLK_PLL,
116 .div_reg = PLLDIV7,
117};
118
119static struct pll_data pll1_data = {
120 .num = 2,
121 .phys_base = DA850_PLL1_BASE,
122 .flags = PLL_HAS_POSTDIV,
123};
124
125static struct clk pll1_clk = {
126 .name = "pll1",
127 .parent = &ref_clk,
128 .pll_data = &pll1_data,
129 .flags = CLK_PLL,
130};
131
132static struct clk pll1_aux_clk = {
133 .name = "pll1_aux_clk",
134 .parent = &pll1_clk,
135 .flags = CLK_PLL | PRE_PLL,
136};
137
138static struct clk pll1_sysclk2 = {
139 .name = "pll1_sysclk2",
140 .parent = &pll1_clk,
141 .flags = CLK_PLL,
142 .div_reg = PLLDIV2,
143};
144
145static struct clk pll1_sysclk3 = {
146 .name = "pll1_sysclk3",
147 .parent = &pll1_clk,
148 .flags = CLK_PLL,
149 .div_reg = PLLDIV3,
150};
151
152static struct clk pll1_sysclk4 = {
153 .name = "pll1_sysclk4",
154 .parent = &pll1_clk,
155 .flags = CLK_PLL,
156 .div_reg = PLLDIV4,
157};
158
159static struct clk pll1_sysclk5 = {
160 .name = "pll1_sysclk5",
161 .parent = &pll1_clk,
162 .flags = CLK_PLL,
163 .div_reg = PLLDIV5,
164};
165
166static struct clk pll1_sysclk6 = {
167 .name = "pll0_sysclk6",
168 .parent = &pll0_clk,
169 .flags = CLK_PLL,
170 .div_reg = PLLDIV6,
171};
172
173static struct clk pll1_sysclk7 = {
174 .name = "pll1_sysclk7",
175 .parent = &pll1_clk,
176 .flags = CLK_PLL,
177 .div_reg = PLLDIV7,
178};
179
180static struct clk i2c0_clk = {
181 .name = "i2c0",
182 .parent = &pll0_aux_clk,
183};
184
185static struct clk timerp64_0_clk = {
186 .name = "timer0",
187 .parent = &pll0_aux_clk,
188};
189
190static struct clk timerp64_1_clk = {
191 .name = "timer1",
192 .parent = &pll0_aux_clk,
193};
194
195static struct clk arm_rom_clk = {
196 .name = "arm_rom",
197 .parent = &pll0_sysclk2,
198 .lpsc = DA8XX_LPSC0_ARM_RAM_ROM,
199 .flags = ALWAYS_ENABLED,
200};
201
202static struct clk tpcc0_clk = {
203 .name = "tpcc0",
204 .parent = &pll0_sysclk2,
205 .lpsc = DA8XX_LPSC0_TPCC,
206 .flags = ALWAYS_ENABLED | CLK_PSC,
207};
208
209static struct clk tptc0_clk = {
210 .name = "tptc0",
211 .parent = &pll0_sysclk2,
212 .lpsc = DA8XX_LPSC0_TPTC0,
213 .flags = ALWAYS_ENABLED,
214};
215
216static struct clk tptc1_clk = {
217 .name = "tptc1",
218 .parent = &pll0_sysclk2,
219 .lpsc = DA8XX_LPSC0_TPTC1,
220 .flags = ALWAYS_ENABLED,
221};
222
223static struct clk tpcc1_clk = {
224 .name = "tpcc1",
225 .parent = &pll0_sysclk2,
226 .lpsc = DA850_LPSC1_TPCC1,
789a785e 227 .gpsc = 1,
e1a8d7e2 228 .flags = CLK_PSC | ALWAYS_ENABLED,
e1a8d7e2
SR		 229};
230
231static struct clk tptc2_clk = {
232 .name = "tptc2",
233 .parent = &pll0_sysclk2,
234 .lpsc = DA850_LPSC1_TPTC2,
789a785e 235 .gpsc = 1,
e1a8d7e2 236 .flags = ALWAYS_ENABLED,
e1a8d7e2
SR		 237};
238
239static struct clk uart0_clk = {
240 .name = "uart0",
241 .parent = &pll0_sysclk2,
242 .lpsc = DA8XX_LPSC0_UART0,
243};
244
245static struct clk uart1_clk = {
246 .name = "uart1",
247 .parent = &pll0_sysclk2,
248 .lpsc = DA8XX_LPSC1_UART1,
789a785e 249 .gpsc = 1,
5d36a332 250 .flags = DA850_CLK_ASYNC3,
e1a8d7e2
SR		 251};
252
253static struct clk uart2_clk = {
254 .name = "uart2",
255 .parent = &pll0_sysclk2,
256 .lpsc = DA8XX_LPSC1_UART2,
789a785e 257 .gpsc = 1,
5d36a332 258 .flags = DA850_CLK_ASYNC3,
e1a8d7e2
SR		 259};
260
261static struct clk aintc_clk = {
262 .name = "aintc",
263 .parent = &pll0_sysclk4,
264 .lpsc = DA8XX_LPSC0_AINTC,
265 .flags = ALWAYS_ENABLED,
266};
267
268static struct clk gpio_clk = {
269 .name = "gpio",
270 .parent = &pll0_sysclk4,
271 .lpsc = DA8XX_LPSC1_GPIO,
789a785e 272 .gpsc = 1,
e1a8d7e2
SR		 273};
274
275static struct clk i2c1_clk = {
276 .name = "i2c1",
277 .parent = &pll0_sysclk4,
278 .lpsc = DA8XX_LPSC1_I2C,
789a785e 279 .gpsc = 1,
e1a8d7e2
SR		 280};
281
282static struct clk emif3_clk = {
283 .name = "emif3",
284 .parent = &pll0_sysclk5,
285 .lpsc = DA8XX_LPSC1_EMIF3C,
789a785e 286 .gpsc = 1,
e1a8d7e2 287 .flags = ALWAYS_ENABLED,
e1a8d7e2
SR		 288};
289
290static struct clk arm_clk = {
291 .name = "arm",
292 .parent = &pll0_sysclk6,
293 .lpsc = DA8XX_LPSC0_ARM,
294 .flags = ALWAYS_ENABLED,
683b1e1f
SN		 295 .set_rate = da850_set_armrate,
296 .round_rate = da850_round_armrate,
e1a8d7e2
SR		 297};
298
299static struct clk rmii_clk = {
300 .name = "rmii",
301 .parent = &pll0_sysclk7,
302};
303
5a4b1315
SR		 304static struct clk emac_clk = {
305 .name = "emac",
306 .parent = &pll0_sysclk4,
307 .lpsc = DA8XX_LPSC1_CPGMAC,
789a785e 308 .gpsc = 1,
5a4b1315
SR		 309};
310
491214e1
C		 311static struct clk mcasp_clk = {
312 .name = "mcasp",
313 .parent = &pll0_sysclk2,
314 .lpsc = DA8XX_LPSC1_McASP0,
789a785e 315 .gpsc = 1,
51157ed8 316 .flags = DA850_CLK_ASYNC3,
491214e1
C		 317};
318
5cbdf276
SR		 319static struct clk lcdc_clk = {
320 .name = "lcdc",
321 .parent = &pll0_sysclk2,
322 .lpsc = DA8XX_LPSC1_LCDC,
789a785e 323 .gpsc = 1,
5cbdf276
SR		 324};
325
700691f2
SR		 326static struct clk mmcsd_clk = {
327 .name = "mmcsd",
328 .parent = &pll0_sysclk2,
329 .lpsc = DA8XX_LPSC0_MMC_SD,
330};
331
38beb929
SR		 332static struct clk aemif_clk = {
333 .name = "aemif",
334 .parent = &pll0_sysclk3,
335 .lpsc = DA8XX_LPSC0_EMIF25,
336 .flags = ALWAYS_ENABLED,
337};
338
08aca087 339static struct clk_lookup da850_clks[] = {
e1a8d7e2
SR		 340 CLK(NULL, "ref", &ref_clk),
341 CLK(NULL, "pll0", &pll0_clk),
342 CLK(NULL, "pll0_aux", &pll0_aux_clk),
343 CLK(NULL, "pll0_sysclk2", &pll0_sysclk2),
344 CLK(NULL, "pll0_sysclk3", &pll0_sysclk3),
345 CLK(NULL, "pll0_sysclk4", &pll0_sysclk4),
346 CLK(NULL, "pll0_sysclk5", &pll0_sysclk5),
347 CLK(NULL, "pll0_sysclk6", &pll0_sysclk6),
348 CLK(NULL, "pll0_sysclk7", &pll0_sysclk7),
349 CLK(NULL, "pll1", &pll1_clk),
350 CLK(NULL, "pll1_aux", &pll1_aux_clk),
351 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
352 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
353 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
354 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
355 CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
356 CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
357 CLK("i2c_davinci.1", NULL, &i2c0_clk),
358 CLK(NULL, "timer0", &timerp64_0_clk),
359 CLK("watchdog", NULL, &timerp64_1_clk),
360 CLK(NULL, "arm_rom", &arm_rom_clk),
361 CLK(NULL, "tpcc0", &tpcc0_clk),
362 CLK(NULL, "tptc0", &tptc0_clk),
363 CLK(NULL, "tptc1", &tptc1_clk),
364 CLK(NULL, "tpcc1", &tpcc1_clk),
365 CLK(NULL, "tptc2", &tptc2_clk),
366 CLK(NULL, "uart0", &uart0_clk),
367 CLK(NULL, "uart1", &uart1_clk),
368 CLK(NULL, "uart2", &uart2_clk),
369 CLK(NULL, "aintc", &aintc_clk),
370 CLK(NULL, "gpio", &gpio_clk),
371 CLK("i2c_davinci.2", NULL, &i2c1_clk),
372 CLK(NULL, "emif3", &emif3_clk),
373 CLK(NULL, "arm", &arm_clk),
374 CLK(NULL, "rmii", &rmii_clk),
5a4b1315 375 CLK("davinci_emac.1", NULL, &emac_clk),
491214e1 376 CLK("davinci-mcasp.0", NULL, &mcasp_clk),
5cbdf276 377 CLK("da8xx_lcdc.0", NULL, &lcdc_clk),
700691f2 378 CLK("davinci_mmc.0", NULL, &mmcsd_clk),
38beb929 379 CLK(NULL, "aemif", &aemif_clk),
e1a8d7e2
SR		 380 CLK(NULL, NULL, NULL),
381};
382
383/*
384 * Device specific mux setup
385 *
386 * soc description mux mode mode mux dbg
387 * reg offset mask mode
388 */
389static const struct mux_config da850_pins[] = {
390#ifdef CONFIG_DAVINCI_MUX
391 /* UART0 function */
392 MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false)
393 MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false)
394 MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false)
395 MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false)
396 /* UART1 function */
397 MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false)
398 MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false)
399 /* UART2 function */
400 MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false)
401 MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false)
402 /* I2C1 function */
403 MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false)
404 MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false)
405 /* I2C0 function */
406 MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false)
407 MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false)
5a4b1315
SR		 408 /* EMAC function */
409 MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false)
410 MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false)
411 MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false)
412 MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false)
413 MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false)
414 MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false)
415 MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false)
416 MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false)
417 MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false)
418 MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false)
419 MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false)
420 MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false)
421 MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false)
422 MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false)
423 MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false)
53ca5c91
SR		 424 MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false)
425 MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false)
2206771c
C		 426 MUX_CFG(DA850, RMII_TXD_0, 14, 12, 15, 8, false)
427 MUX_CFG(DA850, RMII_TXD_1, 14, 8, 15, 8, false)
428 MUX_CFG(DA850, RMII_TXEN, 14, 16, 15, 8, false)
429 MUX_CFG(DA850, RMII_CRS_DV, 15, 4, 15, 8, false)
430 MUX_CFG(DA850, RMII_RXD_0, 14, 24, 15, 8, false)
431 MUX_CFG(DA850, RMII_RXD_1, 14, 20, 15, 8, false)
432 MUX_CFG(DA850, RMII_RXER, 14, 28, 15, 8, false)
433 MUX_CFG(DA850, RMII_MHZ_50_CLK, 15, 0, 15, 0, false)
491214e1
C		 434 /* McASP function */
435 MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false)
436 MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false)
437 MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false)
438 MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false)
439 MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false)
440 MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false)
441 MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false)
442 MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false)
443 MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false)
444 MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false)
445 MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false)
446 MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false)
447 MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false)
448 MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false)
449 MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false)
450 MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false)
451 MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false)
452 MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false)
453 MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false)
454 MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false)
455 MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false)
456 MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false)
457 MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false)
5cbdf276
SR		 458 /* LCD function */
459 MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false)
460 MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false)
461 MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false)
462 MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false)
463 MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false)
464 MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false)
465 MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false)
466 MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false)
467 MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false)
468 MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false)
469 MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false)
470 MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false)
471 MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false)
472 MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false)
473 MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false)
474 MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false)
475 MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false)
476 MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false)
477 MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false)
478 MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false)
700691f2
SR		 479 /* MMC/SD0 function */
480 MUX_CFG(DA850, MMCSD0_DAT_0, 10, 8, 15, 2, false)
481 MUX_CFG(DA850, MMCSD0_DAT_1, 10, 12, 15, 2, false)
482 MUX_CFG(DA850, MMCSD0_DAT_2, 10, 16, 15, 2, false)
483 MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false)
484 MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false)
485 MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false)
38beb929
SR		 486 /* EMIF2.5/EMIFA function */
487 MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false)
488 MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false)
489 MUX_CFG(DA850, EMA_D_5, 9, 8, 15, 1, false)
490 MUX_CFG(DA850, EMA_D_4, 9, 12, 15, 1, false)
491 MUX_CFG(DA850, EMA_D_3, 9, 16, 15, 1, false)
492 MUX_CFG(DA850, EMA_D_2, 9, 20, 15, 1, false)
493 MUX_CFG(DA850, EMA_D_1, 9, 24, 15, 1, false)
494 MUX_CFG(DA850, EMA_D_0, 9, 28, 15, 1, false)
495 MUX_CFG(DA850, EMA_A_1, 12, 24, 15, 1, false)
496 MUX_CFG(DA850, EMA_A_2, 12, 20, 15, 1, false)
497 MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false)
498 MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false)
499 MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false)
500 MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false)
7c5ec609
SR		 501 MUX_CFG(DA850, EMA_A_0, 12, 28, 15, 1, false)
502 MUX_CFG(DA850, EMA_A_3, 12, 16, 15, 1, false)
503 MUX_CFG(DA850, EMA_A_4, 12, 12, 15, 1, false)
504 MUX_CFG(DA850, EMA_A_5, 12, 8, 15, 1, false)
505 MUX_CFG(DA850, EMA_A_6, 12, 4, 15, 1, false)
506 MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false)
507 MUX_CFG(DA850, EMA_A_8, 11, 28, 15, 1, false)
508 MUX_CFG(DA850, EMA_A_9, 11, 24, 15, 1, false)
509 MUX_CFG(DA850, EMA_A_10, 11, 20, 15, 1, false)
510 MUX_CFG(DA850, EMA_A_11, 11, 16, 15, 1, false)
511 MUX_CFG(DA850, EMA_A_12, 11, 12, 15, 1, false)
512 MUX_CFG(DA850, EMA_A_13, 11, 8, 15, 1, false)
513 MUX_CFG(DA850, EMA_A_14, 11, 4, 15, 1, false)
514 MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false)
515 MUX_CFG(DA850, EMA_A_16, 10, 28, 15, 1, false)
516 MUX_CFG(DA850, EMA_A_17, 10, 24, 15, 1, false)
517 MUX_CFG(DA850, EMA_A_18, 10, 20, 15, 1, false)
518 MUX_CFG(DA850, EMA_A_19, 10, 16, 15, 1, false)
519 MUX_CFG(DA850, EMA_A_20, 10, 12, 15, 1, false)
520 MUX_CFG(DA850, EMA_A_21, 10, 8, 15, 1, false)
521 MUX_CFG(DA850, EMA_A_22, 10, 4, 15, 1, false)
522 MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false)
523 MUX_CFG(DA850, EMA_D_8, 8, 28, 15, 1, false)
524 MUX_CFG(DA850, EMA_D_9, 8, 24, 15, 1, false)
525 MUX_CFG(DA850, EMA_D_10, 8, 20, 15, 1, false)
526 MUX_CFG(DA850, EMA_D_11, 8, 16, 15, 1, false)
527 MUX_CFG(DA850, EMA_D_12, 8, 12, 15, 1, false)
528 MUX_CFG(DA850, EMA_D_13, 8, 8, 15, 1, false)
529 MUX_CFG(DA850, EMA_D_14, 8, 4, 15, 1, false)
530 MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false)
531 MUX_CFG(DA850, EMA_BA_1, 5, 24, 15, 1, false)
532 MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false)
533 MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false)
534 MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false)
5cbdf276 535 /* GPIO function */
2206771c 536 MUX_CFG(DA850, GPIO2_6, 6, 4, 15, 8, false)
7761ef67 537 MUX_CFG(DA850, GPIO2_8, 5, 28, 15, 8, false)
5cbdf276 538 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false)
700691f2
SR		 539 MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false)
540 MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false)
044ca015 541 MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false)
e1a8d7e2
SR		 542#endif
543};
544
545const short da850_uart0_pins[] __initdata = {
546 DA850_NUART0_CTS, DA850_NUART0_RTS, DA850_UART0_RXD, DA850_UART0_TXD,
547 -1
548};
549
550const short da850_uart1_pins[] __initdata = {
551 DA850_UART1_RXD, DA850_UART1_TXD,
552 -1
553};
554
555const short da850_uart2_pins[] __initdata = {
556 DA850_UART2_RXD, DA850_UART2_TXD,
557 -1
558};
559
560const short da850_i2c0_pins[] __initdata = {
561 DA850_I2C0_SDA, DA850_I2C0_SCL,
562 -1
563};
564
565const short da850_i2c1_pins[] __initdata = {
566 DA850_I2C1_SCL, DA850_I2C1_SDA,
567 -1
568};
569
5a4b1315
SR		 570const short da850_cpgmac_pins[] __initdata = {
571 DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
572 DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
573 DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
53ca5c91
SR		 574 DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
575 DA850_MDIO_D,
5a4b1315
SR		 576 -1
577};
578
2206771c
C		 579const short da850_rmii_pins[] __initdata = {
580 DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
581 DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
582 DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
583 DA850_MDIO_D,
584 -1
585};
586
491214e1
C		 587const short da850_mcasp_pins[] __initdata = {
588 DA850_AHCLKX, DA850_ACLKX, DA850_AFSX,
589 DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE,
590 DA850_AXR_11, DA850_AXR_12,
591 -1
592};
593
5cbdf276 594const short da850_lcdcntl_pins[] __initdata = {
7761ef67
SR		 595 DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
596 DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
597 DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11,
598 DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15,
599 DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS,
5cbdf276
SR		 600 -1
601};
602
700691f2
SR		 603const short da850_mmcsd0_pins[] __initdata = {
604 DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2,
605 DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD,
606 DA850_GPIO4_0, DA850_GPIO4_1,
607 -1
608};
609
38beb929
SR		 610const short da850_nand_pins[] __initdata = {
611 DA850_EMA_D_7, DA850_EMA_D_6, DA850_EMA_D_5, DA850_EMA_D_4,
612 DA850_EMA_D_3, DA850_EMA_D_2, DA850_EMA_D_1, DA850_EMA_D_0,
613 DA850_EMA_A_1, DA850_EMA_A_2, DA850_NEMA_CS_3, DA850_NEMA_CS_4,
614 DA850_NEMA_WE, DA850_NEMA_OE,
615 -1
616};
617
7c5ec609
SR		 618const short da850_nor_pins[] __initdata = {
619 DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2,
620 DA850_NEMA_WE, DA850_NEMA_OE, DA850_EMA_D_0, DA850_EMA_D_1,
621 DA850_EMA_D_2, DA850_EMA_D_3, DA850_EMA_D_4, DA850_EMA_D_5,
622 DA850_EMA_D_6, DA850_EMA_D_7, DA850_EMA_D_8, DA850_EMA_D_9,
623 DA850_EMA_D_10, DA850_EMA_D_11, DA850_EMA_D_12, DA850_EMA_D_13,
624 DA850_EMA_D_14, DA850_EMA_D_15, DA850_EMA_A_0, DA850_EMA_A_1,
625 DA850_EMA_A_2, DA850_EMA_A_3, DA850_EMA_A_4, DA850_EMA_A_5,
626 DA850_EMA_A_6, DA850_EMA_A_7, DA850_EMA_A_8, DA850_EMA_A_9,
627 DA850_EMA_A_10, DA850_EMA_A_11, DA850_EMA_A_12, DA850_EMA_A_13,
628 DA850_EMA_A_14, DA850_EMA_A_15, DA850_EMA_A_16, DA850_EMA_A_17,
629 DA850_EMA_A_18, DA850_EMA_A_19, DA850_EMA_A_20, DA850_EMA_A_21,
630 DA850_EMA_A_22, DA850_EMA_A_23,
631 -1
632};
633
e1a8d7e2
SR		 634/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
635static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
636 [IRQ_DA8XX_COMMTX] = 7,
637 [IRQ_DA8XX_COMMRX] = 7,
638 [IRQ_DA8XX_NINT] = 7,
639 [IRQ_DA8XX_EVTOUT0] = 7,
640 [IRQ_DA8XX_EVTOUT1] = 7,
641 [IRQ_DA8XX_EVTOUT2] = 7,
642 [IRQ_DA8XX_EVTOUT3] = 7,
643 [IRQ_DA8XX_EVTOUT4] = 7,
644 [IRQ_DA8XX_EVTOUT5] = 7,
645 [IRQ_DA8XX_EVTOUT6] = 7,
e1a8d7e2
SR		 646 [IRQ_DA8XX_EVTOUT7] = 7,
647 [IRQ_DA8XX_CCINT0] = 7,
648 [IRQ_DA8XX_CCERRINT] = 7,
649 [IRQ_DA8XX_TCERRINT0] = 7,
650 [IRQ_DA8XX_AEMIFINT] = 7,
651 [IRQ_DA8XX_I2CINT0] = 7,
652 [IRQ_DA8XX_MMCSDINT0] = 7,
653 [IRQ_DA8XX_MMCSDINT1] = 7,
654 [IRQ_DA8XX_ALLINT0] = 7,
655 [IRQ_DA8XX_RTC] = 7,
656 [IRQ_DA8XX_SPINT0] = 7,
657 [IRQ_DA8XX_TINT12_0] = 7,
658 [IRQ_DA8XX_TINT34_0] = 7,
659 [IRQ_DA8XX_TINT12_1] = 7,
660 [IRQ_DA8XX_TINT34_1] = 7,
661 [IRQ_DA8XX_UARTINT0] = 7,
662 [IRQ_DA8XX_KEYMGRINT] = 7,
e1a8d7e2 663 [IRQ_DA850_MPUADDRERR0] = 7,
e1a8d7e2
SR		 664 [IRQ_DA8XX_CHIPINT0] = 7,
665 [IRQ_DA8XX_CHIPINT1] = 7,
666 [IRQ_DA8XX_CHIPINT2] = 7,
667 [IRQ_DA8XX_CHIPINT3] = 7,
668 [IRQ_DA8XX_TCERRINT1] = 7,
669 [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7,
670 [IRQ_DA8XX_C0_RX_PULSE] = 7,
671 [IRQ_DA8XX_C0_TX_PULSE] = 7,
672 [IRQ_DA8XX_C0_MISC_PULSE] = 7,
673 [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7,
674 [IRQ_DA8XX_C1_RX_PULSE] = 7,
675 [IRQ_DA8XX_C1_TX_PULSE] = 7,
676 [IRQ_DA8XX_C1_MISC_PULSE] = 7,
677 [IRQ_DA8XX_MEMERR] = 7,
678 [IRQ_DA8XX_GPIO0] = 7,
679 [IRQ_DA8XX_GPIO1] = 7,
680 [IRQ_DA8XX_GPIO2] = 7,
681 [IRQ_DA8XX_GPIO3] = 7,
682 [IRQ_DA8XX_GPIO4] = 7,
683 [IRQ_DA8XX_GPIO5] = 7,
684 [IRQ_DA8XX_GPIO6] = 7,
685 [IRQ_DA8XX_GPIO7] = 7,
686 [IRQ_DA8XX_GPIO8] = 7,
687 [IRQ_DA8XX_I2CINT1] = 7,
688 [IRQ_DA8XX_LCDINT] = 7,
689 [IRQ_DA8XX_UARTINT1] = 7,
690 [IRQ_DA8XX_MCASPINT] = 7,
691 [IRQ_DA8XX_ALLINT1] = 7,
692 [IRQ_DA8XX_SPINT1] = 7,
693 [IRQ_DA8XX_UHPI_INT1] = 7,
694 [IRQ_DA8XX_USB_INT] = 7,
695 [IRQ_DA8XX_IRQN] = 7,
696 [IRQ_DA8XX_RWAKEUP] = 7,
697 [IRQ_DA8XX_UARTINT2] = 7,
698 [IRQ_DA8XX_DFTSSINT] = 7,
699 [IRQ_DA8XX_EHRPWM0] = 7,
700 [IRQ_DA8XX_EHRPWM0TZ] = 7,
701 [IRQ_DA8XX_EHRPWM1] = 7,
702 [IRQ_DA8XX_EHRPWM1TZ] = 7,
703 [IRQ_DA850_SATAINT] = 7,
e1a8d7e2
SR		 704 [IRQ_DA850_TINTALL_2] = 7,
705 [IRQ_DA8XX_ECAP0] = 7,
706 [IRQ_DA8XX_ECAP1] = 7,
707 [IRQ_DA8XX_ECAP2] = 7,
708 [IRQ_DA850_MMCSDINT0_1] = 7,
709 [IRQ_DA850_MMCSDINT1_1] = 7,
710 [IRQ_DA850_T12CMPINT0_2] = 7,
711 [IRQ_DA850_T12CMPINT1_2] = 7,
712 [IRQ_DA850_T12CMPINT2_2] = 7,
713 [IRQ_DA850_T12CMPINT3_2] = 7,
714 [IRQ_DA850_T12CMPINT4_2] = 7,
715 [IRQ_DA850_T12CMPINT5_2] = 7,
716 [IRQ_DA850_T12CMPINT6_2] = 7,
717 [IRQ_DA850_T12CMPINT7_2] = 7,
718 [IRQ_DA850_T12CMPINT0_3] = 7,
719 [IRQ_DA850_T12CMPINT1_3] = 7,
720 [IRQ_DA850_T12CMPINT2_3] = 7,
721 [IRQ_DA850_T12CMPINT3_3] = 7,
722 [IRQ_DA850_T12CMPINT4_3] = 7,
723 [IRQ_DA850_T12CMPINT5_3] = 7,
724 [IRQ_DA850_T12CMPINT6_3] = 7,
725 [IRQ_DA850_T12CMPINT7_3] = 7,
726 [IRQ_DA850_RPIINT] = 7,
727 [IRQ_DA850_VPIFINT] = 7,
728 [IRQ_DA850_CCINT1] = 7,
729 [IRQ_DA850_CCERRINT1] = 7,
730 [IRQ_DA850_TCERRINT2] = 7,
e1a8d7e2
SR		 731 [IRQ_DA850_TINTALL_3] = 7,
732 [IRQ_DA850_MCBSP0RINT] = 7,
733 [IRQ_DA850_MCBSP0XINT] = 7,
734 [IRQ_DA850_MCBSP1RINT] = 7,
735 [IRQ_DA850_MCBSP1XINT] = 7,
736 [IRQ_DA8XX_ARMCLKSTOPREQ] = 7,
737};
738
739static struct map_desc da850_io_desc[] = {
740 {
741 .virtual = IO_VIRT,
742 .pfn = __phys_to_pfn(IO_PHYS),
743 .length = IO_SIZE,
744 .type = MT_DEVICE
745 },
746 {
747 .virtual = DA8XX_CP_INTC_VIRT,
748 .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE),
749 .length = DA8XX_CP_INTC_SIZE,
750 .type = MT_DEVICE
751 },
60cd02e1
SN		 752 {
753 .virtual = SRAM_VIRT,
754 .pfn = __phys_to_pfn(DA8XX_ARM_RAM_BASE),
755 .length = SZ_8K,
756 .type = MT_DEVICE
757 },
e1a8d7e2
SR		 758};
759
e4c822c7 760static u32 da850_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE };
e1a8d7e2
SR		 761
762/* Contents of JTAG ID register used to identify exact cpu type */
763static struct davinci_id da850_ids[] = {
764 {
765 .variant = 0x0,
766 .part_no = 0xb7d1,
767 .manufacturer = 0x017, /* 0x02f >> 1 */
768 .cpu_id = DAVINCI_CPU_ID_DA850,
769 .name = "da850/omap-l138",
770 },
771};
772
773static struct davinci_timer_instance da850_timer_instance[4] = {
774 {
1bcd38ad 775 .base = DA8XX_TIMER64P0_BASE,
e1a8d7e2
SR		 776 .bottom_irq = IRQ_DA8XX_TINT12_0,
777 .top_irq = IRQ_DA8XX_TINT34_0,
778 },
779 {
1bcd38ad 780 .base = DA8XX_TIMER64P1_BASE,
e1a8d7e2
SR		 781 .bottom_irq = IRQ_DA8XX_TINT12_1,
782 .top_irq = IRQ_DA8XX_TINT34_1,
783 },
784 {
1bcd38ad 785 .base = DA850_TIMER64P2_BASE,
e1a8d7e2
SR		 786 .bottom_irq = IRQ_DA850_TINT12_2,
787 .top_irq = IRQ_DA850_TINT34_2,
788 },
789 {
1bcd38ad 790 .base = DA850_TIMER64P3_BASE,
e1a8d7e2
SR		 791 .bottom_irq = IRQ_DA850_TINT12_3,
792 .top_irq = IRQ_DA850_TINT34_3,
793 },
794};
795
796/*
797 * T0_BOT: Timer 0, bottom : Used for clock_event
798 * T0_TOP: Timer 0, top : Used for clocksource
799 * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
800 */
801static struct davinci_timer_info da850_timer_info = {
802 .timers = da850_timer_instance,
803 .clockevent_id = T0_BOT,
804 .clocksource_id = T0_TOP,
805};
806
5d36a332
SN		 807static void da850_set_async3_src(int pllnum)
808{
809 struct clk *clk, *newparent = pllnum ? &pll1_sysclk2 : &pll0_sysclk2;
08aca087 810 struct clk_lookup *c;
5d36a332
SN		 811 unsigned int v;
812 int ret;
813
08aca087
KH		 814 for (c = da850_clks; c->clk; c++) {
815 clk = c->clk;
5d36a332
SN		 816 if (clk->flags & DA850_CLK_ASYNC3) {
817 ret = clk_set_parent(clk, newparent);
818 WARN(ret, "DA850: unable to re-parent clock %s",
819 clk->name);
820 }
821 }
822
d2de0582 823 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
5d36a332
SN		 824 if (pllnum)
825 v |= CFGCHIP3_ASYNC3_CLKSRC;
826 else
827 v &= ~CFGCHIP3_ASYNC3_CLKSRC;
d2de0582 828 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
5d36a332
SN		 829}
830
683b1e1f
SN		 831#ifdef CONFIG_CPU_FREQ
832/*
833 * Notes:
834 * According to the TRM, minimum PLLM results in maximum power savings.
835 * The OPP definitions below should keep the PLLM as low as possible.
836 *
837 * The output of the PLLM must be between 400 to 600 MHz.
838 * This rules out prediv of anything but divide-by-one for 24Mhz OSC input.
839 */
840struct da850_opp {
841 unsigned int freq; /* in KHz */
842 unsigned int prediv;
843 unsigned int mult;
844 unsigned int postdiv;
35f9acd8
SN		 845 unsigned int cvdd_min; /* in uV */
846 unsigned int cvdd_max; /* in uV */
683b1e1f
SN		 847};
848
849static const struct da850_opp da850_opp_300 = {
850 .freq = 300000,
851 .prediv = 1,
852 .mult = 25,
853 .postdiv = 2,
35f9acd8
SN		 854 .cvdd_min = 1140000,
855 .cvdd_max = 1320000,
683b1e1f
SN		 856};
857
858static const struct da850_opp da850_opp_200 = {
859 .freq = 200000,
860 .prediv = 1,
861 .mult = 25,
862 .postdiv = 3,
35f9acd8
SN		 863 .cvdd_min = 1050000,
864 .cvdd_max = 1160000,
683b1e1f
SN		 865};
866
867static const struct da850_opp da850_opp_96 = {
868 .freq = 96000,
869 .prediv = 1,
870 .mult = 20,
871 .postdiv = 5,
35f9acd8
SN		 872 .cvdd_min = 950000,
873 .cvdd_max = 1050000,
683b1e1f
SN		 874};
875
876#define OPP(freq) \
877 { \
878 .index = (unsigned int) &da850_opp_##freq, \
879 .frequency = freq * 1000, \
880 }
881
882static struct cpufreq_frequency_table da850_freq_table[] = {
883 OPP(300),
884 OPP(200),
885 OPP(96),
886 {
887 .index = 0,
888 .frequency = CPUFREQ_TABLE_END,
889 },
890};
891
13d5e27a
SN		 892#ifdef CONFIG_REGULATOR
893static struct regulator *cvdd;
894
895static int da850_set_voltage(unsigned int index)
896{
897 struct da850_opp *opp;
898
899 if (!cvdd)
900 return -ENODEV;
901
902 opp = (struct da850_opp *) da850_freq_table[index].index;
903
904 return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
905}
906
907static int da850_regulator_init(void)
908{
909 cvdd = regulator_get(NULL, "cvdd");
910 if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;"
911 " voltage scaling unsupported\n")) {
912 return PTR_ERR(cvdd);
913 }
914
915 return 0;
916}
917#endif
918
683b1e1f
SN		 919static struct davinci_cpufreq_config cpufreq_info = {
920 .freq_table = &da850_freq_table[0],
13d5e27a
SN		 921#ifdef CONFIG_REGULATOR
922 .init = da850_regulator_init,
923 .set_voltage = da850_set_voltage,
924#endif
683b1e1f
SN		 925};
926
927static struct platform_device da850_cpufreq_device = {
928 .name = "cpufreq-davinci",
929 .dev = {
930 .platform_data = &cpufreq_info,
931 },
932};
933
934int __init da850_register_cpufreq(void)
935{
936 return platform_device_register(&da850_cpufreq_device);
937}
938
939static int da850_round_armrate(struct clk *clk, unsigned long rate)
940{
941 int i, ret = 0, diff;
942 unsigned int best = (unsigned int) -1;
943
944 rate /= 1000; /* convert to kHz */
945
946 for (i = 0; da850_freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
947 diff = da850_freq_table[i].frequency - rate;
948 if (diff < 0)
949 diff = -diff;
950
951 if (diff < best) {
952 best = diff;
953 ret = da850_freq_table[i].frequency;
954 }
955 }
956
957 return ret * 1000;
958}
959
960static int da850_set_armrate(struct clk *clk, unsigned long index)
961{
962 struct clk *pllclk = &pll0_clk;
963
964 return clk_set_rate(pllclk, index);
965}
966
967static int da850_set_pll0rate(struct clk *clk, unsigned long index)
968{
969 unsigned int prediv, mult, postdiv;
970 struct da850_opp *opp;
971 struct pll_data *pll = clk->pll_data;
683b1e1f
SN		 972 int ret;
973
974 opp = (struct da850_opp *) da850_freq_table[index].index;
975 prediv = opp->prediv;
976 mult = opp->mult;
977 postdiv = opp->postdiv;
978
683b1e1f
SN		 979 ret = davinci_set_pllrate(pll, prediv, mult, postdiv);
980 if (WARN_ON(ret))
981 return ret;
982
983 return 0;
984}
985#else
986int __init da850_register_cpufreq(void)
987{
988 return 0;
989}
990
991static int da850_set_armrate(struct clk *clk, unsigned long rate)
992{
993 return -EINVAL;
994}
995
996static int da850_set_pll0rate(struct clk *clk, unsigned long armrate)
997{
998 return -EINVAL;
999}
1000
1001static int da850_round_armrate(struct clk *clk, unsigned long rate)
1002{
1003 return clk->rate;
1004}
1005#endif
1006
044ca015
SN		 1007int da850_register_pm(struct platform_device *pdev)
1008{
1009 int ret;
1010 struct davinci_pm_config *pdata = pdev->dev.platform_data;
1011
1012 ret = davinci_cfg_reg(DA850_RTC_ALARM);
1013 if (ret)
1014 return ret;
1015
1016 pdata->ddr2_ctlr_base = da8xx_get_mem_ctlr();
1017 pdata->deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG);
1018 pdata->ddrpsc_num = DA8XX_LPSC1_EMIF3C;
1019
1020 pdata->cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K);
1021 if (!pdata->cpupll_reg_base)
1022 return -ENOMEM;
1023
1024 pdata->ddrpll_reg_base = ioremap(DA8XX_PLL1_BASE, SZ_4K);
1025 if (!pdata->ddrpll_reg_base) {
1026 ret = -ENOMEM;
1027 goto no_ddrpll_mem;
1028 }
1029
1030 pdata->ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K);
1031 if (!pdata->ddrpsc_reg_base) {
1032 ret = -ENOMEM;
1033 goto no_ddrpsc_mem;
1034 }
1035
1036 return platform_device_register(pdev);
1037
1038no_ddrpsc_mem:
1039 iounmap(pdata->ddrpll_reg_base);
1040no_ddrpll_mem:
1041 iounmap(pdata->cpupll_reg_base);
1042 return ret;
1043}
35f9acd8 1044
e1a8d7e2
SR		 1045static struct davinci_soc_info davinci_soc_info_da850 = {
1046 .io_desc = da850_io_desc,
1047 .io_desc_num = ARRAY_SIZE(da850_io_desc),
3347db83 1048 .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
e1a8d7e2
SR		 1049 .ids = da850_ids,
1050 .ids_num = ARRAY_SIZE(da850_ids),
1051 .cpu_clks = da850_clks,
1052 .psc_bases = da850_psc_bases,
1053 .psc_bases_num = ARRAY_SIZE(da850_psc_bases),
779b0d53 1054 .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
e1a8d7e2
SR		 1055 .pinmux_pins = da850_pins,
1056 .pinmux_pins_num = ARRAY_SIZE(da850_pins),
bd808947 1057 .intc_base = DA8XX_CP_INTC_BASE,
e1a8d7e2
SR		 1058 .intc_type = DAVINCI_INTC_TYPE_CP_INTC,
1059 .intc_irq_prios = da850_default_priorities,
1060 .intc_irq_num = DA850_N_CP_INTC_IRQ,
1061 .timer_info = &da850_timer_info,
686b634a 1062 .gpio_type = GPIO_TYPE_DAVINCI,
b8d44293 1063 .gpio_base = DA8XX_GPIO_BASE,
5a8d5441 1064 .gpio_num = 144,
e1a8d7e2
SR		 1065 .gpio_irq = IRQ_DA8XX_GPIO0,
1066 .serial_dev = &da8xx_serial_device,
1067 .emac_pdata = &da8xx_emac_pdata,
60cd02e1
SN		 1068 .sram_dma = DA8XX_ARM_RAM_BASE,
1069 .sram_len = SZ_8K,
c78a5bc2 1070 .reset_device = &da8xx_wdt_device,
e1a8d7e2
SR		 1071};
1072
1073void __init da850_init(void)
1074{
7aad472b
SN		 1075 unsigned int v;
1076
bcd6a1c6
CC		 1077 davinci_common_init(&davinci_soc_info_da850);
1078
d2de0582
SN		 1079 da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
1080 if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
1081 return;
1082
1083 da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K);
1084 if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
6a28adef
SN		 1085 return;
1086
5d36a332
SN		 1087 /*
1088 * Move the clock source of Async3 domain to PLL1 SYSCLK2.
1089 * This helps keeping the peripherals on this domain insulated
1090 * from CPU frequency changes caused by DVFS. The firmware sets
1091 * both PLL0 and PLL1 to the same frequency so, there should not
1092 * be any noticible change even in non-DVFS use cases.
1093 */
1094 da850_set_async3_src(1);
7aad472b
SN		 1095
1096 /* Unlock writing to PLL0 registers */
1097 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1098 v &= ~CFGCHIP0_PLL_MASTER_LOCK;
1099 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1100
1101 /* Unlock writing to PLL1 registers */
1102 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
1103 v &= ~CFGCHIP3_PLL1_MASTER_LOCK;
1104 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
e1a8d7e2 1105}
Linux kernel - Deliverables
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