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davinci: MMC/SD support for Omapl138-Hawkboard
[deliverable/linux.git] / arch / arm / mach-davinci / da850.c
CommitLineData
e1a8d7e2
SR		 1/*
2 * TI DA850/OMAP-L138 chip specific setup
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Derived from: arch/arm/mach-davinci/da830.c
7 * Original Copyrights follow:
8 *
9 * 2009 (c) MontaVista Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
e1a8d7e2
SR		 14#include <linux/init.h>
15#include <linux/clk.h>
16#include <linux/platform_device.h>
683b1e1f 17#include <linux/cpufreq.h>
35f9acd8 18#include <linux/regulator/consumer.h>
e1a8d7e2
SR		 19
20#include <asm/mach/map.h>
21
e1a8d7e2 22#include <mach/psc.h>
e1a8d7e2
SR		 23#include <mach/irqs.h>
24#include <mach/cputype.h>
25#include <mach/common.h>
26#include <mach/time.h>
27#include <mach/da8xx.h>
683b1e1f 28#include <mach/cpufreq.h>
044ca015 29#include <mach/pm.h>
686b634a 30#include <mach/gpio.h>
e1a8d7e2
SR		 31
32#include "clock.h"
33#include "mux.h"
34
5d36a332
SN		 35/* SoC specific clock flags */
36#define DA850_CLK_ASYNC3 BIT(16)
37
e1a8d7e2
SR		 38#define DA850_PLL1_BASE 0x01e1a000
39#define DA850_TIMER64P2_BASE 0x01f0c000
40#define DA850_TIMER64P3_BASE 0x01f0d000
41
42#define DA850_REF_FREQ 24000000
43
5d36a332 44#define CFGCHIP3_ASYNC3_CLKSRC BIT(4)
7aad472b 45#define CFGCHIP3_PLL1_MASTER_LOCK BIT(5)
683b1e1f
SN		 46#define CFGCHIP0_PLL_MASTER_LOCK BIT(4)
47
48static int da850_set_armrate(struct clk *clk, unsigned long rate);
49static int da850_round_armrate(struct clk *clk, unsigned long rate);
50static int da850_set_pll0rate(struct clk *clk, unsigned long armrate);
5d36a332 51
e1a8d7e2
SR		 52static struct pll_data pll0_data = {
53 .num = 1,
54 .phys_base = DA8XX_PLL0_BASE,
55 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
56};
57
58static struct clk ref_clk = {
59 .name = "ref_clk",
60 .rate = DA850_REF_FREQ,
61};
62
63static struct clk pll0_clk = {
64 .name = "pll0",
65 .parent = &ref_clk,
66 .pll_data = &pll0_data,
67 .flags = CLK_PLL,
683b1e1f 68 .set_rate = da850_set_pll0rate,
e1a8d7e2
SR		 69};
70
71static struct clk pll0_aux_clk = {
72 .name = "pll0_aux_clk",
73 .parent = &pll0_clk,
74 .flags = CLK_PLL | PRE_PLL,
75};
76
77static struct clk pll0_sysclk2 = {
78 .name = "pll0_sysclk2",
79 .parent = &pll0_clk,
80 .flags = CLK_PLL,
81 .div_reg = PLLDIV2,
82};
83
84static struct clk pll0_sysclk3 = {
85 .name = "pll0_sysclk3",
86 .parent = &pll0_clk,
87 .flags = CLK_PLL,
88 .div_reg = PLLDIV3,
b987c4b2
SN		 89 .set_rate = davinci_set_sysclk_rate,
90 .maxrate = 100000000,
e1a8d7e2
SR		 91};
92
93static struct clk pll0_sysclk4 = {
94 .name = "pll0_sysclk4",
95 .parent = &pll0_clk,
96 .flags = CLK_PLL,
97 .div_reg = PLLDIV4,
98};
99
100static struct clk pll0_sysclk5 = {
101 .name = "pll0_sysclk5",
102 .parent = &pll0_clk,
103 .flags = CLK_PLL,
104 .div_reg = PLLDIV5,
105};
106
107static struct clk pll0_sysclk6 = {
108 .name = "pll0_sysclk6",
109 .parent = &pll0_clk,
110 .flags = CLK_PLL,
111 .div_reg = PLLDIV6,
112};
113
114static struct clk pll0_sysclk7 = {
115 .name = "pll0_sysclk7",
116 .parent = &pll0_clk,
117 .flags = CLK_PLL,
118 .div_reg = PLLDIV7,
119};
120
121static struct pll_data pll1_data = {
122 .num = 2,
123 .phys_base = DA850_PLL1_BASE,
124 .flags = PLL_HAS_POSTDIV,
125};
126
127static struct clk pll1_clk = {
128 .name = "pll1",
129 .parent = &ref_clk,
130 .pll_data = &pll1_data,
131 .flags = CLK_PLL,
132};
133
134static struct clk pll1_aux_clk = {
135 .name = "pll1_aux_clk",
136 .parent = &pll1_clk,
137 .flags = CLK_PLL | PRE_PLL,
138};
139
140static struct clk pll1_sysclk2 = {
141 .name = "pll1_sysclk2",
142 .parent = &pll1_clk,
143 .flags = CLK_PLL,
144 .div_reg = PLLDIV2,
145};
146
147static struct clk pll1_sysclk3 = {
148 .name = "pll1_sysclk3",
149 .parent = &pll1_clk,
150 .flags = CLK_PLL,
151 .div_reg = PLLDIV3,
152};
153
154static struct clk pll1_sysclk4 = {
155 .name = "pll1_sysclk4",
156 .parent = &pll1_clk,
157 .flags = CLK_PLL,
158 .div_reg = PLLDIV4,
159};
160
161static struct clk pll1_sysclk5 = {
162 .name = "pll1_sysclk5",
163 .parent = &pll1_clk,
164 .flags = CLK_PLL,
165 .div_reg = PLLDIV5,
166};
167
168static struct clk pll1_sysclk6 = {
169 .name = "pll0_sysclk6",
170 .parent = &pll0_clk,
171 .flags = CLK_PLL,
172 .div_reg = PLLDIV6,
173};
174
175static struct clk pll1_sysclk7 = {
176 .name = "pll1_sysclk7",
177 .parent = &pll1_clk,
178 .flags = CLK_PLL,
179 .div_reg = PLLDIV7,
180};
181
182static struct clk i2c0_clk = {
183 .name = "i2c0",
184 .parent = &pll0_aux_clk,
185};
186
187static struct clk timerp64_0_clk = {
188 .name = "timer0",
189 .parent = &pll0_aux_clk,
190};
191
192static struct clk timerp64_1_clk = {
193 .name = "timer1",
194 .parent = &pll0_aux_clk,
195};
196
197static struct clk arm_rom_clk = {
198 .name = "arm_rom",
199 .parent = &pll0_sysclk2,
200 .lpsc = DA8XX_LPSC0_ARM_RAM_ROM,
201 .flags = ALWAYS_ENABLED,
202};
203
204static struct clk tpcc0_clk = {
205 .name = "tpcc0",
206 .parent = &pll0_sysclk2,
207 .lpsc = DA8XX_LPSC0_TPCC,
208 .flags = ALWAYS_ENABLED | CLK_PSC,
209};
210
211static struct clk tptc0_clk = {
212 .name = "tptc0",
213 .parent = &pll0_sysclk2,
214 .lpsc = DA8XX_LPSC0_TPTC0,
215 .flags = ALWAYS_ENABLED,
216};
217
218static struct clk tptc1_clk = {
219 .name = "tptc1",
220 .parent = &pll0_sysclk2,
221 .lpsc = DA8XX_LPSC0_TPTC1,
222 .flags = ALWAYS_ENABLED,
223};
224
225static struct clk tpcc1_clk = {
226 .name = "tpcc1",
227 .parent = &pll0_sysclk2,
228 .lpsc = DA850_LPSC1_TPCC1,
789a785e 229 .gpsc = 1,
e1a8d7e2 230 .flags = CLK_PSC | ALWAYS_ENABLED,
e1a8d7e2
SR		 231};
232
233static struct clk tptc2_clk = {
234 .name = "tptc2",
235 .parent = &pll0_sysclk2,
236 .lpsc = DA850_LPSC1_TPTC2,
789a785e 237 .gpsc = 1,
e1a8d7e2 238 .flags = ALWAYS_ENABLED,
e1a8d7e2
SR		 239};
240
241static struct clk uart0_clk = {
242 .name = "uart0",
243 .parent = &pll0_sysclk2,
244 .lpsc = DA8XX_LPSC0_UART0,
245};
246
247static struct clk uart1_clk = {
248 .name = "uart1",
249 .parent = &pll0_sysclk2,
250 .lpsc = DA8XX_LPSC1_UART1,
789a785e 251 .gpsc = 1,
5d36a332 252 .flags = DA850_CLK_ASYNC3,
e1a8d7e2
SR		 253};
254
255static struct clk uart2_clk = {
256 .name = "uart2",
257 .parent = &pll0_sysclk2,
258 .lpsc = DA8XX_LPSC1_UART2,
789a785e 259 .gpsc = 1,
5d36a332 260 .flags = DA850_CLK_ASYNC3,
e1a8d7e2
SR		 261};
262
263static struct clk aintc_clk = {
264 .name = "aintc",
265 .parent = &pll0_sysclk4,
266 .lpsc = DA8XX_LPSC0_AINTC,
267 .flags = ALWAYS_ENABLED,
268};
269
270static struct clk gpio_clk = {
271 .name = "gpio",
272 .parent = &pll0_sysclk4,
273 .lpsc = DA8XX_LPSC1_GPIO,
789a785e 274 .gpsc = 1,
e1a8d7e2
SR		 275};
276
277static struct clk i2c1_clk = {
278 .name = "i2c1",
279 .parent = &pll0_sysclk4,
280 .lpsc = DA8XX_LPSC1_I2C,
789a785e 281 .gpsc = 1,
e1a8d7e2
SR		 282};
283
284static struct clk emif3_clk = {
285 .name = "emif3",
286 .parent = &pll0_sysclk5,
287 .lpsc = DA8XX_LPSC1_EMIF3C,
789a785e 288 .gpsc = 1,
e1a8d7e2 289 .flags = ALWAYS_ENABLED,
e1a8d7e2
SR		 290};
291
292static struct clk arm_clk = {
293 .name = "arm",
294 .parent = &pll0_sysclk6,
295 .lpsc = DA8XX_LPSC0_ARM,
296 .flags = ALWAYS_ENABLED,
683b1e1f
SN		 297 .set_rate = da850_set_armrate,
298 .round_rate = da850_round_armrate,
e1a8d7e2
SR		 299};
300
301static struct clk rmii_clk = {
302 .name = "rmii",
303 .parent = &pll0_sysclk7,
304};
305
5a4b1315
SR		 306static struct clk emac_clk = {
307 .name = "emac",
308 .parent = &pll0_sysclk4,
309 .lpsc = DA8XX_LPSC1_CPGMAC,
789a785e 310 .gpsc = 1,
5a4b1315
SR		 311};
312
491214e1
C		 313static struct clk mcasp_clk = {
314 .name = "mcasp",
315 .parent = &pll0_sysclk2,
316 .lpsc = DA8XX_LPSC1_McASP0,
789a785e 317 .gpsc = 1,
51157ed8 318 .flags = DA850_CLK_ASYNC3,
491214e1
C		 319};
320
5cbdf276
SR		 321static struct clk lcdc_clk = {
322 .name = "lcdc",
323 .parent = &pll0_sysclk2,
324 .lpsc = DA8XX_LPSC1_LCDC,
789a785e 325 .gpsc = 1,
5cbdf276
SR		 326};
327
051a6687
JK		 328static struct clk mmcsd0_clk = {
329 .name = "mmcsd0",
700691f2
SR		 330 .parent = &pll0_sysclk2,
331 .lpsc = DA8XX_LPSC0_MMC_SD,
332};
333
051a6687
JK		 334static struct clk mmcsd1_clk = {
335 .name = "mmcsd1",
336 .parent = &pll0_sysclk2,
337 .lpsc = DA850_LPSC1_MMC_SD1,
338 .gpsc = 1,
339};
340
38beb929
SR		 341static struct clk aemif_clk = {
342 .name = "aemif",
343 .parent = &pll0_sysclk3,
344 .lpsc = DA8XX_LPSC0_EMIF25,
345 .flags = ALWAYS_ENABLED,
346};
347
08aca087 348static struct clk_lookup da850_clks[] = {
e1a8d7e2
SR		 349 CLK(NULL, "ref", &ref_clk),
350 CLK(NULL, "pll0", &pll0_clk),
351 CLK(NULL, "pll0_aux", &pll0_aux_clk),
352 CLK(NULL, "pll0_sysclk2", &pll0_sysclk2),
353 CLK(NULL, "pll0_sysclk3", &pll0_sysclk3),
354 CLK(NULL, "pll0_sysclk4", &pll0_sysclk4),
355 CLK(NULL, "pll0_sysclk5", &pll0_sysclk5),
356 CLK(NULL, "pll0_sysclk6", &pll0_sysclk6),
357 CLK(NULL, "pll0_sysclk7", &pll0_sysclk7),
358 CLK(NULL, "pll1", &pll1_clk),
359 CLK(NULL, "pll1_aux", &pll1_aux_clk),
360 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
361 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
362 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
363 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
364 CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
365 CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
366 CLK("i2c_davinci.1", NULL, &i2c0_clk),
367 CLK(NULL, "timer0", &timerp64_0_clk),
368 CLK("watchdog", NULL, &timerp64_1_clk),
369 CLK(NULL, "arm_rom", &arm_rom_clk),
370 CLK(NULL, "tpcc0", &tpcc0_clk),
371 CLK(NULL, "tptc0", &tptc0_clk),
372 CLK(NULL, "tptc1", &tptc1_clk),
373 CLK(NULL, "tpcc1", &tpcc1_clk),
374 CLK(NULL, "tptc2", &tptc2_clk),
375 CLK(NULL, "uart0", &uart0_clk),
376 CLK(NULL, "uart1", &uart1_clk),
377 CLK(NULL, "uart2", &uart2_clk),
378 CLK(NULL, "aintc", &aintc_clk),
379 CLK(NULL, "gpio", &gpio_clk),
380 CLK("i2c_davinci.2", NULL, &i2c1_clk),
381 CLK(NULL, "emif3", &emif3_clk),
382 CLK(NULL, "arm", &arm_clk),
383 CLK(NULL, "rmii", &rmii_clk),
5a4b1315 384 CLK("davinci_emac.1", NULL, &emac_clk),
491214e1 385 CLK("davinci-mcasp.0", NULL, &mcasp_clk),
5cbdf276 386 CLK("da8xx_lcdc.0", NULL, &lcdc_clk),
051a6687
JK		 387 CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
388 CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
38beb929 389 CLK(NULL, "aemif", &aemif_clk),
e1a8d7e2
SR		 390 CLK(NULL, NULL, NULL),
391};
392
393/*
394 * Device specific mux setup
395 *
396 * soc description mux mode mode mux dbg
397 * reg offset mask mode
398 */
399static const struct mux_config da850_pins[] = {
400#ifdef CONFIG_DAVINCI_MUX
401 /* UART0 function */
402 MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false)
403 MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false)
404 MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false)
405 MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false)
406 /* UART1 function */
407 MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false)
408 MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false)
409 /* UART2 function */
410 MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false)
411 MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false)
412 /* I2C1 function */
413 MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false)
414 MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false)
415 /* I2C0 function */
416 MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false)
417 MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false)
5a4b1315
SR		 418 /* EMAC function */
419 MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false)
420 MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false)
421 MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false)
422 MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false)
423 MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false)
424 MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false)
425 MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false)
426 MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false)
427 MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false)
428 MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false)
429 MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false)
430 MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false)
431 MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false)
432 MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false)
433 MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false)
53ca5c91
SR		 434 MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false)
435 MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false)
2206771c
C		 436 MUX_CFG(DA850, RMII_TXD_0, 14, 12, 15, 8, false)
437 MUX_CFG(DA850, RMII_TXD_1, 14, 8, 15, 8, false)
438 MUX_CFG(DA850, RMII_TXEN, 14, 16, 15, 8, false)
439 MUX_CFG(DA850, RMII_CRS_DV, 15, 4, 15, 8, false)
440 MUX_CFG(DA850, RMII_RXD_0, 14, 24, 15, 8, false)
441 MUX_CFG(DA850, RMII_RXD_1, 14, 20, 15, 8, false)
442 MUX_CFG(DA850, RMII_RXER, 14, 28, 15, 8, false)
443 MUX_CFG(DA850, RMII_MHZ_50_CLK, 15, 0, 15, 0, false)
491214e1
C		 444 /* McASP function */
445 MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false)
446 MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false)
447 MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false)
448 MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false)
449 MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false)
450 MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false)
451 MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false)
452 MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false)
453 MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false)
454 MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false)
455 MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false)
456 MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false)
457 MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false)
458 MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false)
459 MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false)
460 MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false)
461 MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false)
462 MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false)
463 MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false)
464 MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false)
465 MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false)
466 MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false)
467 MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false)
5cbdf276
SR		 468 /* LCD function */
469 MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false)
470 MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false)
471 MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false)
472 MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false)
473 MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false)
474 MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false)
475 MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false)
476 MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false)
477 MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false)
478 MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false)
479 MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false)
480 MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false)
481 MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false)
482 MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false)
483 MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false)
484 MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false)
485 MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false)
486 MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false)
487 MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false)
488 MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false)
700691f2
SR		 489 /* MMC/SD0 function */
490 MUX_CFG(DA850, MMCSD0_DAT_0, 10, 8, 15, 2, false)
491 MUX_CFG(DA850, MMCSD0_DAT_1, 10, 12, 15, 2, false)
492 MUX_CFG(DA850, MMCSD0_DAT_2, 10, 16, 15, 2, false)
493 MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false)
494 MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false)
495 MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false)
38beb929
SR		 496 /* EMIF2.5/EMIFA function */
497 MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false)
498 MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false)
499 MUX_CFG(DA850, EMA_D_5, 9, 8, 15, 1, false)
500 MUX_CFG(DA850, EMA_D_4, 9, 12, 15, 1, false)
501 MUX_CFG(DA850, EMA_D_3, 9, 16, 15, 1, false)
502 MUX_CFG(DA850, EMA_D_2, 9, 20, 15, 1, false)
503 MUX_CFG(DA850, EMA_D_1, 9, 24, 15, 1, false)
504 MUX_CFG(DA850, EMA_D_0, 9, 28, 15, 1, false)
505 MUX_CFG(DA850, EMA_A_1, 12, 24, 15, 1, false)
506 MUX_CFG(DA850, EMA_A_2, 12, 20, 15, 1, false)
507 MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false)
508 MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false)
509 MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false)
510 MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false)
7c5ec609
SR		 511 MUX_CFG(DA850, EMA_A_0, 12, 28, 15, 1, false)
512 MUX_CFG(DA850, EMA_A_3, 12, 16, 15, 1, false)
513 MUX_CFG(DA850, EMA_A_4, 12, 12, 15, 1, false)
514 MUX_CFG(DA850, EMA_A_5, 12, 8, 15, 1, false)
515 MUX_CFG(DA850, EMA_A_6, 12, 4, 15, 1, false)
516 MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false)
517 MUX_CFG(DA850, EMA_A_8, 11, 28, 15, 1, false)
518 MUX_CFG(DA850, EMA_A_9, 11, 24, 15, 1, false)
519 MUX_CFG(DA850, EMA_A_10, 11, 20, 15, 1, false)
520 MUX_CFG(DA850, EMA_A_11, 11, 16, 15, 1, false)
521 MUX_CFG(DA850, EMA_A_12, 11, 12, 15, 1, false)
522 MUX_CFG(DA850, EMA_A_13, 11, 8, 15, 1, false)
523 MUX_CFG(DA850, EMA_A_14, 11, 4, 15, 1, false)
524 MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false)
525 MUX_CFG(DA850, EMA_A_16, 10, 28, 15, 1, false)
526 MUX_CFG(DA850, EMA_A_17, 10, 24, 15, 1, false)
527 MUX_CFG(DA850, EMA_A_18, 10, 20, 15, 1, false)
528 MUX_CFG(DA850, EMA_A_19, 10, 16, 15, 1, false)
529 MUX_CFG(DA850, EMA_A_20, 10, 12, 15, 1, false)
530 MUX_CFG(DA850, EMA_A_21, 10, 8, 15, 1, false)
531 MUX_CFG(DA850, EMA_A_22, 10, 4, 15, 1, false)
532 MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false)
533 MUX_CFG(DA850, EMA_D_8, 8, 28, 15, 1, false)
534 MUX_CFG(DA850, EMA_D_9, 8, 24, 15, 1, false)
535 MUX_CFG(DA850, EMA_D_10, 8, 20, 15, 1, false)
536 MUX_CFG(DA850, EMA_D_11, 8, 16, 15, 1, false)
537 MUX_CFG(DA850, EMA_D_12, 8, 12, 15, 1, false)
538 MUX_CFG(DA850, EMA_D_13, 8, 8, 15, 1, false)
539 MUX_CFG(DA850, EMA_D_14, 8, 4, 15, 1, false)
540 MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false)
541 MUX_CFG(DA850, EMA_BA_1, 5, 24, 15, 1, false)
542 MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false)
543 MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false)
544 MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false)
5cbdf276 545 /* GPIO function */
fe358d6a 546 MUX_CFG(DA850, GPIO2_4, 6, 12, 15, 8, false)
2206771c 547 MUX_CFG(DA850, GPIO2_6, 6, 4, 15, 8, false)
7761ef67 548 MUX_CFG(DA850, GPIO2_8, 5, 28, 15, 8, false)
5cbdf276 549 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false)
fe358d6a
VR		 550 MUX_CFG(DA850, GPIO3_12, 7, 12, 15, 8, false)
551 MUX_CFG(DA850, GPIO3_13, 7, 8, 15, 8, false)
700691f2
SR		 552 MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false)
553 MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false)
fe358d6a 554 MUX_CFG(DA850, GPIO6_13, 13, 8, 15, 8, false)
044ca015 555 MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false)
e1a8d7e2
SR		 556#endif
557};
558
559const short da850_uart0_pins[] __initdata = {
560 DA850_NUART0_CTS, DA850_NUART0_RTS, DA850_UART0_RXD, DA850_UART0_TXD,
561 -1
562};
563
564const short da850_uart1_pins[] __initdata = {
565 DA850_UART1_RXD, DA850_UART1_TXD,
566 -1
567};
568
569const short da850_uart2_pins[] __initdata = {
570 DA850_UART2_RXD, DA850_UART2_TXD,
571 -1
572};
573
574const short da850_i2c0_pins[] __initdata = {
575 DA850_I2C0_SDA, DA850_I2C0_SCL,
576 -1
577};
578
579const short da850_i2c1_pins[] __initdata = {
580 DA850_I2C1_SCL, DA850_I2C1_SDA,
581 -1
582};
583
5a4b1315
SR		 584const short da850_cpgmac_pins[] __initdata = {
585 DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
586 DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
587 DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
53ca5c91 588 DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
85b8307f
SS		 589 DA850_MDIO_D, DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
590 DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1, DA850_RMII_RXER,
591 DA850_RMII_MHZ_50_CLK,
2206771c
C		 592 -1
593};
594
491214e1
C		 595const short da850_mcasp_pins[] __initdata = {
596 DA850_AHCLKX, DA850_ACLKX, DA850_AFSX,
597 DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE,
598 DA850_AXR_11, DA850_AXR_12,
599 -1
600};
601
5cbdf276 602const short da850_lcdcntl_pins[] __initdata = {
7761ef67
SR		 603 DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
604 DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
605 DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11,
606 DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15,
607 DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS,
5cbdf276
SR		 608 -1
609};
610
700691f2
SR		 611const short da850_mmcsd0_pins[] __initdata = {
612 DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2,
613 DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD,
614 DA850_GPIO4_0, DA850_GPIO4_1,
615 -1
616};
617
f48ecc2f 618const short da850_emif25_pins[] __initdata = {
7c5ec609 619 DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2,
f48ecc2f
SS		 620 DA850_NEMA_CS_3, DA850_NEMA_CS_4, DA850_NEMA_WE, DA850_NEMA_OE,
621 DA850_EMA_D_0, DA850_EMA_D_1, DA850_EMA_D_2, DA850_EMA_D_3,
622 DA850_EMA_D_4, DA850_EMA_D_5, DA850_EMA_D_6, DA850_EMA_D_7,
623 DA850_EMA_D_8, DA850_EMA_D_9, DA850_EMA_D_10, DA850_EMA_D_11,
624 DA850_EMA_D_12, DA850_EMA_D_13, DA850_EMA_D_14, DA850_EMA_D_15,
625 DA850_EMA_A_0, DA850_EMA_A_1, DA850_EMA_A_2, DA850_EMA_A_3,
626 DA850_EMA_A_4, DA850_EMA_A_5, DA850_EMA_A_6, DA850_EMA_A_7,
627 DA850_EMA_A_8, DA850_EMA_A_9, DA850_EMA_A_10, DA850_EMA_A_11,
628 DA850_EMA_A_12, DA850_EMA_A_13, DA850_EMA_A_14, DA850_EMA_A_15,
629 DA850_EMA_A_16, DA850_EMA_A_17, DA850_EMA_A_18, DA850_EMA_A_19,
630 DA850_EMA_A_20, DA850_EMA_A_21, DA850_EMA_A_22, DA850_EMA_A_23,
7c5ec609
SR		 631 -1
632};
633
e1a8d7e2
SR		 634/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
635static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
636 [IRQ_DA8XX_COMMTX] = 7,
637 [IRQ_DA8XX_COMMRX] = 7,
638 [IRQ_DA8XX_NINT] = 7,
639 [IRQ_DA8XX_EVTOUT0] = 7,
640 [IRQ_DA8XX_EVTOUT1] = 7,
641 [IRQ_DA8XX_EVTOUT2] = 7,
642 [IRQ_DA8XX_EVTOUT3] = 7,
643 [IRQ_DA8XX_EVTOUT4] = 7,
644 [IRQ_DA8XX_EVTOUT5] = 7,
645 [IRQ_DA8XX_EVTOUT6] = 7,
e1a8d7e2
SR		 646 [IRQ_DA8XX_EVTOUT7] = 7,
647 [IRQ_DA8XX_CCINT0] = 7,
648 [IRQ_DA8XX_CCERRINT] = 7,
649 [IRQ_DA8XX_TCERRINT0] = 7,
650 [IRQ_DA8XX_AEMIFINT] = 7,
651 [IRQ_DA8XX_I2CINT0] = 7,
652 [IRQ_DA8XX_MMCSDINT0] = 7,
653 [IRQ_DA8XX_MMCSDINT1] = 7,
654 [IRQ_DA8XX_ALLINT0] = 7,
655 [IRQ_DA8XX_RTC] = 7,
656 [IRQ_DA8XX_SPINT0] = 7,
657 [IRQ_DA8XX_TINT12_0] = 7,
658 [IRQ_DA8XX_TINT34_0] = 7,
659 [IRQ_DA8XX_TINT12_1] = 7,
660 [IRQ_DA8XX_TINT34_1] = 7,
661 [IRQ_DA8XX_UARTINT0] = 7,
662 [IRQ_DA8XX_KEYMGRINT] = 7,
e1a8d7e2 663 [IRQ_DA850_MPUADDRERR0] = 7,
e1a8d7e2
SR		 664 [IRQ_DA8XX_CHIPINT0] = 7,
665 [IRQ_DA8XX_CHIPINT1] = 7,
666 [IRQ_DA8XX_CHIPINT2] = 7,
667 [IRQ_DA8XX_CHIPINT3] = 7,
668 [IRQ_DA8XX_TCERRINT1] = 7,
669 [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7,
670 [IRQ_DA8XX_C0_RX_PULSE] = 7,
671 [IRQ_DA8XX_C0_TX_PULSE] = 7,
672 [IRQ_DA8XX_C0_MISC_PULSE] = 7,
673 [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7,
674 [IRQ_DA8XX_C1_RX_PULSE] = 7,
675 [IRQ_DA8XX_C1_TX_PULSE] = 7,
676 [IRQ_DA8XX_C1_MISC_PULSE] = 7,
677 [IRQ_DA8XX_MEMERR] = 7,
678 [IRQ_DA8XX_GPIO0] = 7,
679 [IRQ_DA8XX_GPIO1] = 7,
680 [IRQ_DA8XX_GPIO2] = 7,
681 [IRQ_DA8XX_GPIO3] = 7,
682 [IRQ_DA8XX_GPIO4] = 7,
683 [IRQ_DA8XX_GPIO5] = 7,
684 [IRQ_DA8XX_GPIO6] = 7,
685 [IRQ_DA8XX_GPIO7] = 7,
686 [IRQ_DA8XX_GPIO8] = 7,
687 [IRQ_DA8XX_I2CINT1] = 7,
688 [IRQ_DA8XX_LCDINT] = 7,
689 [IRQ_DA8XX_UARTINT1] = 7,
690 [IRQ_DA8XX_MCASPINT] = 7,
691 [IRQ_DA8XX_ALLINT1] = 7,
692 [IRQ_DA8XX_SPINT1] = 7,
693 [IRQ_DA8XX_UHPI_INT1] = 7,
694 [IRQ_DA8XX_USB_INT] = 7,
695 [IRQ_DA8XX_IRQN] = 7,
696 [IRQ_DA8XX_RWAKEUP] = 7,
697 [IRQ_DA8XX_UARTINT2] = 7,
698 [IRQ_DA8XX_DFTSSINT] = 7,
699 [IRQ_DA8XX_EHRPWM0] = 7,
700 [IRQ_DA8XX_EHRPWM0TZ] = 7,
701 [IRQ_DA8XX_EHRPWM1] = 7,
702 [IRQ_DA8XX_EHRPWM1TZ] = 7,
703 [IRQ_DA850_SATAINT] = 7,
e1a8d7e2
SR		 704 [IRQ_DA850_TINTALL_2] = 7,
705 [IRQ_DA8XX_ECAP0] = 7,
706 [IRQ_DA8XX_ECAP1] = 7,
707 [IRQ_DA8XX_ECAP2] = 7,
708 [IRQ_DA850_MMCSDINT0_1] = 7,
709 [IRQ_DA850_MMCSDINT1_1] = 7,
710 [IRQ_DA850_T12CMPINT0_2] = 7,
711 [IRQ_DA850_T12CMPINT1_2] = 7,
712 [IRQ_DA850_T12CMPINT2_2] = 7,
713 [IRQ_DA850_T12CMPINT3_2] = 7,
714 [IRQ_DA850_T12CMPINT4_2] = 7,
715 [IRQ_DA850_T12CMPINT5_2] = 7,
716 [IRQ_DA850_T12CMPINT6_2] = 7,
717 [IRQ_DA850_T12CMPINT7_2] = 7,
718 [IRQ_DA850_T12CMPINT0_3] = 7,
719 [IRQ_DA850_T12CMPINT1_3] = 7,
720 [IRQ_DA850_T12CMPINT2_3] = 7,
721 [IRQ_DA850_T12CMPINT3_3] = 7,
722 [IRQ_DA850_T12CMPINT4_3] = 7,
723 [IRQ_DA850_T12CMPINT5_3] = 7,
724 [IRQ_DA850_T12CMPINT6_3] = 7,
725 [IRQ_DA850_T12CMPINT7_3] = 7,
726 [IRQ_DA850_RPIINT] = 7,
727 [IRQ_DA850_VPIFINT] = 7,
728 [IRQ_DA850_CCINT1] = 7,
729 [IRQ_DA850_CCERRINT1] = 7,
730 [IRQ_DA850_TCERRINT2] = 7,
e1a8d7e2
SR		 731 [IRQ_DA850_TINTALL_3] = 7,
732 [IRQ_DA850_MCBSP0RINT] = 7,
733 [IRQ_DA850_MCBSP0XINT] = 7,
734 [IRQ_DA850_MCBSP1RINT] = 7,
735 [IRQ_DA850_MCBSP1XINT] = 7,
736 [IRQ_DA8XX_ARMCLKSTOPREQ] = 7,
737};
738
739static struct map_desc da850_io_desc[] = {
740 {
741 .virtual = IO_VIRT,
742 .pfn = __phys_to_pfn(IO_PHYS),
743 .length = IO_SIZE,
744 .type = MT_DEVICE
745 },
746 {
747 .virtual = DA8XX_CP_INTC_VIRT,
748 .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE),
749 .length = DA8XX_CP_INTC_SIZE,
750 .type = MT_DEVICE
751 },
60cd02e1
SN		 752 {
753 .virtual = SRAM_VIRT,
754 .pfn = __phys_to_pfn(DA8XX_ARM_RAM_BASE),
755 .length = SZ_8K,
756 .type = MT_DEVICE
757 },
e1a8d7e2
SR		 758};
759
e4c822c7 760static u32 da850_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE };
e1a8d7e2
SR		 761
762/* Contents of JTAG ID register used to identify exact cpu type */
763static struct davinci_id da850_ids[] = {
764 {
765 .variant = 0x0,
766 .part_no = 0xb7d1,
767 .manufacturer = 0x017, /* 0x02f >> 1 */
768 .cpu_id = DAVINCI_CPU_ID_DA850,
769 .name = "da850/omap-l138",
770 },
771};
772
773static struct davinci_timer_instance da850_timer_instance[4] = {
774 {
1bcd38ad 775 .base = DA8XX_TIMER64P0_BASE,
e1a8d7e2
SR		 776 .bottom_irq = IRQ_DA8XX_TINT12_0,
777 .top_irq = IRQ_DA8XX_TINT34_0,
778 },
779 {
1bcd38ad 780 .base = DA8XX_TIMER64P1_BASE,
e1a8d7e2
SR		 781 .bottom_irq = IRQ_DA8XX_TINT12_1,
782 .top_irq = IRQ_DA8XX_TINT34_1,
783 },
784 {
1bcd38ad 785 .base = DA850_TIMER64P2_BASE,
e1a8d7e2
SR		 786 .bottom_irq = IRQ_DA850_TINT12_2,
787 .top_irq = IRQ_DA850_TINT34_2,
788 },
789 {
1bcd38ad 790 .base = DA850_TIMER64P3_BASE,
e1a8d7e2
SR		 791 .bottom_irq = IRQ_DA850_TINT12_3,
792 .top_irq = IRQ_DA850_TINT34_3,
793 },
794};
795
796/*
797 * T0_BOT: Timer 0, bottom : Used for clock_event
798 * T0_TOP: Timer 0, top : Used for clocksource
799 * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
800 */
801static struct davinci_timer_info da850_timer_info = {
802 .timers = da850_timer_instance,
803 .clockevent_id = T0_BOT,
804 .clocksource_id = T0_TOP,
805};
806
5d36a332
SN		 807static void da850_set_async3_src(int pllnum)
808{
809 struct clk *clk, *newparent = pllnum ? &pll1_sysclk2 : &pll0_sysclk2;
08aca087 810 struct clk_lookup *c;
5d36a332
SN		 811 unsigned int v;
812 int ret;
813
08aca087
KH		 814 for (c = da850_clks; c->clk; c++) {
815 clk = c->clk;
5d36a332
SN		 816 if (clk->flags & DA850_CLK_ASYNC3) {
817 ret = clk_set_parent(clk, newparent);
818 WARN(ret, "DA850: unable to re-parent clock %s",
819 clk->name);
820 }
821 }
822
d2de0582 823 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
5d36a332
SN		 824 if (pllnum)
825 v |= CFGCHIP3_ASYNC3_CLKSRC;
826 else
827 v &= ~CFGCHIP3_ASYNC3_CLKSRC;
d2de0582 828 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
5d36a332
SN		 829}
830
683b1e1f
SN		 831#ifdef CONFIG_CPU_FREQ
832/*
833 * Notes:
834 * According to the TRM, minimum PLLM results in maximum power savings.
835 * The OPP definitions below should keep the PLLM as low as possible.
836 *
39e14550 837 * The output of the PLLM must be between 300 to 600 MHz.
683b1e1f
SN		 838 */
839struct da850_opp {
840 unsigned int freq; /* in KHz */
841 unsigned int prediv;
842 unsigned int mult;
843 unsigned int postdiv;
35f9acd8
SN		 844 unsigned int cvdd_min; /* in uV */
845 unsigned int cvdd_max; /* in uV */
683b1e1f
SN		 846};
847
39e14550
SN		 848static const struct da850_opp da850_opp_456 = {
849 .freq = 456000,
850 .prediv = 1,
851 .mult = 19,
852 .postdiv = 1,
853 .cvdd_min = 1300000,
854 .cvdd_max = 1350000,
855};
856
857static const struct da850_opp da850_opp_408 = {
858 .freq = 408000,
859 .prediv = 1,
860 .mult = 17,
861 .postdiv = 1,
862 .cvdd_min = 1300000,
863 .cvdd_max = 1350000,
864};
865
866static const struct da850_opp da850_opp_372 = {
867 .freq = 372000,
868 .prediv = 2,
869 .mult = 31,
870 .postdiv = 1,
871 .cvdd_min = 1200000,
872 .cvdd_max = 1320000,
873};
874
683b1e1f
SN		 875static const struct da850_opp da850_opp_300 = {
876 .freq = 300000,
877 .prediv = 1,
878 .mult = 25,
879 .postdiv = 2,
6ef62f82 880 .cvdd_min = 1200000,
35f9acd8 881 .cvdd_max = 1320000,
683b1e1f
SN		 882};
883
884static const struct da850_opp da850_opp_200 = {
885 .freq = 200000,
886 .prediv = 1,
887 .mult = 25,
888 .postdiv = 3,
6ef62f82 889 .cvdd_min = 1100000,
35f9acd8 890 .cvdd_max = 1160000,
683b1e1f
SN		 891};
892
893static const struct da850_opp da850_opp_96 = {
894 .freq = 96000,
895 .prediv = 1,
896 .mult = 20,
897 .postdiv = 5,
6ef62f82 898 .cvdd_min = 1000000,
35f9acd8 899 .cvdd_max = 1050000,
683b1e1f
SN		 900};
901
902#define OPP(freq) \
903 { \
904 .index = (unsigned int) &da850_opp_##freq, \
905 .frequency = freq * 1000, \
906 }
907
908static struct cpufreq_frequency_table da850_freq_table[] = {
39e14550
SN		 909 OPP(456),
910 OPP(408),
911 OPP(372),
683b1e1f
SN		 912 OPP(300),
913 OPP(200),
914 OPP(96),
915 {
916 .index = 0,
917 .frequency = CPUFREQ_TABLE_END,
918 },
919};
920
39e14550
SN		 921#ifdef CONFIG_REGULATOR
922static int da850_set_voltage(unsigned int index);
923static int da850_regulator_init(void);
924#endif
925
926static struct davinci_cpufreq_config cpufreq_info = {
927 .freq_table = da850_freq_table,
928#ifdef CONFIG_REGULATOR
929 .init = da850_regulator_init,
930 .set_voltage = da850_set_voltage,
931#endif
932};
933
13d5e27a
SN		 934#ifdef CONFIG_REGULATOR
935static struct regulator *cvdd;
936
937static int da850_set_voltage(unsigned int index)
938{
939 struct da850_opp *opp;
940
941 if (!cvdd)
942 return -ENODEV;
943
39e14550 944 opp = (struct da850_opp *) cpufreq_info.freq_table[index].index;
13d5e27a
SN		 945
946 return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
947}
948
949static int da850_regulator_init(void)
950{
951 cvdd = regulator_get(NULL, "cvdd");
952 if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;"
953 " voltage scaling unsupported\n")) {
954 return PTR_ERR(cvdd);
955 }
956
957 return 0;
958}
959#endif
960
683b1e1f
SN		 961static struct platform_device da850_cpufreq_device = {
962 .name = "cpufreq-davinci",
963 .dev = {
964 .platform_data = &cpufreq_info,
965 },
b987c4b2 966 .id = -1,
683b1e1f
SN		 967};
968
39e14550
SN		 969unsigned int da850_max_speed = 300000;
970
b987c4b2 971int __init da850_register_cpufreq(char *async_clk)
683b1e1f 972{
39e14550
SN		 973 int i;
974
b987c4b2
SN		 975 /* cpufreq driver can help keep an "async" clock constant */
976 if (async_clk)
977 clk_add_alias("async", da850_cpufreq_device.name,
978 async_clk, NULL);
39e14550
SN		 979 for (i = 0; i < ARRAY_SIZE(da850_freq_table); i++) {
980 if (da850_freq_table[i].frequency <= da850_max_speed) {
981 cpufreq_info.freq_table = &da850_freq_table[i];
982 break;
983 }
984 }
b987c4b2 985
683b1e1f
SN		 986 return platform_device_register(&da850_cpufreq_device);
987}
988
989static int da850_round_armrate(struct clk *clk, unsigned long rate)
990{
991 int i, ret = 0, diff;
992 unsigned int best = (unsigned int) -1;
39e14550 993 struct cpufreq_frequency_table *table = cpufreq_info.freq_table;
683b1e1f
SN		 994
995 rate /= 1000; /* convert to kHz */
996
39e14550
SN		 997 for (i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++) {
998 diff = table[i].frequency - rate;
683b1e1f
SN		 999 if (diff < 0)
1000 diff = -diff;
1001
1002 if (diff < best) {
1003 best = diff;
39e14550 1004 ret = table[i].frequency;
683b1e1f
SN		 1005 }
1006 }
1007
1008 return ret * 1000;
1009}
1010
1011static int da850_set_armrate(struct clk *clk, unsigned long index)
1012{
1013 struct clk *pllclk = &pll0_clk;
1014
1015 return clk_set_rate(pllclk, index);
1016}
1017
1018static int da850_set_pll0rate(struct clk *clk, unsigned long index)
1019{
1020 unsigned int prediv, mult, postdiv;
1021 struct da850_opp *opp;
1022 struct pll_data *pll = clk->pll_data;
683b1e1f
SN		 1023 int ret;
1024
39e14550 1025 opp = (struct da850_opp *) cpufreq_info.freq_table[index].index;
683b1e1f
SN		 1026 prediv = opp->prediv;
1027 mult = opp->mult;
1028 postdiv = opp->postdiv;
1029
683b1e1f
SN		 1030 ret = davinci_set_pllrate(pll, prediv, mult, postdiv);
1031 if (WARN_ON(ret))
1032 return ret;
1033
1034 return 0;
1035}
1036#else
fca97b33 1037int __init da850_register_cpufreq(char *async_clk)
683b1e1f
SN		 1038{
1039 return 0;
1040}
1041
1042static int da850_set_armrate(struct clk *clk, unsigned long rate)
1043{
1044 return -EINVAL;
1045}
1046
1047static int da850_set_pll0rate(struct clk *clk, unsigned long armrate)
1048{
1049 return -EINVAL;
1050}
1051
1052static int da850_round_armrate(struct clk *clk, unsigned long rate)
1053{
1054 return clk->rate;
1055}
1056#endif
1057
044ca015
SN		 1058int da850_register_pm(struct platform_device *pdev)
1059{
1060 int ret;
1061 struct davinci_pm_config *pdata = pdev->dev.platform_data;
1062
1063 ret = davinci_cfg_reg(DA850_RTC_ALARM);
1064 if (ret)
1065 return ret;
1066
1067 pdata->ddr2_ctlr_base = da8xx_get_mem_ctlr();
1068 pdata->deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG);
1069 pdata->ddrpsc_num = DA8XX_LPSC1_EMIF3C;
1070
1071 pdata->cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K);
1072 if (!pdata->cpupll_reg_base)
1073 return -ENOMEM;
1074
1075 pdata->ddrpll_reg_base = ioremap(DA8XX_PLL1_BASE, SZ_4K);
1076 if (!pdata->ddrpll_reg_base) {
1077 ret = -ENOMEM;
1078 goto no_ddrpll_mem;
1079 }
1080
1081 pdata->ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K);
1082 if (!pdata->ddrpsc_reg_base) {
1083 ret = -ENOMEM;
1084 goto no_ddrpsc_mem;
1085 }
1086
1087 return platform_device_register(pdev);
1088
1089no_ddrpsc_mem:
1090 iounmap(pdata->ddrpll_reg_base);
1091no_ddrpll_mem:
1092 iounmap(pdata->cpupll_reg_base);
1093 return ret;
1094}
35f9acd8 1095
e1a8d7e2
SR		 1096static struct davinci_soc_info davinci_soc_info_da850 = {
1097 .io_desc = da850_io_desc,
1098 .io_desc_num = ARRAY_SIZE(da850_io_desc),
3347db83 1099 .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
e1a8d7e2
SR		 1100 .ids = da850_ids,
1101 .ids_num = ARRAY_SIZE(da850_ids),
1102 .cpu_clks = da850_clks,
1103 .psc_bases = da850_psc_bases,
1104 .psc_bases_num = ARRAY_SIZE(da850_psc_bases),
779b0d53 1105 .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
e1a8d7e2
SR		 1106 .pinmux_pins = da850_pins,
1107 .pinmux_pins_num = ARRAY_SIZE(da850_pins),
bd808947 1108 .intc_base = DA8XX_CP_INTC_BASE,
e1a8d7e2
SR		 1109 .intc_type = DAVINCI_INTC_TYPE_CP_INTC,
1110 .intc_irq_prios = da850_default_priorities,
1111 .intc_irq_num = DA850_N_CP_INTC_IRQ,
1112 .timer_info = &da850_timer_info,
686b634a 1113 .gpio_type = GPIO_TYPE_DAVINCI,
b8d44293 1114 .gpio_base = DA8XX_GPIO_BASE,
5a8d5441 1115 .gpio_num = 144,
e1a8d7e2
SR		 1116 .gpio_irq = IRQ_DA8XX_GPIO0,
1117 .serial_dev = &da8xx_serial_device,
1118 .emac_pdata = &da8xx_emac_pdata,
60cd02e1
SN		 1119 .sram_dma = DA8XX_ARM_RAM_BASE,
1120 .sram_len = SZ_8K,
c78a5bc2 1121 .reset_device = &da8xx_wdt_device,
e1a8d7e2
SR		 1122};
1123
1124void __init da850_init(void)
1125{
7aad472b
SN		 1126 unsigned int v;
1127
bcd6a1c6
CC		 1128 davinci_common_init(&davinci_soc_info_da850);
1129
d2de0582
SN		 1130 da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
1131 if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
1132 return;
1133
1134 da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K);
1135 if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
6a28adef
SN		 1136 return;
1137
5d36a332
SN		 1138 /*
1139 * Move the clock source of Async3 domain to PLL1 SYSCLK2.
1140 * This helps keeping the peripherals on this domain insulated
1141 * from CPU frequency changes caused by DVFS. The firmware sets
1142 * both PLL0 and PLL1 to the same frequency so, there should not
1143 * be any noticible change even in non-DVFS use cases.
1144 */
1145 da850_set_async3_src(1);
7aad472b
SN		 1146
1147 /* Unlock writing to PLL0 registers */
1148 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1149 v &= ~CFGCHIP0_PLL_MASTER_LOCK;
1150 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1151
1152 /* Unlock writing to PLL1 registers */
1153 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
1154 v &= ~CFGCHIP3_PLL1_MASTER_LOCK;
1155 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
e1a8d7e2 1156}
Linux kernel - Deliverables
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