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55c79a40 MG |
1 | /* |
2 | * DA8XX/OMAP L1XX platform device data | |
3 | * | |
4 | * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com> | |
5 | * Derived from code that was: | |
6 | * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
55c79a40 MG |
13 | #include <linux/init.h> |
14 | #include <linux/platform_device.h> | |
5c71d618 | 15 | #include <linux/dma-contiguous.h> |
55c79a40 | 16 | #include <linux/serial_8250.h> |
cbb2c961 SN |
17 | #include <linux/ahci_platform.h> |
18 | #include <linux/clk.h> | |
7b6d864b | 19 | #include <linux/reboot.h> |
55c79a40 MG |
20 | |
21 | #include <mach/cputype.h> | |
22 | #include <mach/common.h> | |
23 | #include <mach/time.h> | |
24 | #include <mach/da8xx.h> | |
1960e693 | 25 | #include <mach/cpuidle.h> |
8e0d72d2 | 26 | #include <mach/sram.h> |
55c79a40 MG |
27 | |
28 | #include "clock.h" | |
896f66b7 | 29 | #include "asp.h" |
55c79a40 MG |
30 | |
31 | #define DA8XX_TPCC_BASE 0x01c00000 | |
32 | #define DA8XX_TPTC0_BASE 0x01c08000 | |
33 | #define DA8XX_TPTC1_BASE 0x01c08400 | |
34 | #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */ | |
35 | #define DA8XX_I2C0_BASE 0x01c22000 | |
8ac764e3 | 36 | #define DA8XX_RTC_BASE 0x01c23000 |
8e0d72d2 | 37 | #define DA8XX_PRUSS_MEM_BASE 0x01c30000 |
8ac764e3 SS |
38 | #define DA8XX_MMCSD0_BASE 0x01c40000 |
39 | #define DA8XX_SPI0_BASE 0x01c41000 | |
40 | #define DA830_SPI1_BASE 0x01e12000 | |
41 | #define DA8XX_LCD_CNTRL_BASE 0x01e13000 | |
cbb2c961 | 42 | #define DA850_SATA_BASE 0x01e18000 |
8ac764e3 | 43 | #define DA850_MMCSD1_BASE 0x01e1b000 |
55c79a40 MG |
44 | #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000 |
45 | #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000 | |
46 | #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000 | |
47 | #define DA8XX_EMAC_MDIO_BASE 0x01e24000 | |
55c79a40 | 48 | #define DA8XX_I2C1_BASE 0x01e28000 |
8ac764e3 SS |
49 | #define DA850_TPCC1_BASE 0x01e30000 |
50 | #define DA850_TPTC2_BASE 0x01e38000 | |
9e7d24f6 | 51 | #define DA850_SPI1_BASE 0x01f0e000 |
8ac764e3 | 52 | #define DA8XX_DDR2_CTL_BASE 0xb0000000 |
55c79a40 MG |
53 | |
54 | #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000 | |
55 | #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000 | |
56 | #define DA8XX_EMAC_RAM_OFFSET 0x0000 | |
55c79a40 MG |
57 | #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K |
58 | ||
54ce6883 MW |
59 | #define DA8XX_DMA_SPI0_RX EDMA_CTLR_CHAN(0, 14) |
60 | #define DA8XX_DMA_SPI0_TX EDMA_CTLR_CHAN(0, 15) | |
e38c2b22 MW |
61 | #define DA8XX_DMA_MMCSD0_RX EDMA_CTLR_CHAN(0, 16) |
62 | #define DA8XX_DMA_MMCSD0_TX EDMA_CTLR_CHAN(0, 17) | |
54ce6883 MW |
63 | #define DA8XX_DMA_SPI1_RX EDMA_CTLR_CHAN(0, 18) |
64 | #define DA8XX_DMA_SPI1_TX EDMA_CTLR_CHAN(0, 19) | |
e38c2b22 MW |
65 | #define DA850_DMA_MMCSD1_RX EDMA_CTLR_CHAN(1, 28) |
66 | #define DA850_DMA_MMCSD1_TX EDMA_CTLR_CHAN(1, 29) | |
67 | ||
d2de0582 SN |
68 | void __iomem *da8xx_syscfg0_base; |
69 | void __iomem *da8xx_syscfg1_base; | |
6a28adef | 70 | |
19955c3d | 71 | static struct plat_serial8250_port da8xx_serial0_pdata[] = { |
55c79a40 MG |
72 | { |
73 | .mapbase = DA8XX_UART0_BASE, | |
74 | .irq = IRQ_DA8XX_UARTINT0, | |
75 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | |
76 | UPF_IOREMAP, | |
77 | .iotype = UPIO_MEM, | |
78 | .regshift = 2, | |
79 | }, | |
19955c3d MP |
80 | { |
81 | .flags = 0, | |
82 | } | |
83 | }; | |
84 | static struct plat_serial8250_port da8xx_serial1_pdata[] = { | |
55c79a40 MG |
85 | { |
86 | .mapbase = DA8XX_UART1_BASE, | |
87 | .irq = IRQ_DA8XX_UARTINT1, | |
88 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | |
89 | UPF_IOREMAP, | |
90 | .iotype = UPIO_MEM, | |
91 | .regshift = 2, | |
92 | }, | |
19955c3d MP |
93 | { |
94 | .flags = 0, | |
95 | } | |
96 | }; | |
97 | static struct plat_serial8250_port da8xx_serial2_pdata[] = { | |
55c79a40 MG |
98 | { |
99 | .mapbase = DA8XX_UART2_BASE, | |
100 | .irq = IRQ_DA8XX_UARTINT2, | |
101 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | |
102 | UPF_IOREMAP, | |
103 | .iotype = UPIO_MEM, | |
104 | .regshift = 2, | |
105 | }, | |
106 | { | |
107 | .flags = 0, | |
19955c3d | 108 | } |
55c79a40 MG |
109 | }; |
110 | ||
19955c3d MP |
111 | struct platform_device da8xx_serial_device[] = { |
112 | { | |
113 | .name = "serial8250", | |
114 | .id = PLAT8250_DEV_PLATFORM, | |
115 | .dev = { | |
116 | .platform_data = da8xx_serial0_pdata, | |
117 | } | |
118 | }, | |
119 | { | |
120 | .name = "serial8250", | |
121 | .id = PLAT8250_DEV_PLATFORM1, | |
122 | .dev = { | |
123 | .platform_data = da8xx_serial1_pdata, | |
124 | } | |
55c79a40 | 125 | }, |
19955c3d MP |
126 | { |
127 | .name = "serial8250", | |
128 | .id = PLAT8250_DEV_PLATFORM2, | |
129 | .dev = { | |
130 | .platform_data = da8xx_serial2_pdata, | |
131 | } | |
132 | }, | |
133 | { | |
134 | } | |
55c79a40 MG |
135 | }; |
136 | ||
6cba4355 | 137 | static s8 da8xx_queue_tc_mapping[][2] = { |
55c79a40 MG |
138 | /* {event queue no, TC no} */ |
139 | {0, 0}, | |
140 | {1, 1}, | |
141 | {-1, -1} | |
142 | }; | |
143 | ||
6cba4355 | 144 | static s8 da8xx_queue_priority_mapping[][2] = { |
55c79a40 MG |
145 | /* {event queue no, Priority} */ |
146 | {0, 3}, | |
147 | {1, 7}, | |
148 | {-1, -1} | |
149 | }; | |
150 | ||
6cba4355 | 151 | static s8 da850_queue_tc_mapping[][2] = { |
3f995f2f SR |
152 | /* {event queue no, TC no} */ |
153 | {0, 0}, | |
154 | {-1, -1} | |
155 | }; | |
156 | ||
6cba4355 | 157 | static s8 da850_queue_priority_mapping[][2] = { |
3f995f2f SR |
158 | /* {event queue no, Priority} */ |
159 | {0, 3}, | |
160 | {-1, -1} | |
161 | }; | |
162 | ||
bc3ac9f3 SN |
163 | static struct edma_soc_info da830_edma_cc0_info = { |
164 | .n_channel = 32, | |
165 | .n_region = 4, | |
166 | .n_slot = 128, | |
167 | .n_tc = 2, | |
168 | .n_cc = 1, | |
169 | .queue_tc_mapping = da8xx_queue_tc_mapping, | |
170 | .queue_priority_mapping = da8xx_queue_priority_mapping, | |
f23fe857 | 171 | .default_queue = EVENTQ_1, |
bc3ac9f3 SN |
172 | }; |
173 | ||
174 | static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = { | |
175 | &da830_edma_cc0_info, | |
55c79a40 MG |
176 | }; |
177 | ||
bc3ac9f3 | 178 | static struct edma_soc_info da850_edma_cc_info[] = { |
3f995f2f SR |
179 | { |
180 | .n_channel = 32, | |
181 | .n_region = 4, | |
182 | .n_slot = 128, | |
183 | .n_tc = 2, | |
184 | .n_cc = 1, | |
185 | .queue_tc_mapping = da8xx_queue_tc_mapping, | |
186 | .queue_priority_mapping = da8xx_queue_priority_mapping, | |
f23fe857 | 187 | .default_queue = EVENTQ_1, |
3f995f2f SR |
188 | }, |
189 | { | |
190 | .n_channel = 32, | |
191 | .n_region = 4, | |
192 | .n_slot = 128, | |
193 | .n_tc = 1, | |
194 | .n_cc = 1, | |
195 | .queue_tc_mapping = da850_queue_tc_mapping, | |
196 | .queue_priority_mapping = da850_queue_priority_mapping, | |
f23fe857 | 197 | .default_queue = EVENTQ_0, |
3f995f2f SR |
198 | }, |
199 | }; | |
200 | ||
bc3ac9f3 SN |
201 | static struct edma_soc_info *da850_edma_info[EDMA_MAX_CC] = { |
202 | &da850_edma_cc_info[0], | |
203 | &da850_edma_cc_info[1], | |
204 | }; | |
205 | ||
3f995f2f | 206 | static struct resource da830_edma_resources[] = { |
55c79a40 MG |
207 | { |
208 | .name = "edma_cc0", | |
209 | .start = DA8XX_TPCC_BASE, | |
210 | .end = DA8XX_TPCC_BASE + SZ_32K - 1, | |
211 | .flags = IORESOURCE_MEM, | |
212 | }, | |
213 | { | |
214 | .name = "edma_tc0", | |
215 | .start = DA8XX_TPTC0_BASE, | |
216 | .end = DA8XX_TPTC0_BASE + SZ_1K - 1, | |
217 | .flags = IORESOURCE_MEM, | |
218 | }, | |
219 | { | |
220 | .name = "edma_tc1", | |
221 | .start = DA8XX_TPTC1_BASE, | |
222 | .end = DA8XX_TPTC1_BASE + SZ_1K - 1, | |
223 | .flags = IORESOURCE_MEM, | |
224 | }, | |
225 | { | |
226 | .name = "edma0", | |
2259bbd4 | 227 | .start = IRQ_DA8XX_CCINT0, |
55c79a40 MG |
228 | .flags = IORESOURCE_IRQ, |
229 | }, | |
230 | { | |
231 | .name = "edma0_err", | |
232 | .start = IRQ_DA8XX_CCERRINT, | |
233 | .flags = IORESOURCE_IRQ, | |
234 | }, | |
235 | }; | |
236 | ||
3f995f2f SR |
237 | static struct resource da850_edma_resources[] = { |
238 | { | |
239 | .name = "edma_cc0", | |
240 | .start = DA8XX_TPCC_BASE, | |
241 | .end = DA8XX_TPCC_BASE + SZ_32K - 1, | |
242 | .flags = IORESOURCE_MEM, | |
243 | }, | |
244 | { | |
245 | .name = "edma_tc0", | |
246 | .start = DA8XX_TPTC0_BASE, | |
247 | .end = DA8XX_TPTC0_BASE + SZ_1K - 1, | |
248 | .flags = IORESOURCE_MEM, | |
249 | }, | |
250 | { | |
251 | .name = "edma_tc1", | |
252 | .start = DA8XX_TPTC1_BASE, | |
253 | .end = DA8XX_TPTC1_BASE + SZ_1K - 1, | |
254 | .flags = IORESOURCE_MEM, | |
255 | }, | |
256 | { | |
257 | .name = "edma_cc1", | |
258 | .start = DA850_TPCC1_BASE, | |
259 | .end = DA850_TPCC1_BASE + SZ_32K - 1, | |
260 | .flags = IORESOURCE_MEM, | |
261 | }, | |
262 | { | |
263 | .name = "edma_tc2", | |
264 | .start = DA850_TPTC2_BASE, | |
265 | .end = DA850_TPTC2_BASE + SZ_1K - 1, | |
266 | .flags = IORESOURCE_MEM, | |
267 | }, | |
268 | { | |
269 | .name = "edma0", | |
270 | .start = IRQ_DA8XX_CCINT0, | |
271 | .flags = IORESOURCE_IRQ, | |
272 | }, | |
273 | { | |
274 | .name = "edma0_err", | |
275 | .start = IRQ_DA8XX_CCERRINT, | |
276 | .flags = IORESOURCE_IRQ, | |
277 | }, | |
278 | { | |
279 | .name = "edma1", | |
280 | .start = IRQ_DA850_CCINT1, | |
281 | .flags = IORESOURCE_IRQ, | |
282 | }, | |
283 | { | |
284 | .name = "edma1_err", | |
285 | .start = IRQ_DA850_CCERRINT1, | |
286 | .flags = IORESOURCE_IRQ, | |
287 | }, | |
288 | }; | |
289 | ||
290 | static struct platform_device da830_edma_device = { | |
55c79a40 MG |
291 | .name = "edma", |
292 | .id = -1, | |
293 | .dev = { | |
3f995f2f | 294 | .platform_data = da830_edma_info, |
55c79a40 | 295 | }, |
3f995f2f SR |
296 | .num_resources = ARRAY_SIZE(da830_edma_resources), |
297 | .resource = da830_edma_resources, | |
298 | }; | |
299 | ||
300 | static struct platform_device da850_edma_device = { | |
301 | .name = "edma", | |
302 | .id = -1, | |
303 | .dev = { | |
304 | .platform_data = da850_edma_info, | |
305 | }, | |
306 | .num_resources = ARRAY_SIZE(da850_edma_resources), | |
307 | .resource = da850_edma_resources, | |
55c79a40 MG |
308 | }; |
309 | ||
a941c503 | 310 | int __init da830_register_edma(struct edma_rsv_info *rsv) |
55c79a40 | 311 | { |
a941c503 | 312 | da830_edma_cc0_info.rsv = rsv; |
3f995f2f | 313 | |
a941c503 RS |
314 | return platform_device_register(&da830_edma_device); |
315 | } | |
316 | ||
317 | int __init da850_register_edma(struct edma_rsv_info *rsv[2]) | |
318 | { | |
319 | if (rsv) { | |
320 | da850_edma_cc_info[0].rsv = rsv[0]; | |
321 | da850_edma_cc_info[1].rsv = rsv[1]; | |
322 | } | |
3f995f2f | 323 | |
a941c503 | 324 | return platform_device_register(&da850_edma_device); |
55c79a40 MG |
325 | } |
326 | ||
327 | static struct resource da8xx_i2c_resources0[] = { | |
328 | { | |
329 | .start = DA8XX_I2C0_BASE, | |
330 | .end = DA8XX_I2C0_BASE + SZ_4K - 1, | |
331 | .flags = IORESOURCE_MEM, | |
332 | }, | |
333 | { | |
334 | .start = IRQ_DA8XX_I2CINT0, | |
335 | .end = IRQ_DA8XX_I2CINT0, | |
336 | .flags = IORESOURCE_IRQ, | |
337 | }, | |
338 | }; | |
339 | ||
340 | static struct platform_device da8xx_i2c_device0 = { | |
341 | .name = "i2c_davinci", | |
342 | .id = 1, | |
343 | .num_resources = ARRAY_SIZE(da8xx_i2c_resources0), | |
344 | .resource = da8xx_i2c_resources0, | |
345 | }; | |
346 | ||
347 | static struct resource da8xx_i2c_resources1[] = { | |
348 | { | |
349 | .start = DA8XX_I2C1_BASE, | |
350 | .end = DA8XX_I2C1_BASE + SZ_4K - 1, | |
351 | .flags = IORESOURCE_MEM, | |
352 | }, | |
353 | { | |
354 | .start = IRQ_DA8XX_I2CINT1, | |
355 | .end = IRQ_DA8XX_I2CINT1, | |
356 | .flags = IORESOURCE_IRQ, | |
357 | }, | |
358 | }; | |
359 | ||
360 | static struct platform_device da8xx_i2c_device1 = { | |
361 | .name = "i2c_davinci", | |
362 | .id = 2, | |
363 | .num_resources = ARRAY_SIZE(da8xx_i2c_resources1), | |
364 | .resource = da8xx_i2c_resources1, | |
365 | }; | |
366 | ||
367 | int __init da8xx_register_i2c(int instance, | |
368 | struct davinci_i2c_platform_data *pdata) | |
369 | { | |
370 | struct platform_device *pdev; | |
371 | ||
372 | if (instance == 0) | |
373 | pdev = &da8xx_i2c_device0; | |
374 | else if (instance == 1) | |
375 | pdev = &da8xx_i2c_device1; | |
376 | else | |
377 | return -EINVAL; | |
378 | ||
379 | pdev->dev.platform_data = pdata; | |
380 | return platform_device_register(pdev); | |
381 | } | |
382 | ||
383 | static struct resource da8xx_watchdog_resources[] = { | |
384 | { | |
385 | .start = DA8XX_WDOG_BASE, | |
386 | .end = DA8XX_WDOG_BASE + SZ_4K - 1, | |
387 | .flags = IORESOURCE_MEM, | |
388 | }, | |
389 | }; | |
390 | ||
19c7c0d8 | 391 | static struct platform_device da8xx_wdt_device = { |
55c79a40 MG |
392 | .name = "watchdog", |
393 | .id = -1, | |
394 | .num_resources = ARRAY_SIZE(da8xx_watchdog_resources), | |
395 | .resource = da8xx_watchdog_resources, | |
396 | }; | |
397 | ||
7b6d864b | 398 | void da8xx_restart(enum reboot_mode mode, const char *cmd) |
c6121ddd | 399 | { |
19c7c0d8 KA |
400 | struct device *dev; |
401 | ||
402 | dev = bus_find_device_by_name(&platform_bus_type, NULL, "watchdog"); | |
403 | if (!dev) { | |
404 | pr_err("%s: failed to find watchdog device\n", __func__); | |
405 | return; | |
406 | } | |
407 | ||
408 | davinci_watchdog_reset(to_platform_device(dev)); | |
c6121ddd SN |
409 | } |
410 | ||
55c79a40 MG |
411 | int __init da8xx_register_watchdog(void) |
412 | { | |
c78a5bc2 | 413 | return platform_device_register(&da8xx_wdt_device); |
55c79a40 MG |
414 | } |
415 | ||
416 | static struct resource da8xx_emac_resources[] = { | |
417 | { | |
418 | .start = DA8XX_EMAC_CPPI_PORT_BASE, | |
d22960c8 | 419 | .end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1, |
55c79a40 MG |
420 | .flags = IORESOURCE_MEM, |
421 | }, | |
422 | { | |
423 | .start = IRQ_DA8XX_C0_RX_THRESH_PULSE, | |
424 | .end = IRQ_DA8XX_C0_RX_THRESH_PULSE, | |
425 | .flags = IORESOURCE_IRQ, | |
426 | }, | |
427 | { | |
428 | .start = IRQ_DA8XX_C0_RX_PULSE, | |
429 | .end = IRQ_DA8XX_C0_RX_PULSE, | |
430 | .flags = IORESOURCE_IRQ, | |
431 | }, | |
432 | { | |
433 | .start = IRQ_DA8XX_C0_TX_PULSE, | |
434 | .end = IRQ_DA8XX_C0_TX_PULSE, | |
435 | .flags = IORESOURCE_IRQ, | |
436 | }, | |
437 | { | |
438 | .start = IRQ_DA8XX_C0_MISC_PULSE, | |
439 | .end = IRQ_DA8XX_C0_MISC_PULSE, | |
440 | .flags = IORESOURCE_IRQ, | |
441 | }, | |
442 | }; | |
443 | ||
444 | struct emac_platform_data da8xx_emac_pdata = { | |
445 | .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET, | |
446 | .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET, | |
447 | .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET, | |
55c79a40 MG |
448 | .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE, |
449 | .version = EMAC_VERSION_2, | |
450 | }; | |
451 | ||
452 | static struct platform_device da8xx_emac_device = { | |
453 | .name = "davinci_emac", | |
454 | .id = 1, | |
455 | .dev = { | |
456 | .platform_data = &da8xx_emac_pdata, | |
457 | }, | |
458 | .num_resources = ARRAY_SIZE(da8xx_emac_resources), | |
459 | .resource = da8xx_emac_resources, | |
460 | }; | |
461 | ||
d22960c8 CC |
462 | static struct resource da8xx_mdio_resources[] = { |
463 | { | |
464 | .start = DA8XX_EMAC_MDIO_BASE, | |
465 | .end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1, | |
466 | .flags = IORESOURCE_MEM, | |
467 | }, | |
468 | }; | |
469 | ||
470 | static struct platform_device da8xx_mdio_device = { | |
471 | .name = "davinci_mdio", | |
472 | .id = 0, | |
473 | .num_resources = ARRAY_SIZE(da8xx_mdio_resources), | |
474 | .resource = da8xx_mdio_resources, | |
475 | }; | |
476 | ||
31f53cf3 MG |
477 | int __init da8xx_register_emac(void) |
478 | { | |
d22960c8 CC |
479 | int ret; |
480 | ||
481 | ret = platform_device_register(&da8xx_mdio_device); | |
482 | if (ret < 0) | |
483 | return ret; | |
484 | ret = platform_device_register(&da8xx_emac_device); | |
485 | if (ret < 0) | |
486 | return ret; | |
487 | ret = clk_add_alias(NULL, dev_name(&da8xx_mdio_device.dev), | |
488 | NULL, &da8xx_emac_device.dev); | |
489 | return ret; | |
31f53cf3 MG |
490 | } |
491 | ||
e33ef5e3 C |
492 | static struct resource da830_mcasp1_resources[] = { |
493 | { | |
494 | .name = "mcasp1", | |
495 | .start = DAVINCI_DA830_MCASP1_REG_BASE, | |
496 | .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1, | |
497 | .flags = IORESOURCE_MEM, | |
498 | }, | |
499 | /* TX event */ | |
500 | { | |
501 | .start = DAVINCI_DA830_DMA_MCASP1_AXEVT, | |
502 | .end = DAVINCI_DA830_DMA_MCASP1_AXEVT, | |
503 | .flags = IORESOURCE_DMA, | |
504 | }, | |
505 | /* RX event */ | |
506 | { | |
507 | .start = DAVINCI_DA830_DMA_MCASP1_AREVT, | |
508 | .end = DAVINCI_DA830_DMA_MCASP1_AREVT, | |
509 | .flags = IORESOURCE_DMA, | |
510 | }, | |
511 | }; | |
512 | ||
513 | static struct platform_device da830_mcasp1_device = { | |
514 | .name = "davinci-mcasp", | |
515 | .id = 1, | |
516 | .num_resources = ARRAY_SIZE(da830_mcasp1_resources), | |
517 | .resource = da830_mcasp1_resources, | |
518 | }; | |
519 | ||
491214e1 C |
520 | static struct resource da850_mcasp_resources[] = { |
521 | { | |
522 | .name = "mcasp", | |
523 | .start = DAVINCI_DA8XX_MCASP0_REG_BASE, | |
524 | .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1, | |
525 | .flags = IORESOURCE_MEM, | |
526 | }, | |
527 | /* TX event */ | |
528 | { | |
529 | .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, | |
530 | .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, | |
531 | .flags = IORESOURCE_DMA, | |
532 | }, | |
533 | /* RX event */ | |
534 | { | |
535 | .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT, | |
536 | .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT, | |
537 | .flags = IORESOURCE_DMA, | |
538 | }, | |
539 | }; | |
540 | ||
541 | static struct platform_device da850_mcasp_device = { | |
542 | .name = "davinci-mcasp", | |
543 | .id = 0, | |
544 | .num_resources = ARRAY_SIZE(da850_mcasp_resources), | |
545 | .resource = da850_mcasp_resources, | |
546 | }; | |
547 | ||
b8864aa4 | 548 | void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata) |
e33ef5e3 | 549 | { |
491214e1 C |
550 | /* DA830/OMAP-L137 has 3 instances of McASP */ |
551 | if (cpu_is_davinci_da830() && id == 1) { | |
e33ef5e3 C |
552 | da830_mcasp1_device.dev.platform_data = pdata; |
553 | platform_device_register(&da830_mcasp1_device); | |
491214e1 C |
554 | } else if (cpu_is_davinci_da850()) { |
555 | da850_mcasp_device.dev.platform_data = pdata; | |
556 | platform_device_register(&da850_mcasp_device); | |
e33ef5e3 C |
557 | } |
558 | } | |
5cbdf276 | 559 | |
8e0d72d2 MP |
560 | static struct resource da8xx_pruss_resources[] = { |
561 | { | |
562 | .start = DA8XX_PRUSS_MEM_BASE, | |
563 | .end = DA8XX_PRUSS_MEM_BASE + 0xFFFF, | |
564 | .flags = IORESOURCE_MEM, | |
565 | }, | |
566 | { | |
567 | .start = IRQ_DA8XX_EVTOUT0, | |
568 | .end = IRQ_DA8XX_EVTOUT0, | |
569 | .flags = IORESOURCE_IRQ, | |
570 | }, | |
571 | { | |
572 | .start = IRQ_DA8XX_EVTOUT1, | |
573 | .end = IRQ_DA8XX_EVTOUT1, | |
574 | .flags = IORESOURCE_IRQ, | |
575 | }, | |
576 | { | |
577 | .start = IRQ_DA8XX_EVTOUT2, | |
578 | .end = IRQ_DA8XX_EVTOUT2, | |
579 | .flags = IORESOURCE_IRQ, | |
580 | }, | |
581 | { | |
582 | .start = IRQ_DA8XX_EVTOUT3, | |
583 | .end = IRQ_DA8XX_EVTOUT3, | |
584 | .flags = IORESOURCE_IRQ, | |
585 | }, | |
586 | { | |
587 | .start = IRQ_DA8XX_EVTOUT4, | |
588 | .end = IRQ_DA8XX_EVTOUT4, | |
589 | .flags = IORESOURCE_IRQ, | |
590 | }, | |
591 | { | |
592 | .start = IRQ_DA8XX_EVTOUT5, | |
593 | .end = IRQ_DA8XX_EVTOUT5, | |
594 | .flags = IORESOURCE_IRQ, | |
595 | }, | |
596 | { | |
597 | .start = IRQ_DA8XX_EVTOUT6, | |
598 | .end = IRQ_DA8XX_EVTOUT6, | |
599 | .flags = IORESOURCE_IRQ, | |
600 | }, | |
601 | { | |
602 | .start = IRQ_DA8XX_EVTOUT7, | |
603 | .end = IRQ_DA8XX_EVTOUT7, | |
604 | .flags = IORESOURCE_IRQ, | |
605 | }, | |
606 | }; | |
607 | ||
608 | static struct uio_pruss_pdata da8xx_uio_pruss_pdata = { | |
609 | .pintc_base = 0x4000, | |
610 | }; | |
611 | ||
612 | static struct platform_device da8xx_uio_pruss_dev = { | |
613 | .name = "pruss_uio", | |
614 | .id = -1, | |
615 | .num_resources = ARRAY_SIZE(da8xx_pruss_resources), | |
616 | .resource = da8xx_pruss_resources, | |
617 | .dev = { | |
618 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
619 | .platform_data = &da8xx_uio_pruss_pdata, | |
620 | } | |
621 | }; | |
622 | ||
623 | int __init da8xx_register_uio_pruss(void) | |
624 | { | |
625 | da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool(); | |
626 | return platform_device_register(&da8xx_uio_pruss_dev); | |
627 | } | |
628 | ||
5cbdf276 | 629 | static struct lcd_ctrl_config lcd_cfg = { |
3b43ad20 | 630 | .panel_shade = COLOR_ACTIVE, |
5cbdf276 | 631 | .bpp = 16, |
5cbdf276 SR |
632 | }; |
633 | ||
b9e6342b MG |
634 | struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = { |
635 | .manu_name = "sharp", | |
636 | .controller_data = &lcd_cfg, | |
637 | .type = "Sharp_LCD035Q3DG01", | |
638 | }; | |
639 | ||
640 | struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = { | |
641 | .manu_name = "sharp", | |
642 | .controller_data = &lcd_cfg, | |
643 | .type = "Sharp_LK043T1DG01", | |
5cbdf276 SR |
644 | }; |
645 | ||
646 | static struct resource da8xx_lcdc_resources[] = { | |
647 | [0] = { /* registers */ | |
648 | .start = DA8XX_LCD_CNTRL_BASE, | |
649 | .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1, | |
650 | .flags = IORESOURCE_MEM, | |
651 | }, | |
652 | [1] = { /* interrupt */ | |
653 | .start = IRQ_DA8XX_LCDINT, | |
654 | .end = IRQ_DA8XX_LCDINT, | |
655 | .flags = IORESOURCE_IRQ, | |
656 | }, | |
657 | }; | |
658 | ||
b9e6342b | 659 | static struct platform_device da8xx_lcdc_device = { |
5cbdf276 SR |
660 | .name = "da8xx_lcdc", |
661 | .id = 0, | |
662 | .num_resources = ARRAY_SIZE(da8xx_lcdc_resources), | |
663 | .resource = da8xx_lcdc_resources, | |
5cbdf276 SR |
664 | }; |
665 | ||
b9e6342b | 666 | int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata) |
5cbdf276 | 667 | { |
b9e6342b MG |
668 | da8xx_lcdc_device.dev.platform_data = pdata; |
669 | return platform_device_register(&da8xx_lcdc_device); | |
5cbdf276 | 670 | } |
700691f2 SR |
671 | |
672 | static struct resource da8xx_mmcsd0_resources[] = { | |
673 | { /* registers */ | |
674 | .start = DA8XX_MMCSD0_BASE, | |
675 | .end = DA8XX_MMCSD0_BASE + SZ_4K - 1, | |
676 | .flags = IORESOURCE_MEM, | |
677 | }, | |
678 | { /* interrupt */ | |
679 | .start = IRQ_DA8XX_MMCSDINT0, | |
680 | .end = IRQ_DA8XX_MMCSDINT0, | |
681 | .flags = IORESOURCE_IRQ, | |
682 | }, | |
683 | { /* DMA RX */ | |
e38c2b22 MW |
684 | .start = DA8XX_DMA_MMCSD0_RX, |
685 | .end = DA8XX_DMA_MMCSD0_RX, | |
700691f2 SR |
686 | .flags = IORESOURCE_DMA, |
687 | }, | |
688 | { /* DMA TX */ | |
e38c2b22 MW |
689 | .start = DA8XX_DMA_MMCSD0_TX, |
690 | .end = DA8XX_DMA_MMCSD0_TX, | |
700691f2 SR |
691 | .flags = IORESOURCE_DMA, |
692 | }, | |
693 | }; | |
694 | ||
695 | static struct platform_device da8xx_mmcsd0_device = { | |
d7ca4c75 | 696 | .name = "da830-mmc", |
700691f2 SR |
697 | .id = 0, |
698 | .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources), | |
699 | .resource = da8xx_mmcsd0_resources, | |
700 | }; | |
701 | ||
702 | int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config) | |
703 | { | |
704 | da8xx_mmcsd0_device.dev.platform_data = config; | |
705 | return platform_device_register(&da8xx_mmcsd0_device); | |
706 | } | |
c51df70b | 707 | |
b8241aef JK |
708 | #ifdef CONFIG_ARCH_DAVINCI_DA850 |
709 | static struct resource da850_mmcsd1_resources[] = { | |
710 | { /* registers */ | |
711 | .start = DA850_MMCSD1_BASE, | |
712 | .end = DA850_MMCSD1_BASE + SZ_4K - 1, | |
713 | .flags = IORESOURCE_MEM, | |
714 | }, | |
715 | { /* interrupt */ | |
716 | .start = IRQ_DA850_MMCSDINT0_1, | |
717 | .end = IRQ_DA850_MMCSDINT0_1, | |
718 | .flags = IORESOURCE_IRQ, | |
719 | }, | |
720 | { /* DMA RX */ | |
e38c2b22 MW |
721 | .start = DA850_DMA_MMCSD1_RX, |
722 | .end = DA850_DMA_MMCSD1_RX, | |
b8241aef JK |
723 | .flags = IORESOURCE_DMA, |
724 | }, | |
725 | { /* DMA TX */ | |
e38c2b22 MW |
726 | .start = DA850_DMA_MMCSD1_TX, |
727 | .end = DA850_DMA_MMCSD1_TX, | |
b8241aef JK |
728 | .flags = IORESOURCE_DMA, |
729 | }, | |
730 | }; | |
731 | ||
732 | static struct platform_device da850_mmcsd1_device = { | |
d7ca4c75 | 733 | .name = "da830-mmc", |
b8241aef JK |
734 | .id = 1, |
735 | .num_resources = ARRAY_SIZE(da850_mmcsd1_resources), | |
736 | .resource = da850_mmcsd1_resources, | |
737 | }; | |
738 | ||
739 | int __init da850_register_mmcsd1(struct davinci_mmc_config *config) | |
740 | { | |
741 | da850_mmcsd1_device.dev.platform_data = config; | |
742 | return platform_device_register(&da850_mmcsd1_device); | |
743 | } | |
744 | #endif | |
745 | ||
5c71d618 RT |
746 | static struct resource da8xx_rproc_resources[] = { |
747 | { /* DSP boot address */ | |
748 | .start = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG, | |
749 | .end = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3, | |
750 | .flags = IORESOURCE_MEM, | |
751 | }, | |
752 | { /* DSP interrupt registers */ | |
753 | .start = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG, | |
754 | .end = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7, | |
755 | .flags = IORESOURCE_MEM, | |
756 | }, | |
757 | { /* dsp irq */ | |
758 | .start = IRQ_DA8XX_CHIPINT0, | |
759 | .end = IRQ_DA8XX_CHIPINT0, | |
760 | .flags = IORESOURCE_IRQ, | |
761 | }, | |
762 | }; | |
763 | ||
764 | static struct platform_device da8xx_dsp = { | |
765 | .name = "davinci-rproc", | |
766 | .dev = { | |
767 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
768 | }, | |
769 | .num_resources = ARRAY_SIZE(da8xx_rproc_resources), | |
770 | .resource = da8xx_rproc_resources, | |
771 | }; | |
772 | ||
773 | #if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC) | |
774 | ||
775 | static phys_addr_t rproc_base __initdata; | |
776 | static unsigned long rproc_size __initdata; | |
777 | ||
778 | static int __init early_rproc_mem(char *p) | |
779 | { | |
780 | char *endp; | |
781 | ||
782 | if (p == NULL) | |
783 | return 0; | |
784 | ||
785 | rproc_size = memparse(p, &endp); | |
786 | if (*endp == '@') | |
787 | rproc_base = memparse(endp + 1, NULL); | |
788 | ||
789 | return 0; | |
790 | } | |
791 | early_param("rproc_mem", early_rproc_mem); | |
792 | ||
793 | void __init da8xx_rproc_reserve_cma(void) | |
794 | { | |
795 | int ret; | |
796 | ||
797 | if (!rproc_base || !rproc_size) { | |
798 | pr_err("%s: 'rproc_mem=nn@address' badly specified\n" | |
799 | " 'nn' and 'address' must both be non-zero\n", | |
800 | __func__); | |
801 | ||
802 | return; | |
803 | } | |
804 | ||
805 | pr_info("%s: reserving 0x%lx @ 0x%lx...\n", | |
806 | __func__, rproc_size, (unsigned long)rproc_base); | |
807 | ||
808 | ret = dma_declare_contiguous(&da8xx_dsp.dev, rproc_size, rproc_base, 0); | |
809 | if (ret) | |
810 | pr_err("%s: dma_declare_contiguous failed %d\n", __func__, ret); | |
811 | } | |
812 | ||
813 | #else | |
814 | ||
815 | void __init da8xx_rproc_reserve_cma(void) | |
816 | { | |
817 | } | |
818 | ||
819 | #endif | |
820 | ||
821 | int __init da8xx_register_rproc(void) | |
822 | { | |
823 | int ret; | |
824 | ||
825 | ret = platform_device_register(&da8xx_dsp); | |
826 | if (ret) | |
827 | pr_err("%s: can't register DSP device: %d\n", __func__, ret); | |
828 | ||
829 | return ret; | |
830 | }; | |
831 | ||
c51df70b MG |
832 | static struct resource da8xx_rtc_resources[] = { |
833 | { | |
834 | .start = DA8XX_RTC_BASE, | |
835 | .end = DA8XX_RTC_BASE + SZ_4K - 1, | |
836 | .flags = IORESOURCE_MEM, | |
837 | }, | |
838 | { /* timer irq */ | |
839 | .start = IRQ_DA8XX_RTC, | |
840 | .end = IRQ_DA8XX_RTC, | |
841 | .flags = IORESOURCE_IRQ, | |
842 | }, | |
843 | { /* alarm irq */ | |
844 | .start = IRQ_DA8XX_RTC, | |
845 | .end = IRQ_DA8XX_RTC, | |
846 | .flags = IORESOURCE_IRQ, | |
847 | }, | |
848 | }; | |
849 | ||
850 | static struct platform_device da8xx_rtc_device = { | |
852168c9 | 851 | .name = "da830-rtc", |
c51df70b MG |
852 | .id = -1, |
853 | .num_resources = ARRAY_SIZE(da8xx_rtc_resources), | |
854 | .resource = da8xx_rtc_resources, | |
855 | }; | |
856 | ||
857 | int da8xx_register_rtc(void) | |
858 | { | |
75c99bb0 | 859 | int ret; |
c51df70b | 860 | |
75c99bb0 SN |
861 | ret = platform_device_register(&da8xx_rtc_device); |
862 | if (!ret) | |
863 | /* Atleast on DA850, RTC is a wakeup source */ | |
864 | device_init_wakeup(&da8xx_rtc_device.dev, true); | |
865 | ||
866 | return ret; | |
c51df70b | 867 | } |
1960e693 | 868 | |
948c66df SN |
869 | static void __iomem *da8xx_ddr2_ctlr_base; |
870 | void __iomem * __init da8xx_get_mem_ctlr(void) | |
871 | { | |
872 | if (da8xx_ddr2_ctlr_base) | |
873 | return da8xx_ddr2_ctlr_base; | |
874 | ||
875 | da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K); | |
876 | if (!da8xx_ddr2_ctlr_base) | |
d2e0c18a | 877 | pr_warn("%s: Unable to map DDR2 controller", __func__); |
948c66df SN |
878 | |
879 | return da8xx_ddr2_ctlr_base; | |
880 | } | |
881 | ||
1960e693 SN |
882 | static struct resource da8xx_cpuidle_resources[] = { |
883 | { | |
884 | .start = DA8XX_DDR2_CTL_BASE, | |
885 | .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1, | |
886 | .flags = IORESOURCE_MEM, | |
887 | }, | |
888 | }; | |
889 | ||
890 | /* DA8XX devices support DDR2 power down */ | |
891 | static struct davinci_cpuidle_config da8xx_cpuidle_pdata = { | |
892 | .ddr2_pdown = 1, | |
893 | }; | |
894 | ||
895 | ||
896 | static struct platform_device da8xx_cpuidle_device = { | |
897 | .name = "cpuidle-davinci", | |
898 | .num_resources = ARRAY_SIZE(da8xx_cpuidle_resources), | |
899 | .resource = da8xx_cpuidle_resources, | |
900 | .dev = { | |
901 | .platform_data = &da8xx_cpuidle_pdata, | |
902 | }, | |
903 | }; | |
904 | ||
905 | int __init da8xx_register_cpuidle(void) | |
906 | { | |
948c66df SN |
907 | da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr(); |
908 | ||
1960e693 SN |
909 | return platform_device_register(&da8xx_cpuidle_device); |
910 | } | |
54ce6883 MW |
911 | |
912 | static struct resource da8xx_spi0_resources[] = { | |
913 | [0] = { | |
914 | .start = DA8XX_SPI0_BASE, | |
915 | .end = DA8XX_SPI0_BASE + SZ_4K - 1, | |
916 | .flags = IORESOURCE_MEM, | |
917 | }, | |
918 | [1] = { | |
919 | .start = IRQ_DA8XX_SPINT0, | |
920 | .end = IRQ_DA8XX_SPINT0, | |
921 | .flags = IORESOURCE_IRQ, | |
922 | }, | |
923 | [2] = { | |
924 | .start = DA8XX_DMA_SPI0_RX, | |
925 | .end = DA8XX_DMA_SPI0_RX, | |
926 | .flags = IORESOURCE_DMA, | |
927 | }, | |
928 | [3] = { | |
929 | .start = DA8XX_DMA_SPI0_TX, | |
930 | .end = DA8XX_DMA_SPI0_TX, | |
931 | .flags = IORESOURCE_DMA, | |
932 | }, | |
933 | }; | |
934 | ||
935 | static struct resource da8xx_spi1_resources[] = { | |
936 | [0] = { | |
9e7d24f6 SS |
937 | .start = DA830_SPI1_BASE, |
938 | .end = DA830_SPI1_BASE + SZ_4K - 1, | |
54ce6883 MW |
939 | .flags = IORESOURCE_MEM, |
940 | }, | |
941 | [1] = { | |
942 | .start = IRQ_DA8XX_SPINT1, | |
943 | .end = IRQ_DA8XX_SPINT1, | |
944 | .flags = IORESOURCE_IRQ, | |
945 | }, | |
946 | [2] = { | |
947 | .start = DA8XX_DMA_SPI1_RX, | |
948 | .end = DA8XX_DMA_SPI1_RX, | |
949 | .flags = IORESOURCE_DMA, | |
950 | }, | |
951 | [3] = { | |
952 | .start = DA8XX_DMA_SPI1_TX, | |
953 | .end = DA8XX_DMA_SPI1_TX, | |
954 | .flags = IORESOURCE_DMA, | |
955 | }, | |
956 | }; | |
957 | ||
0273612c | 958 | static struct davinci_spi_platform_data da8xx_spi_pdata[] = { |
54ce6883 MW |
959 | [0] = { |
960 | .version = SPI_VERSION_2, | |
961 | .intr_line = 1, | |
962 | .dma_event_q = EVENTQ_0, | |
963 | }, | |
964 | [1] = { | |
965 | .version = SPI_VERSION_2, | |
966 | .intr_line = 1, | |
967 | .dma_event_q = EVENTQ_0, | |
968 | }, | |
969 | }; | |
970 | ||
971 | static struct platform_device da8xx_spi_device[] = { | |
972 | [0] = { | |
973 | .name = "spi_davinci", | |
974 | .id = 0, | |
975 | .num_resources = ARRAY_SIZE(da8xx_spi0_resources), | |
976 | .resource = da8xx_spi0_resources, | |
977 | .dev = { | |
978 | .platform_data = &da8xx_spi_pdata[0], | |
979 | }, | |
980 | }, | |
981 | [1] = { | |
982 | .name = "spi_davinci", | |
983 | .id = 1, | |
984 | .num_resources = ARRAY_SIZE(da8xx_spi1_resources), | |
985 | .resource = da8xx_spi1_resources, | |
986 | .dev = { | |
987 | .platform_data = &da8xx_spi_pdata[1], | |
988 | }, | |
989 | }, | |
990 | }; | |
991 | ||
0273612c | 992 | int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect) |
54ce6883 | 993 | { |
54ce6883 MW |
994 | if (instance < 0 || instance > 1) |
995 | return -EINVAL; | |
996 | ||
0273612c | 997 | da8xx_spi_pdata[instance].num_chipselect = num_chipselect; |
54ce6883 | 998 | |
9e7d24f6 SS |
999 | if (instance == 1 && cpu_is_davinci_da850()) { |
1000 | da8xx_spi1_resources[0].start = DA850_SPI1_BASE; | |
1001 | da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1; | |
1002 | } | |
1003 | ||
54ce6883 MW |
1004 | return platform_device_register(&da8xx_spi_device[instance]); |
1005 | } | |
cbb2c961 SN |
1006 | |
1007 | #ifdef CONFIG_ARCH_DAVINCI_DA850 | |
1008 | ||
1009 | static struct resource da850_sata_resources[] = { | |
1010 | { | |
1011 | .start = DA850_SATA_BASE, | |
1012 | .end = DA850_SATA_BASE + 0x1fff, | |
1013 | .flags = IORESOURCE_MEM, | |
1014 | }, | |
1015 | { | |
1016 | .start = IRQ_DA850_SATAINT, | |
1017 | .flags = IORESOURCE_IRQ, | |
1018 | }, | |
1019 | }; | |
1020 | ||
1021 | /* SATA PHY Control Register offset from AHCI base */ | |
1022 | #define SATA_P0PHYCR_REG 0x178 | |
1023 | ||
1024 | #define SATA_PHY_MPY(x) ((x) << 0) | |
1025 | #define SATA_PHY_LOS(x) ((x) << 6) | |
1026 | #define SATA_PHY_RXCDR(x) ((x) << 10) | |
1027 | #define SATA_PHY_RXEQ(x) ((x) << 13) | |
1028 | #define SATA_PHY_TXSWING(x) ((x) << 19) | |
1029 | #define SATA_PHY_ENPLL(x) ((x) << 31) | |
1030 | ||
1031 | static struct clk *da850_sata_clk; | |
1032 | static unsigned long da850_sata_refclkpn; | |
1033 | ||
1034 | /* Supported DA850 SATA crystal frequencies */ | |
1035 | #define KHZ_TO_HZ(freq) ((freq) * 1000) | |
1036 | static unsigned long da850_sata_xtal[] = { | |
1037 | KHZ_TO_HZ(300000), | |
1038 | KHZ_TO_HZ(250000), | |
1039 | 0, /* Reserved */ | |
1040 | KHZ_TO_HZ(187500), | |
1041 | KHZ_TO_HZ(150000), | |
1042 | KHZ_TO_HZ(125000), | |
1043 | KHZ_TO_HZ(120000), | |
1044 | KHZ_TO_HZ(100000), | |
1045 | KHZ_TO_HZ(75000), | |
1046 | KHZ_TO_HZ(60000), | |
1047 | }; | |
1048 | ||
1049 | static int da850_sata_init(struct device *dev, void __iomem *addr) | |
1050 | { | |
1051 | int i, ret; | |
1052 | unsigned int val; | |
1053 | ||
1054 | da850_sata_clk = clk_get(dev, NULL); | |
1055 | if (IS_ERR(da850_sata_clk)) | |
1056 | return PTR_ERR(da850_sata_clk); | |
1057 | ||
b6f1ffed | 1058 | ret = clk_prepare_enable(da850_sata_clk); |
cbb2c961 SN |
1059 | if (ret) |
1060 | goto err0; | |
1061 | ||
1062 | /* Enable SATA clock receiver */ | |
1063 | val = __raw_readl(DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG)); | |
1064 | val &= ~BIT(0); | |
1065 | __raw_writel(val, DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG)); | |
1066 | ||
1067 | /* Get the multiplier needed for 1.5GHz PLL output */ | |
1068 | for (i = 0; i < ARRAY_SIZE(da850_sata_xtal); i++) | |
1069 | if (da850_sata_xtal[i] == da850_sata_refclkpn) | |
1070 | break; | |
1071 | ||
1072 | if (i == ARRAY_SIZE(da850_sata_xtal)) { | |
1073 | ret = -EINVAL; | |
1074 | goto err1; | |
1075 | } | |
1076 | ||
1077 | val = SATA_PHY_MPY(i + 1) | | |
1078 | SATA_PHY_LOS(1) | | |
1079 | SATA_PHY_RXCDR(4) | | |
1080 | SATA_PHY_RXEQ(1) | | |
1081 | SATA_PHY_TXSWING(3) | | |
1082 | SATA_PHY_ENPLL(1); | |
1083 | ||
1084 | __raw_writel(val, addr + SATA_P0PHYCR_REG); | |
1085 | ||
1086 | return 0; | |
1087 | ||
1088 | err1: | |
b6f1ffed | 1089 | clk_disable_unprepare(da850_sata_clk); |
cbb2c961 SN |
1090 | err0: |
1091 | clk_put(da850_sata_clk); | |
1092 | return ret; | |
1093 | } | |
1094 | ||
1095 | static void da850_sata_exit(struct device *dev) | |
1096 | { | |
b6f1ffed | 1097 | clk_disable_unprepare(da850_sata_clk); |
cbb2c961 SN |
1098 | clk_put(da850_sata_clk); |
1099 | } | |
1100 | ||
1101 | static struct ahci_platform_data da850_sata_pdata = { | |
1102 | .init = da850_sata_init, | |
1103 | .exit = da850_sata_exit, | |
1104 | }; | |
1105 | ||
1106 | static u64 da850_sata_dmamask = DMA_BIT_MASK(32); | |
1107 | ||
1108 | static struct platform_device da850_sata_device = { | |
1109 | .name = "ahci", | |
1110 | .id = -1, | |
1111 | .dev = { | |
1112 | .platform_data = &da850_sata_pdata, | |
1113 | .dma_mask = &da850_sata_dmamask, | |
1114 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
1115 | }, | |
1116 | .num_resources = ARRAY_SIZE(da850_sata_resources), | |
1117 | .resource = da850_sata_resources, | |
1118 | }; | |
1119 | ||
1120 | int __init da850_register_sata(unsigned long refclkpn) | |
1121 | { | |
1122 | da850_sata_refclkpn = refclkpn; | |
1123 | if (!da850_sata_refclkpn) | |
1124 | return -EINVAL; | |
1125 | ||
1126 | return platform_device_register(&da850_sata_device); | |
1127 | } | |
1128 | #endif |