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ARM: restart: cns3xxx: use new restart hook
[deliverable/linux.git] / arch / arm / mach-davinci / devices-da8xx.c
CommitLineData
55c79a40
MG		 1/*
2 * DA8XX/OMAP L1XX platform device data
3 *
4 * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
5 * Derived from code that was:
6 * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
55c79a40
MG		 13#include <linux/init.h>
14#include <linux/platform_device.h>
15#include <linux/dma-mapping.h>
16#include <linux/serial_8250.h>
cbb2c961
SN		 17#include <linux/ahci_platform.h>
18#include <linux/clk.h>
55c79a40
MG		 19
20#include <mach/cputype.h>
21#include <mach/common.h>
22#include <mach/time.h>
23#include <mach/da8xx.h>
1960e693 24#include <mach/cpuidle.h>
55c79a40
MG		 25
26#include "clock.h"
27
28#define DA8XX_TPCC_BASE 0x01c00000
29#define DA8XX_TPTC0_BASE 0x01c08000
30#define DA8XX_TPTC1_BASE 0x01c08400
31#define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
32#define DA8XX_I2C0_BASE 0x01c22000
8ac764e3
SS		 33#define DA8XX_RTC_BASE 0x01c23000
34#define DA8XX_MMCSD0_BASE 0x01c40000
35#define DA8XX_SPI0_BASE 0x01c41000
36#define DA830_SPI1_BASE 0x01e12000
37#define DA8XX_LCD_CNTRL_BASE 0x01e13000
cbb2c961 38#define DA850_SATA_BASE 0x01e18000
8ac764e3 39#define DA850_MMCSD1_BASE 0x01e1b000
55c79a40
MG		 40#define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000
41#define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000
42#define DA8XX_EMAC_CPGMAC_BASE 0x01e23000
43#define DA8XX_EMAC_MDIO_BASE 0x01e24000
55c79a40 44#define DA8XX_I2C1_BASE 0x01e28000
8ac764e3
SS		 45#define DA850_TPCC1_BASE 0x01e30000
46#define DA850_TPTC2_BASE 0x01e38000
9e7d24f6 47#define DA850_SPI1_BASE 0x01f0e000
8ac764e3 48#define DA8XX_DDR2_CTL_BASE 0xb0000000
55c79a40
MG		 49
50#define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000
51#define DA8XX_EMAC_MOD_REG_OFFSET 0x2000
52#define DA8XX_EMAC_RAM_OFFSET 0x0000
55c79a40
MG		 53#define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
54
54ce6883
MW		 55#define DA8XX_DMA_SPI0_RX EDMA_CTLR_CHAN(0, 14)
56#define DA8XX_DMA_SPI0_TX EDMA_CTLR_CHAN(0, 15)
e38c2b22
MW		 57#define DA8XX_DMA_MMCSD0_RX EDMA_CTLR_CHAN(0, 16)
58#define DA8XX_DMA_MMCSD0_TX EDMA_CTLR_CHAN(0, 17)
54ce6883
MW		 59#define DA8XX_DMA_SPI1_RX EDMA_CTLR_CHAN(0, 18)
60#define DA8XX_DMA_SPI1_TX EDMA_CTLR_CHAN(0, 19)
e38c2b22
MW		 61#define DA850_DMA_MMCSD1_RX EDMA_CTLR_CHAN(1, 28)
62#define DA850_DMA_MMCSD1_TX EDMA_CTLR_CHAN(1, 29)
63
d2de0582
SN		 64void __iomem *da8xx_syscfg0_base;
65void __iomem *da8xx_syscfg1_base;
6a28adef 66
55c79a40
MG		 67static struct plat_serial8250_port da8xx_serial_pdata[] = {
68 {
69 .mapbase = DA8XX_UART0_BASE,
70 .irq = IRQ_DA8XX_UARTINT0,
71 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
72 UPF_IOREMAP,
73 .iotype = UPIO_MEM,
74 .regshift = 2,
75 },
76 {
77 .mapbase = DA8XX_UART1_BASE,
78 .irq = IRQ_DA8XX_UARTINT1,
79 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
80 UPF_IOREMAP,
81 .iotype = UPIO_MEM,
82 .regshift = 2,
83 },
84 {
85 .mapbase = DA8XX_UART2_BASE,
86 .irq = IRQ_DA8XX_UARTINT2,
87 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
88 UPF_IOREMAP,
89 .iotype = UPIO_MEM,
90 .regshift = 2,
91 },
92 {
93 .flags = 0,
94 },
95};
96
97struct platform_device da8xx_serial_device = {
98 .name = "serial8250",
99 .id = PLAT8250_DEV_PLATFORM,
100 .dev = {
101 .platform_data = da8xx_serial_pdata,
102 },
103};
104
55c79a40
MG		 105static const s8 da8xx_queue_tc_mapping[][2] = {
106 /* {event queue no, TC no} */
107 {0, 0},
108 {1, 1},
109 {-1, -1}
110};
111
112static const s8 da8xx_queue_priority_mapping[][2] = {
113 /* {event queue no, Priority} */
114 {0, 3},
115 {1, 7},
116 {-1, -1}
117};
118
3f995f2f
SR		 119static const s8 da850_queue_tc_mapping[][2] = {
120 /* {event queue no, TC no} */
121 {0, 0},
122 {-1, -1}
123};
124
125static const s8 da850_queue_priority_mapping[][2] = {
126 /* {event queue no, Priority} */
127 {0, 3},
128 {-1, -1}
129};
130
bc3ac9f3
SN		 131static struct edma_soc_info da830_edma_cc0_info = {
132 .n_channel = 32,
133 .n_region = 4,
134 .n_slot = 128,
135 .n_tc = 2,
136 .n_cc = 1,
137 .queue_tc_mapping = da8xx_queue_tc_mapping,
138 .queue_priority_mapping = da8xx_queue_priority_mapping,
f23fe857 139 .default_queue = EVENTQ_1,
bc3ac9f3
SN		 140};
141
142static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = {
143 &da830_edma_cc0_info,
55c79a40
MG		 144};
145
bc3ac9f3 146static struct edma_soc_info da850_edma_cc_info[] = {
3f995f2f
SR		 147 {
148 .n_channel = 32,
149 .n_region = 4,
150 .n_slot = 128,
151 .n_tc = 2,
152 .n_cc = 1,
153 .queue_tc_mapping = da8xx_queue_tc_mapping,
154 .queue_priority_mapping = da8xx_queue_priority_mapping,
f23fe857 155 .default_queue = EVENTQ_1,
3f995f2f
SR		 156 },
157 {
158 .n_channel = 32,
159 .n_region = 4,
160 .n_slot = 128,
161 .n_tc = 1,
162 .n_cc = 1,
163 .queue_tc_mapping = da850_queue_tc_mapping,
164 .queue_priority_mapping = da850_queue_priority_mapping,
f23fe857 165 .default_queue = EVENTQ_0,
3f995f2f
SR		 166 },
167};
168
bc3ac9f3
SN		 169static struct edma_soc_info *da850_edma_info[EDMA_MAX_CC] = {
170 &da850_edma_cc_info[0],
171 &da850_edma_cc_info[1],
172};
173
3f995f2f 174static struct resource da830_edma_resources[] = {
55c79a40
MG		 175 {
176 .name = "edma_cc0",
177 .start = DA8XX_TPCC_BASE,
178 .end = DA8XX_TPCC_BASE + SZ_32K - 1,
179 .flags = IORESOURCE_MEM,
180 },
181 {
182 .name = "edma_tc0",
183 .start = DA8XX_TPTC0_BASE,
184 .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
185 .flags = IORESOURCE_MEM,
186 },
187 {
188 .name = "edma_tc1",
189 .start = DA8XX_TPTC1_BASE,
190 .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
191 .flags = IORESOURCE_MEM,
192 },
193 {
194 .name = "edma0",
2259bbd4 195 .start = IRQ_DA8XX_CCINT0,
55c79a40
MG		 196 .flags = IORESOURCE_IRQ,
197 },
198 {
199 .name = "edma0_err",
200 .start = IRQ_DA8XX_CCERRINT,
201 .flags = IORESOURCE_IRQ,
202 },
203};
204
3f995f2f
SR		 205static struct resource da850_edma_resources[] = {
206 {
207 .name = "edma_cc0",
208 .start = DA8XX_TPCC_BASE,
209 .end = DA8XX_TPCC_BASE + SZ_32K - 1,
210 .flags = IORESOURCE_MEM,
211 },
212 {
213 .name = "edma_tc0",
214 .start = DA8XX_TPTC0_BASE,
215 .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
216 .flags = IORESOURCE_MEM,
217 },
218 {
219 .name = "edma_tc1",
220 .start = DA8XX_TPTC1_BASE,
221 .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
222 .flags = IORESOURCE_MEM,
223 },
224 {
225 .name = "edma_cc1",
226 .start = DA850_TPCC1_BASE,
227 .end = DA850_TPCC1_BASE + SZ_32K - 1,
228 .flags = IORESOURCE_MEM,
229 },
230 {
231 .name = "edma_tc2",
232 .start = DA850_TPTC2_BASE,
233 .end = DA850_TPTC2_BASE + SZ_1K - 1,
234 .flags = IORESOURCE_MEM,
235 },
236 {
237 .name = "edma0",
238 .start = IRQ_DA8XX_CCINT0,
239 .flags = IORESOURCE_IRQ,
240 },
241 {
242 .name = "edma0_err",
243 .start = IRQ_DA8XX_CCERRINT,
244 .flags = IORESOURCE_IRQ,
245 },
246 {
247 .name = "edma1",
248 .start = IRQ_DA850_CCINT1,
249 .flags = IORESOURCE_IRQ,
250 },
251 {
252 .name = "edma1_err",
253 .start = IRQ_DA850_CCERRINT1,
254 .flags = IORESOURCE_IRQ,
255 },
256};
257
258static struct platform_device da830_edma_device = {
55c79a40
MG		 259 .name = "edma",
260 .id = -1,
261 .dev = {
3f995f2f 262 .platform_data = da830_edma_info,
55c79a40 263 },
3f995f2f
SR		 264 .num_resources = ARRAY_SIZE(da830_edma_resources),
265 .resource = da830_edma_resources,
266};
267
268static struct platform_device da850_edma_device = {
269 .name = "edma",
270 .id = -1,
271 .dev = {
272 .platform_data = da850_edma_info,
273 },
274 .num_resources = ARRAY_SIZE(da850_edma_resources),
275 .resource = da850_edma_resources,
55c79a40
MG		 276};
277
a941c503 278int __init da830_register_edma(struct edma_rsv_info *rsv)
55c79a40 279{
a941c503 280 da830_edma_cc0_info.rsv = rsv;
3f995f2f 281
a941c503
RS		 282 return platform_device_register(&da830_edma_device);
283}
284
285int __init da850_register_edma(struct edma_rsv_info *rsv[2])
286{
287 if (rsv) {
288 da850_edma_cc_info[0].rsv = rsv[0];
289 da850_edma_cc_info[1].rsv = rsv[1];
290 }
3f995f2f 291
a941c503 292 return platform_device_register(&da850_edma_device);
55c79a40
MG		 293}
294
295static struct resource da8xx_i2c_resources0[] = {
296 {
297 .start = DA8XX_I2C0_BASE,
298 .end = DA8XX_I2C0_BASE + SZ_4K - 1,
299 .flags = IORESOURCE_MEM,
300 },
301 {
302 .start = IRQ_DA8XX_I2CINT0,
303 .end = IRQ_DA8XX_I2CINT0,
304 .flags = IORESOURCE_IRQ,
305 },
306};
307
308static struct platform_device da8xx_i2c_device0 = {
309 .name = "i2c_davinci",
310 .id = 1,
311 .num_resources = ARRAY_SIZE(da8xx_i2c_resources0),
312 .resource = da8xx_i2c_resources0,
313};
314
315static struct resource da8xx_i2c_resources1[] = {
316 {
317 .start = DA8XX_I2C1_BASE,
318 .end = DA8XX_I2C1_BASE + SZ_4K - 1,
319 .flags = IORESOURCE_MEM,
320 },
321 {
322 .start = IRQ_DA8XX_I2CINT1,
323 .end = IRQ_DA8XX_I2CINT1,
324 .flags = IORESOURCE_IRQ,
325 },
326};
327
328static struct platform_device da8xx_i2c_device1 = {
329 .name = "i2c_davinci",
330 .id = 2,
331 .num_resources = ARRAY_SIZE(da8xx_i2c_resources1),
332 .resource = da8xx_i2c_resources1,
333};
334
335int __init da8xx_register_i2c(int instance,
336 struct davinci_i2c_platform_data *pdata)
337{
338 struct platform_device *pdev;
339
340 if (instance == 0)
341 pdev = &da8xx_i2c_device0;
342 else if (instance == 1)
343 pdev = &da8xx_i2c_device1;
344 else
345 return -EINVAL;
346
347 pdev->dev.platform_data = pdata;
348 return platform_device_register(pdev);
349}
350
351static struct resource da8xx_watchdog_resources[] = {
352 {
353 .start = DA8XX_WDOG_BASE,
354 .end = DA8XX_WDOG_BASE + SZ_4K - 1,
355 .flags = IORESOURCE_MEM,
356 },
357};
358
c78a5bc2 359struct platform_device da8xx_wdt_device = {
55c79a40
MG		 360 .name = "watchdog",
361 .id = -1,
362 .num_resources = ARRAY_SIZE(da8xx_watchdog_resources),
363 .resource = da8xx_watchdog_resources,
364};
365
366int __init da8xx_register_watchdog(void)
367{
c78a5bc2 368 return platform_device_register(&da8xx_wdt_device);
55c79a40
MG		 369}
370
371static struct resource da8xx_emac_resources[] = {
372 {
373 .start = DA8XX_EMAC_CPPI_PORT_BASE,
d22960c8 374 .end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1,
55c79a40
MG		 375 .flags = IORESOURCE_MEM,
376 },
377 {
378 .start = IRQ_DA8XX_C0_RX_THRESH_PULSE,
379 .end = IRQ_DA8XX_C0_RX_THRESH_PULSE,
380 .flags = IORESOURCE_IRQ,
381 },
382 {
383 .start = IRQ_DA8XX_C0_RX_PULSE,
384 .end = IRQ_DA8XX_C0_RX_PULSE,
385 .flags = IORESOURCE_IRQ,
386 },
387 {
388 .start = IRQ_DA8XX_C0_TX_PULSE,
389 .end = IRQ_DA8XX_C0_TX_PULSE,
390 .flags = IORESOURCE_IRQ,
391 },
392 {
393 .start = IRQ_DA8XX_C0_MISC_PULSE,
394 .end = IRQ_DA8XX_C0_MISC_PULSE,
395 .flags = IORESOURCE_IRQ,
396 },
397};
398
399struct emac_platform_data da8xx_emac_pdata = {
400 .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET,
401 .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET,
402 .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET,
55c79a40
MG		 403 .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE,
404 .version = EMAC_VERSION_2,
405};
406
407static struct platform_device da8xx_emac_device = {
408 .name = "davinci_emac",
409 .id = 1,
410 .dev = {
411 .platform_data = &da8xx_emac_pdata,
412 },
413 .num_resources = ARRAY_SIZE(da8xx_emac_resources),
414 .resource = da8xx_emac_resources,
415};
416
d22960c8
CC		 417static struct resource da8xx_mdio_resources[] = {
418 {
419 .start = DA8XX_EMAC_MDIO_BASE,
420 .end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1,
421 .flags = IORESOURCE_MEM,
422 },
423};
424
425static struct platform_device da8xx_mdio_device = {
426 .name = "davinci_mdio",
427 .id = 0,
428 .num_resources = ARRAY_SIZE(da8xx_mdio_resources),
429 .resource = da8xx_mdio_resources,
430};
431
31f53cf3
MG		 432int __init da8xx_register_emac(void)
433{
d22960c8
CC		 434 int ret;
435
436 ret = platform_device_register(&da8xx_mdio_device);
437 if (ret < 0)
438 return ret;
439 ret = platform_device_register(&da8xx_emac_device);
440 if (ret < 0)
441 return ret;
442 ret = clk_add_alias(NULL, dev_name(&da8xx_mdio_device.dev),
443 NULL, &da8xx_emac_device.dev);
444 return ret;
31f53cf3
MG		 445}
446
e33ef5e3
C		 447static struct resource da830_mcasp1_resources[] = {
448 {
449 .name = "mcasp1",
450 .start = DAVINCI_DA830_MCASP1_REG_BASE,
451 .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
452 .flags = IORESOURCE_MEM,
453 },
454 /* TX event */
455 {
456 .start = DAVINCI_DA830_DMA_MCASP1_AXEVT,
457 .end = DAVINCI_DA830_DMA_MCASP1_AXEVT,
458 .flags = IORESOURCE_DMA,
459 },
460 /* RX event */
461 {
462 .start = DAVINCI_DA830_DMA_MCASP1_AREVT,
463 .end = DAVINCI_DA830_DMA_MCASP1_AREVT,
464 .flags = IORESOURCE_DMA,
465 },
466};
467
468static struct platform_device da830_mcasp1_device = {
469 .name = "davinci-mcasp",
470 .id = 1,
471 .num_resources = ARRAY_SIZE(da830_mcasp1_resources),
472 .resource = da830_mcasp1_resources,
473};
474
491214e1
C		 475static struct resource da850_mcasp_resources[] = {
476 {
477 .name = "mcasp",
478 .start = DAVINCI_DA8XX_MCASP0_REG_BASE,
479 .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
480 .flags = IORESOURCE_MEM,
481 },
482 /* TX event */
483 {
484 .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
485 .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
486 .flags = IORESOURCE_DMA,
487 },
488 /* RX event */
489 {
490 .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
491 .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
492 .flags = IORESOURCE_DMA,
493 },
494};
495
496static struct platform_device da850_mcasp_device = {
497 .name = "davinci-mcasp",
498 .id = 0,
499 .num_resources = ARRAY_SIZE(da850_mcasp_resources),
500 .resource = da850_mcasp_resources,
501};
502
7e9f1945 503static struct platform_device davinci_pcm_device = {
b3d1ffb2
RS		 504 .name = "davinci-pcm-audio",
505 .id = -1,
506};
507
b8864aa4 508void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
e33ef5e3 509{
b3d1ffb2
RS		 510 platform_device_register(&davinci_pcm_device);
511
491214e1
C		 512 /* DA830/OMAP-L137 has 3 instances of McASP */
513 if (cpu_is_davinci_da830() && id == 1) {
e33ef5e3
C		 514 da830_mcasp1_device.dev.platform_data = pdata;
515 platform_device_register(&da830_mcasp1_device);
491214e1
C		 516 } else if (cpu_is_davinci_da850()) {
517 da850_mcasp_device.dev.platform_data = pdata;
518 platform_device_register(&da850_mcasp_device);
e33ef5e3
C		 519 }
520}
5cbdf276
SR		 521
522static const struct display_panel disp_panel = {
523 QVGA,
524 16,
525 16,
526 COLOR_ACTIVE,
527};
528
529static struct lcd_ctrl_config lcd_cfg = {
530 &disp_panel,
531 .ac_bias = 255,
532 .ac_bias_intrpt = 0,
533 .dma_burst_sz = 16,
534 .bpp = 16,
535 .fdd = 255,
536 .tft_alt_mode = 0,
537 .stn_565_mode = 0,
538 .mono_8bit_mode = 0,
539 .invert_line_clock = 1,
540 .invert_frm_clock = 1,
541 .sync_edge = 0,
542 .sync_ctrl = 1,
543 .raster_order = 0,
544};
545
b9e6342b
MG		 546struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
547 .manu_name = "sharp",
548 .controller_data = &lcd_cfg,
549 .type = "Sharp_LCD035Q3DG01",
550};
551
552struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
553 .manu_name = "sharp",
554 .controller_data = &lcd_cfg,
555 .type = "Sharp_LK043T1DG01",
5cbdf276
SR		 556};
557
558static struct resource da8xx_lcdc_resources[] = {
559 [0] = { /* registers */
560 .start = DA8XX_LCD_CNTRL_BASE,
561 .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
562 .flags = IORESOURCE_MEM,
563 },
564 [1] = { /* interrupt */
565 .start = IRQ_DA8XX_LCDINT,
566 .end = IRQ_DA8XX_LCDINT,
567 .flags = IORESOURCE_IRQ,
568 },
569};
570
b9e6342b 571static struct platform_device da8xx_lcdc_device = {
5cbdf276
SR		 572 .name = "da8xx_lcdc",
573 .id = 0,
574 .num_resources = ARRAY_SIZE(da8xx_lcdc_resources),
575 .resource = da8xx_lcdc_resources,
5cbdf276
SR		 576};
577
b9e6342b 578int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
5cbdf276 579{
b9e6342b
MG		 580 da8xx_lcdc_device.dev.platform_data = pdata;
581 return platform_device_register(&da8xx_lcdc_device);
5cbdf276 582}
700691f2
SR		 583
584static struct resource da8xx_mmcsd0_resources[] = {
585 { /* registers */
586 .start = DA8XX_MMCSD0_BASE,
587 .end = DA8XX_MMCSD0_BASE + SZ_4K - 1,
588 .flags = IORESOURCE_MEM,
589 },
590 { /* interrupt */
591 .start = IRQ_DA8XX_MMCSDINT0,
592 .end = IRQ_DA8XX_MMCSDINT0,
593 .flags = IORESOURCE_IRQ,
594 },
595 { /* DMA RX */
e38c2b22
MW		 596 .start = DA8XX_DMA_MMCSD0_RX,
597 .end = DA8XX_DMA_MMCSD0_RX,
700691f2
SR		 598 .flags = IORESOURCE_DMA,
599 },
600 { /* DMA TX */
e38c2b22
MW		 601 .start = DA8XX_DMA_MMCSD0_TX,
602 .end = DA8XX_DMA_MMCSD0_TX,
700691f2
SR		 603 .flags = IORESOURCE_DMA,
604 },
605};
606
607static struct platform_device da8xx_mmcsd0_device = {
608 .name = "davinci_mmc",
609 .id = 0,
610 .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources),
611 .resource = da8xx_mmcsd0_resources,
612};
613
614int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
615{
616 da8xx_mmcsd0_device.dev.platform_data = config;
617 return platform_device_register(&da8xx_mmcsd0_device);
618}
c51df70b 619
b8241aef
JK		 620#ifdef CONFIG_ARCH_DAVINCI_DA850
621static struct resource da850_mmcsd1_resources[] = {
622 { /* registers */
623 .start = DA850_MMCSD1_BASE,
624 .end = DA850_MMCSD1_BASE + SZ_4K - 1,
625 .flags = IORESOURCE_MEM,
626 },
627 { /* interrupt */
628 .start = IRQ_DA850_MMCSDINT0_1,
629 .end = IRQ_DA850_MMCSDINT0_1,
630 .flags = IORESOURCE_IRQ,
631 },
632 { /* DMA RX */
e38c2b22
MW		 633 .start = DA850_DMA_MMCSD1_RX,
634 .end = DA850_DMA_MMCSD1_RX,
b8241aef
JK		 635 .flags = IORESOURCE_DMA,
636 },
637 { /* DMA TX */
e38c2b22
MW		 638 .start = DA850_DMA_MMCSD1_TX,
639 .end = DA850_DMA_MMCSD1_TX,
b8241aef
JK		 640 .flags = IORESOURCE_DMA,
641 },
642};
643
644static struct platform_device da850_mmcsd1_device = {
645 .name = "davinci_mmc",
646 .id = 1,
647 .num_resources = ARRAY_SIZE(da850_mmcsd1_resources),
648 .resource = da850_mmcsd1_resources,
649};
650
651int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
652{
653 da850_mmcsd1_device.dev.platform_data = config;
654 return platform_device_register(&da850_mmcsd1_device);
655}
656#endif
657
c51df70b
MG		 658static struct resource da8xx_rtc_resources[] = {
659 {
660 .start = DA8XX_RTC_BASE,
661 .end = DA8XX_RTC_BASE + SZ_4K - 1,
662 .flags = IORESOURCE_MEM,
663 },
664 { /* timer irq */
665 .start = IRQ_DA8XX_RTC,
666 .end = IRQ_DA8XX_RTC,
667 .flags = IORESOURCE_IRQ,
668 },
669 { /* alarm irq */
670 .start = IRQ_DA8XX_RTC,
671 .end = IRQ_DA8XX_RTC,
672 .flags = IORESOURCE_IRQ,
673 },
674};
675
676static struct platform_device da8xx_rtc_device = {
677 .name = "omap_rtc",
678 .id = -1,
679 .num_resources = ARRAY_SIZE(da8xx_rtc_resources),
680 .resource = da8xx_rtc_resources,
681};
682
683int da8xx_register_rtc(void)
684{
75c99bb0 685 int ret;
db6db5d8
CC		 686 void __iomem *base;
687
688 base = ioremap(DA8XX_RTC_BASE, SZ_4K);
689 if (WARN_ON(!base))
690 return -ENOMEM;
75c99bb0 691
c51df70b 692 /* Unlock the rtc's registers */
db6db5d8
CC		 693 __raw_writel(0x83e70b13, base + 0x6c);
694 __raw_writel(0x95a4f1e0, base + 0x70);
695
696 iounmap(base);
c51df70b 697
75c99bb0
SN		 698 ret = platform_device_register(&da8xx_rtc_device);
699 if (!ret)
700 /* Atleast on DA850, RTC is a wakeup source */
701 device_init_wakeup(&da8xx_rtc_device.dev, true);
702
703 return ret;
c51df70b 704}
1960e693 705
948c66df
SN		 706static void __iomem *da8xx_ddr2_ctlr_base;
707void __iomem * __init da8xx_get_mem_ctlr(void)
708{
709 if (da8xx_ddr2_ctlr_base)
710 return da8xx_ddr2_ctlr_base;
711
712 da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
713 if (!da8xx_ddr2_ctlr_base)
714 pr_warning("%s: Unable to map DDR2 controller", __func__);
715
716 return da8xx_ddr2_ctlr_base;
717}
718
1960e693
SN		 719static struct resource da8xx_cpuidle_resources[] = {
720 {
721 .start = DA8XX_DDR2_CTL_BASE,
722 .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
723 .flags = IORESOURCE_MEM,
724 },
725};
726
727/* DA8XX devices support DDR2 power down */
728static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
729 .ddr2_pdown = 1,
730};
731
732
733static struct platform_device da8xx_cpuidle_device = {
734 .name = "cpuidle-davinci",
735 .num_resources = ARRAY_SIZE(da8xx_cpuidle_resources),
736 .resource = da8xx_cpuidle_resources,
737 .dev = {
738 .platform_data = &da8xx_cpuidle_pdata,
739 },
740};
741
742int __init da8xx_register_cpuidle(void)
743{
948c66df
SN		 744 da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
745
1960e693
SN		 746 return platform_device_register(&da8xx_cpuidle_device);
747}
54ce6883
MW		 748
749static struct resource da8xx_spi0_resources[] = {
750 [0] = {
751 .start = DA8XX_SPI0_BASE,
752 .end = DA8XX_SPI0_BASE + SZ_4K - 1,
753 .flags = IORESOURCE_MEM,
754 },
755 [1] = {
756 .start = IRQ_DA8XX_SPINT0,
757 .end = IRQ_DA8XX_SPINT0,
758 .flags = IORESOURCE_IRQ,
759 },
760 [2] = {
761 .start = DA8XX_DMA_SPI0_RX,
762 .end = DA8XX_DMA_SPI0_RX,
763 .flags = IORESOURCE_DMA,
764 },
765 [3] = {
766 .start = DA8XX_DMA_SPI0_TX,
767 .end = DA8XX_DMA_SPI0_TX,
768 .flags = IORESOURCE_DMA,
769 },
770};
771
772static struct resource da8xx_spi1_resources[] = {
773 [0] = {
9e7d24f6
SS		 774 .start = DA830_SPI1_BASE,
775 .end = DA830_SPI1_BASE + SZ_4K - 1,
54ce6883
MW		 776 .flags = IORESOURCE_MEM,
777 },
778 [1] = {
779 .start = IRQ_DA8XX_SPINT1,
780 .end = IRQ_DA8XX_SPINT1,
781 .flags = IORESOURCE_IRQ,
782 },
783 [2] = {
784 .start = DA8XX_DMA_SPI1_RX,
785 .end = DA8XX_DMA_SPI1_RX,
786 .flags = IORESOURCE_DMA,
787 },
788 [3] = {
789 .start = DA8XX_DMA_SPI1_TX,
790 .end = DA8XX_DMA_SPI1_TX,
791 .flags = IORESOURCE_DMA,
792 },
793};
794
795struct davinci_spi_platform_data da8xx_spi_pdata[] = {
796 [0] = {
797 .version = SPI_VERSION_2,
798 .intr_line = 1,
799 .dma_event_q = EVENTQ_0,
800 },
801 [1] = {
802 .version = SPI_VERSION_2,
803 .intr_line = 1,
804 .dma_event_q = EVENTQ_0,
805 },
806};
807
808static struct platform_device da8xx_spi_device[] = {
809 [0] = {
810 .name = "spi_davinci",
811 .id = 0,
812 .num_resources = ARRAY_SIZE(da8xx_spi0_resources),
813 .resource = da8xx_spi0_resources,
814 .dev = {
815 .platform_data = &da8xx_spi_pdata[0],
816 },
817 },
818 [1] = {
819 .name = "spi_davinci",
820 .id = 1,
821 .num_resources = ARRAY_SIZE(da8xx_spi1_resources),
822 .resource = da8xx_spi1_resources,
823 .dev = {
824 .platform_data = &da8xx_spi_pdata[1],
825 },
826 },
827};
828
829int __init da8xx_register_spi(int instance, struct spi_board_info *info,
830 unsigned len)
831{
832 int ret;
833
834 if (instance < 0 || instance > 1)
835 return -EINVAL;
836
837 ret = spi_register_board_info(info, len);
838 if (ret)
839 pr_warning("%s: failed to register board info for spi %d :"
840 " %d\n", __func__, instance, ret);
841
842 da8xx_spi_pdata[instance].num_chipselect = len;
843
9e7d24f6
SS		 844 if (instance == 1 && cpu_is_davinci_da850()) {
845 da8xx_spi1_resources[0].start = DA850_SPI1_BASE;
846 da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1;
847 }
848
54ce6883
MW		 849 return platform_device_register(&da8xx_spi_device[instance]);
850}
cbb2c961
SN		 851
852#ifdef CONFIG_ARCH_DAVINCI_DA850
853
854static struct resource da850_sata_resources[] = {
855 {
856 .start = DA850_SATA_BASE,
857 .end = DA850_SATA_BASE + 0x1fff,
858 .flags = IORESOURCE_MEM,
859 },
860 {
861 .start = IRQ_DA850_SATAINT,
862 .flags = IORESOURCE_IRQ,
863 },
864};
865
866/* SATA PHY Control Register offset from AHCI base */
867#define SATA_P0PHYCR_REG 0x178
868
869#define SATA_PHY_MPY(x) ((x) << 0)
870#define SATA_PHY_LOS(x) ((x) << 6)
871#define SATA_PHY_RXCDR(x) ((x) << 10)
872#define SATA_PHY_RXEQ(x) ((x) << 13)
873#define SATA_PHY_TXSWING(x) ((x) << 19)
874#define SATA_PHY_ENPLL(x) ((x) << 31)
875
876static struct clk *da850_sata_clk;
877static unsigned long da850_sata_refclkpn;
878
879/* Supported DA850 SATA crystal frequencies */
880#define KHZ_TO_HZ(freq) ((freq) * 1000)
881static unsigned long da850_sata_xtal[] = {
882 KHZ_TO_HZ(300000),
883 KHZ_TO_HZ(250000),
884 0, /* Reserved */
885 KHZ_TO_HZ(187500),
886 KHZ_TO_HZ(150000),
887 KHZ_TO_HZ(125000),
888 KHZ_TO_HZ(120000),
889 KHZ_TO_HZ(100000),
890 KHZ_TO_HZ(75000),
891 KHZ_TO_HZ(60000),
892};
893
894static int da850_sata_init(struct device *dev, void __iomem *addr)
895{
896 int i, ret;
897 unsigned int val;
898
899 da850_sata_clk = clk_get(dev, NULL);
900 if (IS_ERR(da850_sata_clk))
901 return PTR_ERR(da850_sata_clk);
902
903 ret = clk_enable(da850_sata_clk);
904 if (ret)
905 goto err0;
906
907 /* Enable SATA clock receiver */
908 val = __raw_readl(DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG));
909 val &= ~BIT(0);
910 __raw_writel(val, DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG));
911
912 /* Get the multiplier needed for 1.5GHz PLL output */
913 for (i = 0; i < ARRAY_SIZE(da850_sata_xtal); i++)
914 if (da850_sata_xtal[i] == da850_sata_refclkpn)
915 break;
916
917 if (i == ARRAY_SIZE(da850_sata_xtal)) {
918 ret = -EINVAL;
919 goto err1;
920 }
921
922 val = SATA_PHY_MPY(i + 1) |
923 SATA_PHY_LOS(1) |
924 SATA_PHY_RXCDR(4) |
925 SATA_PHY_RXEQ(1) |
926 SATA_PHY_TXSWING(3) |
927 SATA_PHY_ENPLL(1);
928
929 __raw_writel(val, addr + SATA_P0PHYCR_REG);
930
931 return 0;
932
933err1:
934 clk_disable(da850_sata_clk);
935err0:
936 clk_put(da850_sata_clk);
937 return ret;
938}
939
940static void da850_sata_exit(struct device *dev)
941{
942 clk_disable(da850_sata_clk);
943 clk_put(da850_sata_clk);
944}
945
946static struct ahci_platform_data da850_sata_pdata = {
947 .init = da850_sata_init,
948 .exit = da850_sata_exit,
949};
950
951static u64 da850_sata_dmamask = DMA_BIT_MASK(32);
952
953static struct platform_device da850_sata_device = {
954 .name = "ahci",
955 .id = -1,
956 .dev = {
957 .platform_data = &da850_sata_pdata,
958 .dma_mask = &da850_sata_dmamask,
959 .coherent_dma_mask = DMA_BIT_MASK(32),
960 },
961 .num_resources = ARRAY_SIZE(da850_sata_resources),
962 .resource = da850_sata_resources,
963};
964
965int __init da850_register_sata(unsigned long refclkpn)
966{
967 da850_sata_refclkpn = refclkpn;
968 if (!da850_sata_refclkpn)
969 return -EINVAL;
970
971 return platform_device_register(&da850_sata_device);
972}
973#endif
Linux kernel - Deliverables
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