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Linux 3.11-rc2
[deliverable/linux.git] / arch / arm / mach-davinci / devices-da8xx.c
CommitLineData
55c79a40
MG		 1/*
2 * DA8XX/OMAP L1XX platform device data
3 *
4 * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
5 * Derived from code that was:
6 * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
55c79a40
MG		 13#include <linux/init.h>
14#include <linux/platform_device.h>
5c71d618 15#include <linux/dma-contiguous.h>
55c79a40 16#include <linux/serial_8250.h>
cbb2c961
SN		 17#include <linux/ahci_platform.h>
18#include <linux/clk.h>
7b6d864b 19#include <linux/reboot.h>
55c79a40
MG		 20
21#include <mach/cputype.h>
22#include <mach/common.h>
23#include <mach/time.h>
24#include <mach/da8xx.h>
1960e693 25#include <mach/cpuidle.h>
8e0d72d2 26#include <mach/sram.h>
55c79a40
MG		 27
28#include "clock.h"
896f66b7 29#include "asp.h"
55c79a40
MG		 30
31#define DA8XX_TPCC_BASE 0x01c00000
32#define DA8XX_TPTC0_BASE 0x01c08000
33#define DA8XX_TPTC1_BASE 0x01c08400
34#define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
35#define DA8XX_I2C0_BASE 0x01c22000
8ac764e3 36#define DA8XX_RTC_BASE 0x01c23000
8e0d72d2 37#define DA8XX_PRUSS_MEM_BASE 0x01c30000
8ac764e3
SS		 38#define DA8XX_MMCSD0_BASE 0x01c40000
39#define DA8XX_SPI0_BASE 0x01c41000
40#define DA830_SPI1_BASE 0x01e12000
41#define DA8XX_LCD_CNTRL_BASE 0x01e13000
cbb2c961 42#define DA850_SATA_BASE 0x01e18000
8ac764e3 43#define DA850_MMCSD1_BASE 0x01e1b000
55c79a40
MG		 44#define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000
45#define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000
46#define DA8XX_EMAC_CPGMAC_BASE 0x01e23000
47#define DA8XX_EMAC_MDIO_BASE 0x01e24000
55c79a40 48#define DA8XX_I2C1_BASE 0x01e28000
8ac764e3
SS		 49#define DA850_TPCC1_BASE 0x01e30000
50#define DA850_TPTC2_BASE 0x01e38000
9e7d24f6 51#define DA850_SPI1_BASE 0x01f0e000
8ac764e3 52#define DA8XX_DDR2_CTL_BASE 0xb0000000
55c79a40
MG		 53
54#define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000
55#define DA8XX_EMAC_MOD_REG_OFFSET 0x2000
56#define DA8XX_EMAC_RAM_OFFSET 0x0000
55c79a40
MG		 57#define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
58
54ce6883
MW		 59#define DA8XX_DMA_SPI0_RX EDMA_CTLR_CHAN(0, 14)
60#define DA8XX_DMA_SPI0_TX EDMA_CTLR_CHAN(0, 15)
e38c2b22
MW		 61#define DA8XX_DMA_MMCSD0_RX EDMA_CTLR_CHAN(0, 16)
62#define DA8XX_DMA_MMCSD0_TX EDMA_CTLR_CHAN(0, 17)
54ce6883
MW		 63#define DA8XX_DMA_SPI1_RX EDMA_CTLR_CHAN(0, 18)
64#define DA8XX_DMA_SPI1_TX EDMA_CTLR_CHAN(0, 19)
e38c2b22
MW		 65#define DA850_DMA_MMCSD1_RX EDMA_CTLR_CHAN(1, 28)
66#define DA850_DMA_MMCSD1_TX EDMA_CTLR_CHAN(1, 29)
67
d2de0582
SN		 68void __iomem *da8xx_syscfg0_base;
69void __iomem *da8xx_syscfg1_base;
6a28adef 70
55c79a40
MG		 71static struct plat_serial8250_port da8xx_serial_pdata[] = {
72 {
73 .mapbase = DA8XX_UART0_BASE,
74 .irq = IRQ_DA8XX_UARTINT0,
75 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
76 UPF_IOREMAP,
77 .iotype = UPIO_MEM,
78 .regshift = 2,
79 },
80 {
81 .mapbase = DA8XX_UART1_BASE,
82 .irq = IRQ_DA8XX_UARTINT1,
83 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
84 UPF_IOREMAP,
85 .iotype = UPIO_MEM,
86 .regshift = 2,
87 },
88 {
89 .mapbase = DA8XX_UART2_BASE,
90 .irq = IRQ_DA8XX_UARTINT2,
91 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
92 UPF_IOREMAP,
93 .iotype = UPIO_MEM,
94 .regshift = 2,
95 },
96 {
97 .flags = 0,
98 },
99};
100
101struct platform_device da8xx_serial_device = {
102 .name = "serial8250",
103 .id = PLAT8250_DEV_PLATFORM,
104 .dev = {
105 .platform_data = da8xx_serial_pdata,
106 },
107};
108
6cba4355 109static s8 da8xx_queue_tc_mapping[][2] = {
55c79a40
MG		 110 /* {event queue no, TC no} */
111 {0, 0},
112 {1, 1},
113 {-1, -1}
114};
115
6cba4355 116static s8 da8xx_queue_priority_mapping[][2] = {
55c79a40
MG		 117 /* {event queue no, Priority} */
118 {0, 3},
119 {1, 7},
120 {-1, -1}
121};
122
6cba4355 123static s8 da850_queue_tc_mapping[][2] = {
3f995f2f
SR		 124 /* {event queue no, TC no} */
125 {0, 0},
126 {-1, -1}
127};
128
6cba4355 129static s8 da850_queue_priority_mapping[][2] = {
3f995f2f
SR		 130 /* {event queue no, Priority} */
131 {0, 3},
132 {-1, -1}
133};
134
bc3ac9f3
SN		 135static struct edma_soc_info da830_edma_cc0_info = {
136 .n_channel = 32,
137 .n_region = 4,
138 .n_slot = 128,
139 .n_tc = 2,
140 .n_cc = 1,
141 .queue_tc_mapping = da8xx_queue_tc_mapping,
142 .queue_priority_mapping = da8xx_queue_priority_mapping,
f23fe857 143 .default_queue = EVENTQ_1,
bc3ac9f3
SN		 144};
145
146static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = {
147 &da830_edma_cc0_info,
55c79a40
MG		 148};
149
bc3ac9f3 150static struct edma_soc_info da850_edma_cc_info[] = {
3f995f2f
SR		 151 {
152 .n_channel = 32,
153 .n_region = 4,
154 .n_slot = 128,
155 .n_tc = 2,
156 .n_cc = 1,
157 .queue_tc_mapping = da8xx_queue_tc_mapping,
158 .queue_priority_mapping = da8xx_queue_priority_mapping,
f23fe857 159 .default_queue = EVENTQ_1,
3f995f2f
SR		 160 },
161 {
162 .n_channel = 32,
163 .n_region = 4,
164 .n_slot = 128,
165 .n_tc = 1,
166 .n_cc = 1,
167 .queue_tc_mapping = da850_queue_tc_mapping,
168 .queue_priority_mapping = da850_queue_priority_mapping,
f23fe857 169 .default_queue = EVENTQ_0,
3f995f2f
SR		 170 },
171};
172
bc3ac9f3
SN		 173static struct edma_soc_info *da850_edma_info[EDMA_MAX_CC] = {
174 &da850_edma_cc_info[0],
175 &da850_edma_cc_info[1],
176};
177
3f995f2f 178static struct resource da830_edma_resources[] = {
55c79a40
MG		 179 {
180 .name = "edma_cc0",
181 .start = DA8XX_TPCC_BASE,
182 .end = DA8XX_TPCC_BASE + SZ_32K - 1,
183 .flags = IORESOURCE_MEM,
184 },
185 {
186 .name = "edma_tc0",
187 .start = DA8XX_TPTC0_BASE,
188 .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
189 .flags = IORESOURCE_MEM,
190 },
191 {
192 .name = "edma_tc1",
193 .start = DA8XX_TPTC1_BASE,
194 .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
195 .flags = IORESOURCE_MEM,
196 },
197 {
198 .name = "edma0",
2259bbd4 199 .start = IRQ_DA8XX_CCINT0,
55c79a40
MG		 200 .flags = IORESOURCE_IRQ,
201 },
202 {
203 .name = "edma0_err",
204 .start = IRQ_DA8XX_CCERRINT,
205 .flags = IORESOURCE_IRQ,
206 },
207};
208
3f995f2f
SR		 209static struct resource da850_edma_resources[] = {
210 {
211 .name = "edma_cc0",
212 .start = DA8XX_TPCC_BASE,
213 .end = DA8XX_TPCC_BASE + SZ_32K - 1,
214 .flags = IORESOURCE_MEM,
215 },
216 {
217 .name = "edma_tc0",
218 .start = DA8XX_TPTC0_BASE,
219 .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
220 .flags = IORESOURCE_MEM,
221 },
222 {
223 .name = "edma_tc1",
224 .start = DA8XX_TPTC1_BASE,
225 .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
226 .flags = IORESOURCE_MEM,
227 },
228 {
229 .name = "edma_cc1",
230 .start = DA850_TPCC1_BASE,
231 .end = DA850_TPCC1_BASE + SZ_32K - 1,
232 .flags = IORESOURCE_MEM,
233 },
234 {
235 .name = "edma_tc2",
236 .start = DA850_TPTC2_BASE,
237 .end = DA850_TPTC2_BASE + SZ_1K - 1,
238 .flags = IORESOURCE_MEM,
239 },
240 {
241 .name = "edma0",
242 .start = IRQ_DA8XX_CCINT0,
243 .flags = IORESOURCE_IRQ,
244 },
245 {
246 .name = "edma0_err",
247 .start = IRQ_DA8XX_CCERRINT,
248 .flags = IORESOURCE_IRQ,
249 },
250 {
251 .name = "edma1",
252 .start = IRQ_DA850_CCINT1,
253 .flags = IORESOURCE_IRQ,
254 },
255 {
256 .name = "edma1_err",
257 .start = IRQ_DA850_CCERRINT1,
258 .flags = IORESOURCE_IRQ,
259 },
260};
261
262static struct platform_device da830_edma_device = {
55c79a40
MG		 263 .name = "edma",
264 .id = -1,
265 .dev = {
3f995f2f 266 .platform_data = da830_edma_info,
55c79a40 267 },
3f995f2f
SR		 268 .num_resources = ARRAY_SIZE(da830_edma_resources),
269 .resource = da830_edma_resources,
270};
271
272static struct platform_device da850_edma_device = {
273 .name = "edma",
274 .id = -1,
275 .dev = {
276 .platform_data = da850_edma_info,
277 },
278 .num_resources = ARRAY_SIZE(da850_edma_resources),
279 .resource = da850_edma_resources,
55c79a40
MG		 280};
281
a941c503 282int __init da830_register_edma(struct edma_rsv_info *rsv)
55c79a40 283{
a941c503 284 da830_edma_cc0_info.rsv = rsv;
3f995f2f 285
a941c503
RS		 286 return platform_device_register(&da830_edma_device);
287}
288
289int __init da850_register_edma(struct edma_rsv_info *rsv[2])
290{
291 if (rsv) {
292 da850_edma_cc_info[0].rsv = rsv[0];
293 da850_edma_cc_info[1].rsv = rsv[1];
294 }
3f995f2f 295
a941c503 296 return platform_device_register(&da850_edma_device);
55c79a40
MG		 297}
298
299static struct resource da8xx_i2c_resources0[] = {
300 {
301 .start = DA8XX_I2C0_BASE,
302 .end = DA8XX_I2C0_BASE + SZ_4K - 1,
303 .flags = IORESOURCE_MEM,
304 },
305 {
306 .start = IRQ_DA8XX_I2CINT0,
307 .end = IRQ_DA8XX_I2CINT0,
308 .flags = IORESOURCE_IRQ,
309 },
310};
311
312static struct platform_device da8xx_i2c_device0 = {
313 .name = "i2c_davinci",
314 .id = 1,
315 .num_resources = ARRAY_SIZE(da8xx_i2c_resources0),
316 .resource = da8xx_i2c_resources0,
317};
318
319static struct resource da8xx_i2c_resources1[] = {
320 {
321 .start = DA8XX_I2C1_BASE,
322 .end = DA8XX_I2C1_BASE + SZ_4K - 1,
323 .flags = IORESOURCE_MEM,
324 },
325 {
326 .start = IRQ_DA8XX_I2CINT1,
327 .end = IRQ_DA8XX_I2CINT1,
328 .flags = IORESOURCE_IRQ,
329 },
330};
331
332static struct platform_device da8xx_i2c_device1 = {
333 .name = "i2c_davinci",
334 .id = 2,
335 .num_resources = ARRAY_SIZE(da8xx_i2c_resources1),
336 .resource = da8xx_i2c_resources1,
337};
338
339int __init da8xx_register_i2c(int instance,
340 struct davinci_i2c_platform_data *pdata)
341{
342 struct platform_device *pdev;
343
344 if (instance == 0)
345 pdev = &da8xx_i2c_device0;
346 else if (instance == 1)
347 pdev = &da8xx_i2c_device1;
348 else
349 return -EINVAL;
350
351 pdev->dev.platform_data = pdata;
352 return platform_device_register(pdev);
353}
354
355static struct resource da8xx_watchdog_resources[] = {
356 {
357 .start = DA8XX_WDOG_BASE,
358 .end = DA8XX_WDOG_BASE + SZ_4K - 1,
359 .flags = IORESOURCE_MEM,
360 },
361};
362
19c7c0d8 363static struct platform_device da8xx_wdt_device = {
55c79a40
MG		 364 .name = "watchdog",
365 .id = -1,
366 .num_resources = ARRAY_SIZE(da8xx_watchdog_resources),
367 .resource = da8xx_watchdog_resources,
368};
369
7b6d864b 370void da8xx_restart(enum reboot_mode mode, const char *cmd)
c6121ddd 371{
19c7c0d8
KA		 372 struct device *dev;
373
374 dev = bus_find_device_by_name(&platform_bus_type, NULL, "watchdog");
375 if (!dev) {
376 pr_err("%s: failed to find watchdog device\n", __func__);
377 return;
378 }
379
380 davinci_watchdog_reset(to_platform_device(dev));
c6121ddd
SN		 381}
382
55c79a40
MG		 383int __init da8xx_register_watchdog(void)
384{
c78a5bc2 385 return platform_device_register(&da8xx_wdt_device);
55c79a40
MG		 386}
387
388static struct resource da8xx_emac_resources[] = {
389 {
390 .start = DA8XX_EMAC_CPPI_PORT_BASE,
d22960c8 391 .end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1,
55c79a40
MG		 392 .flags = IORESOURCE_MEM,
393 },
394 {
395 .start = IRQ_DA8XX_C0_RX_THRESH_PULSE,
396 .end = IRQ_DA8XX_C0_RX_THRESH_PULSE,
397 .flags = IORESOURCE_IRQ,
398 },
399 {
400 .start = IRQ_DA8XX_C0_RX_PULSE,
401 .end = IRQ_DA8XX_C0_RX_PULSE,
402 .flags = IORESOURCE_IRQ,
403 },
404 {
405 .start = IRQ_DA8XX_C0_TX_PULSE,
406 .end = IRQ_DA8XX_C0_TX_PULSE,
407 .flags = IORESOURCE_IRQ,
408 },
409 {
410 .start = IRQ_DA8XX_C0_MISC_PULSE,
411 .end = IRQ_DA8XX_C0_MISC_PULSE,
412 .flags = IORESOURCE_IRQ,
413 },
414};
415
416struct emac_platform_data da8xx_emac_pdata = {
417 .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET,
418 .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET,
419 .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET,
55c79a40
MG		 420 .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE,
421 .version = EMAC_VERSION_2,
422};
423
424static struct platform_device da8xx_emac_device = {
425 .name = "davinci_emac",
426 .id = 1,
427 .dev = {
428 .platform_data = &da8xx_emac_pdata,
429 },
430 .num_resources = ARRAY_SIZE(da8xx_emac_resources),
431 .resource = da8xx_emac_resources,
432};
433
d22960c8
CC		 434static struct resource da8xx_mdio_resources[] = {
435 {
436 .start = DA8XX_EMAC_MDIO_BASE,
437 .end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1,
438 .flags = IORESOURCE_MEM,
439 },
440};
441
442static struct platform_device da8xx_mdio_device = {
443 .name = "davinci_mdio",
444 .id = 0,
445 .num_resources = ARRAY_SIZE(da8xx_mdio_resources),
446 .resource = da8xx_mdio_resources,
447};
448
31f53cf3
MG		 449int __init da8xx_register_emac(void)
450{
d22960c8
CC		 451 int ret;
452
453 ret = platform_device_register(&da8xx_mdio_device);
454 if (ret < 0)
455 return ret;
456 ret = platform_device_register(&da8xx_emac_device);
457 if (ret < 0)
458 return ret;
459 ret = clk_add_alias(NULL, dev_name(&da8xx_mdio_device.dev),
460 NULL, &da8xx_emac_device.dev);
461 return ret;
31f53cf3
MG		 462}
463
e33ef5e3
C		 464static struct resource da830_mcasp1_resources[] = {
465 {
466 .name = "mcasp1",
467 .start = DAVINCI_DA830_MCASP1_REG_BASE,
468 .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
469 .flags = IORESOURCE_MEM,
470 },
471 /* TX event */
472 {
473 .start = DAVINCI_DA830_DMA_MCASP1_AXEVT,
474 .end = DAVINCI_DA830_DMA_MCASP1_AXEVT,
475 .flags = IORESOURCE_DMA,
476 },
477 /* RX event */
478 {
479 .start = DAVINCI_DA830_DMA_MCASP1_AREVT,
480 .end = DAVINCI_DA830_DMA_MCASP1_AREVT,
481 .flags = IORESOURCE_DMA,
482 },
483};
484
485static struct platform_device da830_mcasp1_device = {
486 .name = "davinci-mcasp",
487 .id = 1,
488 .num_resources = ARRAY_SIZE(da830_mcasp1_resources),
489 .resource = da830_mcasp1_resources,
490};
491
491214e1
C		 492static struct resource da850_mcasp_resources[] = {
493 {
494 .name = "mcasp",
495 .start = DAVINCI_DA8XX_MCASP0_REG_BASE,
496 .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
497 .flags = IORESOURCE_MEM,
498 },
499 /* TX event */
500 {
501 .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
502 .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
503 .flags = IORESOURCE_DMA,
504 },
505 /* RX event */
506 {
507 .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
508 .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
509 .flags = IORESOURCE_DMA,
510 },
511};
512
513static struct platform_device da850_mcasp_device = {
514 .name = "davinci-mcasp",
515 .id = 0,
516 .num_resources = ARRAY_SIZE(da850_mcasp_resources),
517 .resource = da850_mcasp_resources,
518};
519
b8864aa4 520void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
e33ef5e3 521{
491214e1
C		 522 /* DA830/OMAP-L137 has 3 instances of McASP */
523 if (cpu_is_davinci_da830() && id == 1) {
e33ef5e3
C		 524 da830_mcasp1_device.dev.platform_data = pdata;
525 platform_device_register(&da830_mcasp1_device);
491214e1
C		 526 } else if (cpu_is_davinci_da850()) {
527 da850_mcasp_device.dev.platform_data = pdata;
528 platform_device_register(&da850_mcasp_device);
e33ef5e3
C		 529 }
530}
5cbdf276 531
8e0d72d2
MP		 532static struct resource da8xx_pruss_resources[] = {
533 {
534 .start = DA8XX_PRUSS_MEM_BASE,
535 .end = DA8XX_PRUSS_MEM_BASE + 0xFFFF,
536 .flags = IORESOURCE_MEM,
537 },
538 {
539 .start = IRQ_DA8XX_EVTOUT0,
540 .end = IRQ_DA8XX_EVTOUT0,
541 .flags = IORESOURCE_IRQ,
542 },
543 {
544 .start = IRQ_DA8XX_EVTOUT1,
545 .end = IRQ_DA8XX_EVTOUT1,
546 .flags = IORESOURCE_IRQ,
547 },
548 {
549 .start = IRQ_DA8XX_EVTOUT2,
550 .end = IRQ_DA8XX_EVTOUT2,
551 .flags = IORESOURCE_IRQ,
552 },
553 {
554 .start = IRQ_DA8XX_EVTOUT3,
555 .end = IRQ_DA8XX_EVTOUT3,
556 .flags = IORESOURCE_IRQ,
557 },
558 {
559 .start = IRQ_DA8XX_EVTOUT4,
560 .end = IRQ_DA8XX_EVTOUT4,
561 .flags = IORESOURCE_IRQ,
562 },
563 {
564 .start = IRQ_DA8XX_EVTOUT5,
565 .end = IRQ_DA8XX_EVTOUT5,
566 .flags = IORESOURCE_IRQ,
567 },
568 {
569 .start = IRQ_DA8XX_EVTOUT6,
570 .end = IRQ_DA8XX_EVTOUT6,
571 .flags = IORESOURCE_IRQ,
572 },
573 {
574 .start = IRQ_DA8XX_EVTOUT7,
575 .end = IRQ_DA8XX_EVTOUT7,
576 .flags = IORESOURCE_IRQ,
577 },
578};
579
580static struct uio_pruss_pdata da8xx_uio_pruss_pdata = {
581 .pintc_base = 0x4000,
582};
583
584static struct platform_device da8xx_uio_pruss_dev = {
585 .name = "pruss_uio",
586 .id = -1,
587 .num_resources = ARRAY_SIZE(da8xx_pruss_resources),
588 .resource = da8xx_pruss_resources,
589 .dev = {
590 .coherent_dma_mask = DMA_BIT_MASK(32),
591 .platform_data = &da8xx_uio_pruss_pdata,
592 }
593};
594
595int __init da8xx_register_uio_pruss(void)
596{
597 da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool();
598 return platform_device_register(&da8xx_uio_pruss_dev);
599}
600
5cbdf276 601static struct lcd_ctrl_config lcd_cfg = {
3b43ad20 602 .panel_shade = COLOR_ACTIVE,
5cbdf276 603 .bpp = 16,
5cbdf276
SR		 604};
605
b9e6342b
MG		 606struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
607 .manu_name = "sharp",
608 .controller_data = &lcd_cfg,
609 .type = "Sharp_LCD035Q3DG01",
610};
611
612struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
613 .manu_name = "sharp",
614 .controller_data = &lcd_cfg,
615 .type = "Sharp_LK043T1DG01",
5cbdf276
SR		 616};
617
618static struct resource da8xx_lcdc_resources[] = {
619 [0] = { /* registers */
620 .start = DA8XX_LCD_CNTRL_BASE,
621 .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
622 .flags = IORESOURCE_MEM,
623 },
624 [1] = { /* interrupt */
625 .start = IRQ_DA8XX_LCDINT,
626 .end = IRQ_DA8XX_LCDINT,
627 .flags = IORESOURCE_IRQ,
628 },
629};
630
b9e6342b 631static struct platform_device da8xx_lcdc_device = {
5cbdf276
SR		 632 .name = "da8xx_lcdc",
633 .id = 0,
634 .num_resources = ARRAY_SIZE(da8xx_lcdc_resources),
635 .resource = da8xx_lcdc_resources,
5cbdf276
SR		 636};
637
b9e6342b 638int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
5cbdf276 639{
b9e6342b
MG		 640 da8xx_lcdc_device.dev.platform_data = pdata;
641 return platform_device_register(&da8xx_lcdc_device);
5cbdf276 642}
700691f2
SR		 643
644static struct resource da8xx_mmcsd0_resources[] = {
645 { /* registers */
646 .start = DA8XX_MMCSD0_BASE,
647 .end = DA8XX_MMCSD0_BASE + SZ_4K - 1,
648 .flags = IORESOURCE_MEM,
649 },
650 { /* interrupt */
651 .start = IRQ_DA8XX_MMCSDINT0,
652 .end = IRQ_DA8XX_MMCSDINT0,
653 .flags = IORESOURCE_IRQ,
654 },
655 { /* DMA RX */
e38c2b22
MW		 656 .start = DA8XX_DMA_MMCSD0_RX,
657 .end = DA8XX_DMA_MMCSD0_RX,
700691f2
SR		 658 .flags = IORESOURCE_DMA,
659 },
660 { /* DMA TX */
e38c2b22
MW		 661 .start = DA8XX_DMA_MMCSD0_TX,
662 .end = DA8XX_DMA_MMCSD0_TX,
700691f2
SR		 663 .flags = IORESOURCE_DMA,
664 },
665};
666
667static struct platform_device da8xx_mmcsd0_device = {
d7ca4c75 668 .name = "da830-mmc",
700691f2
SR		 669 .id = 0,
670 .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources),
671 .resource = da8xx_mmcsd0_resources,
672};
673
674int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
675{
676 da8xx_mmcsd0_device.dev.platform_data = config;
677 return platform_device_register(&da8xx_mmcsd0_device);
678}
c51df70b 679
b8241aef
JK		 680#ifdef CONFIG_ARCH_DAVINCI_DA850
681static struct resource da850_mmcsd1_resources[] = {
682 { /* registers */
683 .start = DA850_MMCSD1_BASE,
684 .end = DA850_MMCSD1_BASE + SZ_4K - 1,
685 .flags = IORESOURCE_MEM,
686 },
687 { /* interrupt */
688 .start = IRQ_DA850_MMCSDINT0_1,
689 .end = IRQ_DA850_MMCSDINT0_1,
690 .flags = IORESOURCE_IRQ,
691 },
692 { /* DMA RX */
e38c2b22
MW		 693 .start = DA850_DMA_MMCSD1_RX,
694 .end = DA850_DMA_MMCSD1_RX,
b8241aef
JK		 695 .flags = IORESOURCE_DMA,
696 },
697 { /* DMA TX */
e38c2b22
MW		 698 .start = DA850_DMA_MMCSD1_TX,
699 .end = DA850_DMA_MMCSD1_TX,
b8241aef
JK		 700 .flags = IORESOURCE_DMA,
701 },
702};
703
704static struct platform_device da850_mmcsd1_device = {
d7ca4c75 705 .name = "da830-mmc",
b8241aef
JK		 706 .id = 1,
707 .num_resources = ARRAY_SIZE(da850_mmcsd1_resources),
708 .resource = da850_mmcsd1_resources,
709};
710
711int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
712{
713 da850_mmcsd1_device.dev.platform_data = config;
714 return platform_device_register(&da850_mmcsd1_device);
715}
716#endif
717
5c71d618
RT		 718static struct resource da8xx_rproc_resources[] = {
719 { /* DSP boot address */
720 .start = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG,
721 .end = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3,
722 .flags = IORESOURCE_MEM,
723 },
724 { /* DSP interrupt registers */
725 .start = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG,
726 .end = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7,
727 .flags = IORESOURCE_MEM,
728 },
729 { /* dsp irq */
730 .start = IRQ_DA8XX_CHIPINT0,
731 .end = IRQ_DA8XX_CHIPINT0,
732 .flags = IORESOURCE_IRQ,
733 },
734};
735
736static struct platform_device da8xx_dsp = {
737 .name = "davinci-rproc",
738 .dev = {
739 .coherent_dma_mask = DMA_BIT_MASK(32),
740 },
741 .num_resources = ARRAY_SIZE(da8xx_rproc_resources),
742 .resource = da8xx_rproc_resources,
743};
744
745#if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC)
746
747static phys_addr_t rproc_base __initdata;
748static unsigned long rproc_size __initdata;
749
750static int __init early_rproc_mem(char *p)
751{
752 char *endp;
753
754 if (p == NULL)
755 return 0;
756
757 rproc_size = memparse(p, &endp);
758 if (*endp == '@')
759 rproc_base = memparse(endp + 1, NULL);
760
761 return 0;
762}
763early_param("rproc_mem", early_rproc_mem);
764
765void __init da8xx_rproc_reserve_cma(void)
766{
767 int ret;
768
769 if (!rproc_base || !rproc_size) {
770 pr_err("%s: 'rproc_mem=nn@address' badly specified\n"
771 " 'nn' and 'address' must both be non-zero\n",
772 __func__);
773
774 return;
775 }
776
777 pr_info("%s: reserving 0x%lx @ 0x%lx...\n",
778 __func__, rproc_size, (unsigned long)rproc_base);
779
780 ret = dma_declare_contiguous(&da8xx_dsp.dev, rproc_size, rproc_base, 0);
781 if (ret)
782 pr_err("%s: dma_declare_contiguous failed %d\n", __func__, ret);
783}
784
785#else
786
787void __init da8xx_rproc_reserve_cma(void)
788{
789}
790
791#endif
792
793int __init da8xx_register_rproc(void)
794{
795 int ret;
796
797 ret = platform_device_register(&da8xx_dsp);
798 if (ret)
799 pr_err("%s: can't register DSP device: %d\n", __func__, ret);
800
801 return ret;
802};
803
c51df70b
MG		 804static struct resource da8xx_rtc_resources[] = {
805 {
806 .start = DA8XX_RTC_BASE,
807 .end = DA8XX_RTC_BASE + SZ_4K - 1,
808 .flags = IORESOURCE_MEM,
809 },
810 { /* timer irq */
811 .start = IRQ_DA8XX_RTC,
812 .end = IRQ_DA8XX_RTC,
813 .flags = IORESOURCE_IRQ,
814 },
815 { /* alarm irq */
816 .start = IRQ_DA8XX_RTC,
817 .end = IRQ_DA8XX_RTC,
818 .flags = IORESOURCE_IRQ,
819 },
820};
821
822static struct platform_device da8xx_rtc_device = {
852168c9 823 .name = "da830-rtc",
c51df70b
MG		 824 .id = -1,
825 .num_resources = ARRAY_SIZE(da8xx_rtc_resources),
826 .resource = da8xx_rtc_resources,
827};
828
829int da8xx_register_rtc(void)
830{
75c99bb0 831 int ret;
c51df70b 832
75c99bb0
SN		 833 ret = platform_device_register(&da8xx_rtc_device);
834 if (!ret)
835 /* Atleast on DA850, RTC is a wakeup source */
836 device_init_wakeup(&da8xx_rtc_device.dev, true);
837
838 return ret;
c51df70b 839}
1960e693 840
948c66df
SN		 841static void __iomem *da8xx_ddr2_ctlr_base;
842void __iomem * __init da8xx_get_mem_ctlr(void)
843{
844 if (da8xx_ddr2_ctlr_base)
845 return da8xx_ddr2_ctlr_base;
846
847 da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
848 if (!da8xx_ddr2_ctlr_base)
d2e0c18a 849 pr_warn("%s: Unable to map DDR2 controller", __func__);
948c66df
SN		 850
851 return da8xx_ddr2_ctlr_base;
852}
853
1960e693
SN		 854static struct resource da8xx_cpuidle_resources[] = {
855 {
856 .start = DA8XX_DDR2_CTL_BASE,
857 .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
858 .flags = IORESOURCE_MEM,
859 },
860};
861
862/* DA8XX devices support DDR2 power down */
863static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
864 .ddr2_pdown = 1,
865};
866
867
868static struct platform_device da8xx_cpuidle_device = {
869 .name = "cpuidle-davinci",
870 .num_resources = ARRAY_SIZE(da8xx_cpuidle_resources),
871 .resource = da8xx_cpuidle_resources,
872 .dev = {
873 .platform_data = &da8xx_cpuidle_pdata,
874 },
875};
876
877int __init da8xx_register_cpuidle(void)
878{
948c66df
SN		 879 da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
880
1960e693
SN		 881 return platform_device_register(&da8xx_cpuidle_device);
882}
54ce6883
MW		 883
884static struct resource da8xx_spi0_resources[] = {
885 [0] = {
886 .start = DA8XX_SPI0_BASE,
887 .end = DA8XX_SPI0_BASE + SZ_4K - 1,
888 .flags = IORESOURCE_MEM,
889 },
890 [1] = {
891 .start = IRQ_DA8XX_SPINT0,
892 .end = IRQ_DA8XX_SPINT0,
893 .flags = IORESOURCE_IRQ,
894 },
895 [2] = {
896 .start = DA8XX_DMA_SPI0_RX,
897 .end = DA8XX_DMA_SPI0_RX,
898 .flags = IORESOURCE_DMA,
899 },
900 [3] = {
901 .start = DA8XX_DMA_SPI0_TX,
902 .end = DA8XX_DMA_SPI0_TX,
903 .flags = IORESOURCE_DMA,
904 },
905};
906
907static struct resource da8xx_spi1_resources[] = {
908 [0] = {
9e7d24f6
SS		 909 .start = DA830_SPI1_BASE,
910 .end = DA830_SPI1_BASE + SZ_4K - 1,
54ce6883
MW		 911 .flags = IORESOURCE_MEM,
912 },
913 [1] = {
914 .start = IRQ_DA8XX_SPINT1,
915 .end = IRQ_DA8XX_SPINT1,
916 .flags = IORESOURCE_IRQ,
917 },
918 [2] = {
919 .start = DA8XX_DMA_SPI1_RX,
920 .end = DA8XX_DMA_SPI1_RX,
921 .flags = IORESOURCE_DMA,
922 },
923 [3] = {
924 .start = DA8XX_DMA_SPI1_TX,
925 .end = DA8XX_DMA_SPI1_TX,
926 .flags = IORESOURCE_DMA,
927 },
928};
929
0273612c 930static struct davinci_spi_platform_data da8xx_spi_pdata[] = {
54ce6883
MW		 931 [0] = {
932 .version = SPI_VERSION_2,
933 .intr_line = 1,
934 .dma_event_q = EVENTQ_0,
935 },
936 [1] = {
937 .version = SPI_VERSION_2,
938 .intr_line = 1,
939 .dma_event_q = EVENTQ_0,
940 },
941};
942
943static struct platform_device da8xx_spi_device[] = {
944 [0] = {
945 .name = "spi_davinci",
946 .id = 0,
947 .num_resources = ARRAY_SIZE(da8xx_spi0_resources),
948 .resource = da8xx_spi0_resources,
949 .dev = {
950 .platform_data = &da8xx_spi_pdata[0],
951 },
952 },
953 [1] = {
954 .name = "spi_davinci",
955 .id = 1,
956 .num_resources = ARRAY_SIZE(da8xx_spi1_resources),
957 .resource = da8xx_spi1_resources,
958 .dev = {
959 .platform_data = &da8xx_spi_pdata[1],
960 },
961 },
962};
963
0273612c 964int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect)
54ce6883 965{
54ce6883
MW		 966 if (instance < 0 || instance > 1)
967 return -EINVAL;
968
0273612c 969 da8xx_spi_pdata[instance].num_chipselect = num_chipselect;
54ce6883 970
9e7d24f6
SS		 971 if (instance == 1 && cpu_is_davinci_da850()) {
972 da8xx_spi1_resources[0].start = DA850_SPI1_BASE;
973 da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1;
974 }
975
54ce6883
MW		 976 return platform_device_register(&da8xx_spi_device[instance]);
977}
cbb2c961
SN		 978
979#ifdef CONFIG_ARCH_DAVINCI_DA850
980
981static struct resource da850_sata_resources[] = {
982 {
983 .start = DA850_SATA_BASE,
984 .end = DA850_SATA_BASE + 0x1fff,
985 .flags = IORESOURCE_MEM,
986 },
987 {
988 .start = IRQ_DA850_SATAINT,
989 .flags = IORESOURCE_IRQ,
990 },
991};
992
993/* SATA PHY Control Register offset from AHCI base */
994#define SATA_P0PHYCR_REG 0x178
995
996#define SATA_PHY_MPY(x) ((x) << 0)
997#define SATA_PHY_LOS(x) ((x) << 6)
998#define SATA_PHY_RXCDR(x) ((x) << 10)
999#define SATA_PHY_RXEQ(x) ((x) << 13)
1000#define SATA_PHY_TXSWING(x) ((x) << 19)
1001#define SATA_PHY_ENPLL(x) ((x) << 31)
1002
1003static struct clk *da850_sata_clk;
1004static unsigned long da850_sata_refclkpn;
1005
1006/* Supported DA850 SATA crystal frequencies */
1007#define KHZ_TO_HZ(freq) ((freq) * 1000)
1008static unsigned long da850_sata_xtal[] = {
1009 KHZ_TO_HZ(300000),
1010 KHZ_TO_HZ(250000),
1011 0, /* Reserved */
1012 KHZ_TO_HZ(187500),
1013 KHZ_TO_HZ(150000),
1014 KHZ_TO_HZ(125000),
1015 KHZ_TO_HZ(120000),
1016 KHZ_TO_HZ(100000),
1017 KHZ_TO_HZ(75000),
1018 KHZ_TO_HZ(60000),
1019};
1020
1021static int da850_sata_init(struct device *dev, void __iomem *addr)
1022{
1023 int i, ret;
1024 unsigned int val;
1025
1026 da850_sata_clk = clk_get(dev, NULL);
1027 if (IS_ERR(da850_sata_clk))
1028 return PTR_ERR(da850_sata_clk);
1029
b6f1ffed 1030 ret = clk_prepare_enable(da850_sata_clk);
cbb2c961
SN		 1031 if (ret)
1032 goto err0;
1033
1034 /* Enable SATA clock receiver */
1035 val = __raw_readl(DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG));
1036 val &= ~BIT(0);
1037 __raw_writel(val, DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG));
1038
1039 /* Get the multiplier needed for 1.5GHz PLL output */
1040 for (i = 0; i < ARRAY_SIZE(da850_sata_xtal); i++)
1041 if (da850_sata_xtal[i] == da850_sata_refclkpn)
1042 break;
1043
1044 if (i == ARRAY_SIZE(da850_sata_xtal)) {
1045 ret = -EINVAL;
1046 goto err1;
1047 }
1048
1049 val = SATA_PHY_MPY(i + 1) |
1050 SATA_PHY_LOS(1) |
1051 SATA_PHY_RXCDR(4) |
1052 SATA_PHY_RXEQ(1) |
1053 SATA_PHY_TXSWING(3) |
1054 SATA_PHY_ENPLL(1);
1055
1056 __raw_writel(val, addr + SATA_P0PHYCR_REG);
1057
1058 return 0;
1059
1060err1:
b6f1ffed 1061 clk_disable_unprepare(da850_sata_clk);
cbb2c961
SN		 1062err0:
1063 clk_put(da850_sata_clk);
1064 return ret;
1065}
1066
1067static void da850_sata_exit(struct device *dev)
1068{
b6f1ffed 1069 clk_disable_unprepare(da850_sata_clk);
cbb2c961
SN		 1070 clk_put(da850_sata_clk);
1071}
1072
1073static struct ahci_platform_data da850_sata_pdata = {
1074 .init = da850_sata_init,
1075 .exit = da850_sata_exit,
1076};
1077
1078static u64 da850_sata_dmamask = DMA_BIT_MASK(32);
1079
1080static struct platform_device da850_sata_device = {
1081 .name = "ahci",
1082 .id = -1,
1083 .dev = {
1084 .platform_data = &da850_sata_pdata,
1085 .dma_mask = &da850_sata_dmamask,
1086 .coherent_dma_mask = DMA_BIT_MASK(32),
1087 },
1088 .num_resources = ARRAY_SIZE(da850_sata_resources),
1089 .resource = da850_sata_resources,
1090};
1091
1092int __init da850_register_sata(unsigned long refclkpn)
1093{
1094 da850_sata_refclkpn = refclkpn;
1095 if (!da850_sata_refclkpn)
1096 return -EINVAL;
1097
1098 return platform_device_register(&da850_sata_device);
1099}
1100#endif
Linux kernel - Deliverables
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