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ARM: davinci: remove rtc kicker release
[deliverable/linux.git] / arch / arm / mach-davinci / devices-da8xx.c
CommitLineData
55c79a40
MG		 1/*
2 * DA8XX/OMAP L1XX platform device data
3 *
4 * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
5 * Derived from code that was:
6 * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
55c79a40
MG		 13#include <linux/init.h>
14#include <linux/platform_device.h>
15#include <linux/dma-mapping.h>
16#include <linux/serial_8250.h>
cbb2c961
SN		 17#include <linux/ahci_platform.h>
18#include <linux/clk.h>
55c79a40
MG		 19
20#include <mach/cputype.h>
21#include <mach/common.h>
22#include <mach/time.h>
23#include <mach/da8xx.h>
1960e693 24#include <mach/cpuidle.h>
8e0d72d2 25#include <mach/sram.h>
55c79a40
MG		 26
27#include "clock.h"
896f66b7 28#include "asp.h"
55c79a40
MG		 29
30#define DA8XX_TPCC_BASE 0x01c00000
31#define DA8XX_TPTC0_BASE 0x01c08000
32#define DA8XX_TPTC1_BASE 0x01c08400
33#define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
34#define DA8XX_I2C0_BASE 0x01c22000
8ac764e3 35#define DA8XX_RTC_BASE 0x01c23000
8e0d72d2 36#define DA8XX_PRUSS_MEM_BASE 0x01c30000
8ac764e3
SS		 37#define DA8XX_MMCSD0_BASE 0x01c40000
38#define DA8XX_SPI0_BASE 0x01c41000
39#define DA830_SPI1_BASE 0x01e12000
40#define DA8XX_LCD_CNTRL_BASE 0x01e13000
cbb2c961 41#define DA850_SATA_BASE 0x01e18000
8ac764e3 42#define DA850_MMCSD1_BASE 0x01e1b000
55c79a40
MG		 43#define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000
44#define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000
45#define DA8XX_EMAC_CPGMAC_BASE 0x01e23000
46#define DA8XX_EMAC_MDIO_BASE 0x01e24000
55c79a40 47#define DA8XX_I2C1_BASE 0x01e28000
8ac764e3
SS		 48#define DA850_TPCC1_BASE 0x01e30000
49#define DA850_TPTC2_BASE 0x01e38000
9e7d24f6 50#define DA850_SPI1_BASE 0x01f0e000
8ac764e3 51#define DA8XX_DDR2_CTL_BASE 0xb0000000
55c79a40
MG		 52
53#define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000
54#define DA8XX_EMAC_MOD_REG_OFFSET 0x2000
55#define DA8XX_EMAC_RAM_OFFSET 0x0000
55c79a40
MG		 56#define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
57
54ce6883
MW		 58#define DA8XX_DMA_SPI0_RX EDMA_CTLR_CHAN(0, 14)
59#define DA8XX_DMA_SPI0_TX EDMA_CTLR_CHAN(0, 15)
e38c2b22
MW		 60#define DA8XX_DMA_MMCSD0_RX EDMA_CTLR_CHAN(0, 16)
61#define DA8XX_DMA_MMCSD0_TX EDMA_CTLR_CHAN(0, 17)
54ce6883
MW		 62#define DA8XX_DMA_SPI1_RX EDMA_CTLR_CHAN(0, 18)
63#define DA8XX_DMA_SPI1_TX EDMA_CTLR_CHAN(0, 19)
e38c2b22
MW		 64#define DA850_DMA_MMCSD1_RX EDMA_CTLR_CHAN(1, 28)
65#define DA850_DMA_MMCSD1_TX EDMA_CTLR_CHAN(1, 29)
66
d2de0582
SN		 67void __iomem *da8xx_syscfg0_base;
68void __iomem *da8xx_syscfg1_base;
6a28adef 69
55c79a40
MG		 70static struct plat_serial8250_port da8xx_serial_pdata[] = {
71 {
72 .mapbase = DA8XX_UART0_BASE,
73 .irq = IRQ_DA8XX_UARTINT0,
74 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
75 UPF_IOREMAP,
76 .iotype = UPIO_MEM,
77 .regshift = 2,
78 },
79 {
80 .mapbase = DA8XX_UART1_BASE,
81 .irq = IRQ_DA8XX_UARTINT1,
82 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
83 UPF_IOREMAP,
84 .iotype = UPIO_MEM,
85 .regshift = 2,
86 },
87 {
88 .mapbase = DA8XX_UART2_BASE,
89 .irq = IRQ_DA8XX_UARTINT2,
90 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
91 UPF_IOREMAP,
92 .iotype = UPIO_MEM,
93 .regshift = 2,
94 },
95 {
96 .flags = 0,
97 },
98};
99
100struct platform_device da8xx_serial_device = {
101 .name = "serial8250",
102 .id = PLAT8250_DEV_PLATFORM,
103 .dev = {
104 .platform_data = da8xx_serial_pdata,
105 },
106};
107
55c79a40
MG		 108static const s8 da8xx_queue_tc_mapping[][2] = {
109 /* {event queue no, TC no} */
110 {0, 0},
111 {1, 1},
112 {-1, -1}
113};
114
115static const s8 da8xx_queue_priority_mapping[][2] = {
116 /* {event queue no, Priority} */
117 {0, 3},
118 {1, 7},
119 {-1, -1}
120};
121
3f995f2f
SR		 122static const s8 da850_queue_tc_mapping[][2] = {
123 /* {event queue no, TC no} */
124 {0, 0},
125 {-1, -1}
126};
127
128static const s8 da850_queue_priority_mapping[][2] = {
129 /* {event queue no, Priority} */
130 {0, 3},
131 {-1, -1}
132};
133
bc3ac9f3
SN		 134static struct edma_soc_info da830_edma_cc0_info = {
135 .n_channel = 32,
136 .n_region = 4,
137 .n_slot = 128,
138 .n_tc = 2,
139 .n_cc = 1,
140 .queue_tc_mapping = da8xx_queue_tc_mapping,
141 .queue_priority_mapping = da8xx_queue_priority_mapping,
f23fe857 142 .default_queue = EVENTQ_1,
bc3ac9f3
SN		 143};
144
145static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = {
146 &da830_edma_cc0_info,
55c79a40
MG		 147};
148
bc3ac9f3 149static struct edma_soc_info da850_edma_cc_info[] = {
3f995f2f
SR		 150 {
151 .n_channel = 32,
152 .n_region = 4,
153 .n_slot = 128,
154 .n_tc = 2,
155 .n_cc = 1,
156 .queue_tc_mapping = da8xx_queue_tc_mapping,
157 .queue_priority_mapping = da8xx_queue_priority_mapping,
f23fe857 158 .default_queue = EVENTQ_1,
3f995f2f
SR		 159 },
160 {
161 .n_channel = 32,
162 .n_region = 4,
163 .n_slot = 128,
164 .n_tc = 1,
165 .n_cc = 1,
166 .queue_tc_mapping = da850_queue_tc_mapping,
167 .queue_priority_mapping = da850_queue_priority_mapping,
f23fe857 168 .default_queue = EVENTQ_0,
3f995f2f
SR		 169 },
170};
171
bc3ac9f3
SN		 172static struct edma_soc_info *da850_edma_info[EDMA_MAX_CC] = {
173 &da850_edma_cc_info[0],
174 &da850_edma_cc_info[1],
175};
176
3f995f2f 177static struct resource da830_edma_resources[] = {
55c79a40
MG		 178 {
179 .name = "edma_cc0",
180 .start = DA8XX_TPCC_BASE,
181 .end = DA8XX_TPCC_BASE + SZ_32K - 1,
182 .flags = IORESOURCE_MEM,
183 },
184 {
185 .name = "edma_tc0",
186 .start = DA8XX_TPTC0_BASE,
187 .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
188 .flags = IORESOURCE_MEM,
189 },
190 {
191 .name = "edma_tc1",
192 .start = DA8XX_TPTC1_BASE,
193 .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
194 .flags = IORESOURCE_MEM,
195 },
196 {
197 .name = "edma0",
2259bbd4 198 .start = IRQ_DA8XX_CCINT0,
55c79a40
MG		 199 .flags = IORESOURCE_IRQ,
200 },
201 {
202 .name = "edma0_err",
203 .start = IRQ_DA8XX_CCERRINT,
204 .flags = IORESOURCE_IRQ,
205 },
206};
207
3f995f2f
SR		 208static struct resource da850_edma_resources[] = {
209 {
210 .name = "edma_cc0",
211 .start = DA8XX_TPCC_BASE,
212 .end = DA8XX_TPCC_BASE + SZ_32K - 1,
213 .flags = IORESOURCE_MEM,
214 },
215 {
216 .name = "edma_tc0",
217 .start = DA8XX_TPTC0_BASE,
218 .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
219 .flags = IORESOURCE_MEM,
220 },
221 {
222 .name = "edma_tc1",
223 .start = DA8XX_TPTC1_BASE,
224 .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
225 .flags = IORESOURCE_MEM,
226 },
227 {
228 .name = "edma_cc1",
229 .start = DA850_TPCC1_BASE,
230 .end = DA850_TPCC1_BASE + SZ_32K - 1,
231 .flags = IORESOURCE_MEM,
232 },
233 {
234 .name = "edma_tc2",
235 .start = DA850_TPTC2_BASE,
236 .end = DA850_TPTC2_BASE + SZ_1K - 1,
237 .flags = IORESOURCE_MEM,
238 },
239 {
240 .name = "edma0",
241 .start = IRQ_DA8XX_CCINT0,
242 .flags = IORESOURCE_IRQ,
243 },
244 {
245 .name = "edma0_err",
246 .start = IRQ_DA8XX_CCERRINT,
247 .flags = IORESOURCE_IRQ,
248 },
249 {
250 .name = "edma1",
251 .start = IRQ_DA850_CCINT1,
252 .flags = IORESOURCE_IRQ,
253 },
254 {
255 .name = "edma1_err",
256 .start = IRQ_DA850_CCERRINT1,
257 .flags = IORESOURCE_IRQ,
258 },
259};
260
261static struct platform_device da830_edma_device = {
55c79a40
MG		 262 .name = "edma",
263 .id = -1,
264 .dev = {
3f995f2f 265 .platform_data = da830_edma_info,
55c79a40 266 },
3f995f2f
SR		 267 .num_resources = ARRAY_SIZE(da830_edma_resources),
268 .resource = da830_edma_resources,
269};
270
271static struct platform_device da850_edma_device = {
272 .name = "edma",
273 .id = -1,
274 .dev = {
275 .platform_data = da850_edma_info,
276 },
277 .num_resources = ARRAY_SIZE(da850_edma_resources),
278 .resource = da850_edma_resources,
55c79a40
MG		 279};
280
a941c503 281int __init da830_register_edma(struct edma_rsv_info *rsv)
55c79a40 282{
a941c503 283 da830_edma_cc0_info.rsv = rsv;
3f995f2f 284
a941c503
RS		 285 return platform_device_register(&da830_edma_device);
286}
287
288int __init da850_register_edma(struct edma_rsv_info *rsv[2])
289{
290 if (rsv) {
291 da850_edma_cc_info[0].rsv = rsv[0];
292 da850_edma_cc_info[1].rsv = rsv[1];
293 }
3f995f2f 294
a941c503 295 return platform_device_register(&da850_edma_device);
55c79a40
MG		 296}
297
298static struct resource da8xx_i2c_resources0[] = {
299 {
300 .start = DA8XX_I2C0_BASE,
301 .end = DA8XX_I2C0_BASE + SZ_4K - 1,
302 .flags = IORESOURCE_MEM,
303 },
304 {
305 .start = IRQ_DA8XX_I2CINT0,
306 .end = IRQ_DA8XX_I2CINT0,
307 .flags = IORESOURCE_IRQ,
308 },
309};
310
311static struct platform_device da8xx_i2c_device0 = {
312 .name = "i2c_davinci",
313 .id = 1,
314 .num_resources = ARRAY_SIZE(da8xx_i2c_resources0),
315 .resource = da8xx_i2c_resources0,
316};
317
318static struct resource da8xx_i2c_resources1[] = {
319 {
320 .start = DA8XX_I2C1_BASE,
321 .end = DA8XX_I2C1_BASE + SZ_4K - 1,
322 .flags = IORESOURCE_MEM,
323 },
324 {
325 .start = IRQ_DA8XX_I2CINT1,
326 .end = IRQ_DA8XX_I2CINT1,
327 .flags = IORESOURCE_IRQ,
328 },
329};
330
331static struct platform_device da8xx_i2c_device1 = {
332 .name = "i2c_davinci",
333 .id = 2,
334 .num_resources = ARRAY_SIZE(da8xx_i2c_resources1),
335 .resource = da8xx_i2c_resources1,
336};
337
338int __init da8xx_register_i2c(int instance,
339 struct davinci_i2c_platform_data *pdata)
340{
341 struct platform_device *pdev;
342
343 if (instance == 0)
344 pdev = &da8xx_i2c_device0;
345 else if (instance == 1)
346 pdev = &da8xx_i2c_device1;
347 else
348 return -EINVAL;
349
350 pdev->dev.platform_data = pdata;
351 return platform_device_register(pdev);
352}
353
354static struct resource da8xx_watchdog_resources[] = {
355 {
356 .start = DA8XX_WDOG_BASE,
357 .end = DA8XX_WDOG_BASE + SZ_4K - 1,
358 .flags = IORESOURCE_MEM,
359 },
360};
361
c78a5bc2 362struct platform_device da8xx_wdt_device = {
55c79a40
MG		 363 .name = "watchdog",
364 .id = -1,
365 .num_resources = ARRAY_SIZE(da8xx_watchdog_resources),
366 .resource = da8xx_watchdog_resources,
367};
368
c6121ddd
SN		 369void da8xx_restart(char mode, const char *cmd)
370{
371 davinci_watchdog_reset(&da8xx_wdt_device);
372}
373
55c79a40
MG		 374int __init da8xx_register_watchdog(void)
375{
c78a5bc2 376 return platform_device_register(&da8xx_wdt_device);
55c79a40
MG		 377}
378
379static struct resource da8xx_emac_resources[] = {
380 {
381 .start = DA8XX_EMAC_CPPI_PORT_BASE,
d22960c8 382 .end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1,
55c79a40
MG		 383 .flags = IORESOURCE_MEM,
384 },
385 {
386 .start = IRQ_DA8XX_C0_RX_THRESH_PULSE,
387 .end = IRQ_DA8XX_C0_RX_THRESH_PULSE,
388 .flags = IORESOURCE_IRQ,
389 },
390 {
391 .start = IRQ_DA8XX_C0_RX_PULSE,
392 .end = IRQ_DA8XX_C0_RX_PULSE,
393 .flags = IORESOURCE_IRQ,
394 },
395 {
396 .start = IRQ_DA8XX_C0_TX_PULSE,
397 .end = IRQ_DA8XX_C0_TX_PULSE,
398 .flags = IORESOURCE_IRQ,
399 },
400 {
401 .start = IRQ_DA8XX_C0_MISC_PULSE,
402 .end = IRQ_DA8XX_C0_MISC_PULSE,
403 .flags = IORESOURCE_IRQ,
404 },
405};
406
407struct emac_platform_data da8xx_emac_pdata = {
408 .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET,
409 .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET,
410 .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET,
55c79a40
MG		 411 .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE,
412 .version = EMAC_VERSION_2,
413};
414
415static struct platform_device da8xx_emac_device = {
416 .name = "davinci_emac",
417 .id = 1,
418 .dev = {
419 .platform_data = &da8xx_emac_pdata,
420 },
421 .num_resources = ARRAY_SIZE(da8xx_emac_resources),
422 .resource = da8xx_emac_resources,
423};
424
d22960c8
CC		 425static struct resource da8xx_mdio_resources[] = {
426 {
427 .start = DA8XX_EMAC_MDIO_BASE,
428 .end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1,
429 .flags = IORESOURCE_MEM,
430 },
431};
432
433static struct platform_device da8xx_mdio_device = {
434 .name = "davinci_mdio",
435 .id = 0,
436 .num_resources = ARRAY_SIZE(da8xx_mdio_resources),
437 .resource = da8xx_mdio_resources,
438};
439
31f53cf3
MG		 440int __init da8xx_register_emac(void)
441{
d22960c8
CC		 442 int ret;
443
444 ret = platform_device_register(&da8xx_mdio_device);
445 if (ret < 0)
446 return ret;
447 ret = platform_device_register(&da8xx_emac_device);
448 if (ret < 0)
449 return ret;
450 ret = clk_add_alias(NULL, dev_name(&da8xx_mdio_device.dev),
451 NULL, &da8xx_emac_device.dev);
452 return ret;
31f53cf3
MG		 453}
454
e33ef5e3
C		 455static struct resource da830_mcasp1_resources[] = {
456 {
457 .name = "mcasp1",
458 .start = DAVINCI_DA830_MCASP1_REG_BASE,
459 .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
460 .flags = IORESOURCE_MEM,
461 },
462 /* TX event */
463 {
464 .start = DAVINCI_DA830_DMA_MCASP1_AXEVT,
465 .end = DAVINCI_DA830_DMA_MCASP1_AXEVT,
466 .flags = IORESOURCE_DMA,
467 },
468 /* RX event */
469 {
470 .start = DAVINCI_DA830_DMA_MCASP1_AREVT,
471 .end = DAVINCI_DA830_DMA_MCASP1_AREVT,
472 .flags = IORESOURCE_DMA,
473 },
474};
475
476static struct platform_device da830_mcasp1_device = {
477 .name = "davinci-mcasp",
478 .id = 1,
479 .num_resources = ARRAY_SIZE(da830_mcasp1_resources),
480 .resource = da830_mcasp1_resources,
481};
482
491214e1
C		 483static struct resource da850_mcasp_resources[] = {
484 {
485 .name = "mcasp",
486 .start = DAVINCI_DA8XX_MCASP0_REG_BASE,
487 .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
488 .flags = IORESOURCE_MEM,
489 },
490 /* TX event */
491 {
492 .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
493 .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
494 .flags = IORESOURCE_DMA,
495 },
496 /* RX event */
497 {
498 .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
499 .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
500 .flags = IORESOURCE_DMA,
501 },
502};
503
504static struct platform_device da850_mcasp_device = {
505 .name = "davinci-mcasp",
506 .id = 0,
507 .num_resources = ARRAY_SIZE(da850_mcasp_resources),
508 .resource = da850_mcasp_resources,
509};
510
b8864aa4 511void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
e33ef5e3 512{
491214e1
C		 513 /* DA830/OMAP-L137 has 3 instances of McASP */
514 if (cpu_is_davinci_da830() && id == 1) {
e33ef5e3
C		 515 da830_mcasp1_device.dev.platform_data = pdata;
516 platform_device_register(&da830_mcasp1_device);
491214e1
C		 517 } else if (cpu_is_davinci_da850()) {
518 da850_mcasp_device.dev.platform_data = pdata;
519 platform_device_register(&da850_mcasp_device);
e33ef5e3
C		 520 }
521}
5cbdf276 522
8e0d72d2
MP		 523static struct resource da8xx_pruss_resources[] = {
524 {
525 .start = DA8XX_PRUSS_MEM_BASE,
526 .end = DA8XX_PRUSS_MEM_BASE + 0xFFFF,
527 .flags = IORESOURCE_MEM,
528 },
529 {
530 .start = IRQ_DA8XX_EVTOUT0,
531 .end = IRQ_DA8XX_EVTOUT0,
532 .flags = IORESOURCE_IRQ,
533 },
534 {
535 .start = IRQ_DA8XX_EVTOUT1,
536 .end = IRQ_DA8XX_EVTOUT1,
537 .flags = IORESOURCE_IRQ,
538 },
539 {
540 .start = IRQ_DA8XX_EVTOUT2,
541 .end = IRQ_DA8XX_EVTOUT2,
542 .flags = IORESOURCE_IRQ,
543 },
544 {
545 .start = IRQ_DA8XX_EVTOUT3,
546 .end = IRQ_DA8XX_EVTOUT3,
547 .flags = IORESOURCE_IRQ,
548 },
549 {
550 .start = IRQ_DA8XX_EVTOUT4,
551 .end = IRQ_DA8XX_EVTOUT4,
552 .flags = IORESOURCE_IRQ,
553 },
554 {
555 .start = IRQ_DA8XX_EVTOUT5,
556 .end = IRQ_DA8XX_EVTOUT5,
557 .flags = IORESOURCE_IRQ,
558 },
559 {
560 .start = IRQ_DA8XX_EVTOUT6,
561 .end = IRQ_DA8XX_EVTOUT6,
562 .flags = IORESOURCE_IRQ,
563 },
564 {
565 .start = IRQ_DA8XX_EVTOUT7,
566 .end = IRQ_DA8XX_EVTOUT7,
567 .flags = IORESOURCE_IRQ,
568 },
569};
570
571static struct uio_pruss_pdata da8xx_uio_pruss_pdata = {
572 .pintc_base = 0x4000,
573};
574
575static struct platform_device da8xx_uio_pruss_dev = {
576 .name = "pruss_uio",
577 .id = -1,
578 .num_resources = ARRAY_SIZE(da8xx_pruss_resources),
579 .resource = da8xx_pruss_resources,
580 .dev = {
581 .coherent_dma_mask = DMA_BIT_MASK(32),
582 .platform_data = &da8xx_uio_pruss_pdata,
583 }
584};
585
586int __init da8xx_register_uio_pruss(void)
587{
588 da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool();
589 return platform_device_register(&da8xx_uio_pruss_dev);
590}
591
5cbdf276 592static struct lcd_ctrl_config lcd_cfg = {
3b43ad20 593 .panel_shade = COLOR_ACTIVE,
5cbdf276 594 .bpp = 16,
5cbdf276
SR		 595};
596
b9e6342b
MG		 597struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
598 .manu_name = "sharp",
599 .controller_data = &lcd_cfg,
600 .type = "Sharp_LCD035Q3DG01",
601};
602
603struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
604 .manu_name = "sharp",
605 .controller_data = &lcd_cfg,
606 .type = "Sharp_LK043T1DG01",
5cbdf276
SR		 607};
608
609static struct resource da8xx_lcdc_resources[] = {
610 [0] = { /* registers */
611 .start = DA8XX_LCD_CNTRL_BASE,
612 .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
613 .flags = IORESOURCE_MEM,
614 },
615 [1] = { /* interrupt */
616 .start = IRQ_DA8XX_LCDINT,
617 .end = IRQ_DA8XX_LCDINT,
618 .flags = IORESOURCE_IRQ,
619 },
620};
621
b9e6342b 622static struct platform_device da8xx_lcdc_device = {
5cbdf276
SR		 623 .name = "da8xx_lcdc",
624 .id = 0,
625 .num_resources = ARRAY_SIZE(da8xx_lcdc_resources),
626 .resource = da8xx_lcdc_resources,
5cbdf276
SR		 627};
628
b9e6342b 629int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
5cbdf276 630{
b9e6342b
MG		 631 da8xx_lcdc_device.dev.platform_data = pdata;
632 return platform_device_register(&da8xx_lcdc_device);
5cbdf276 633}
700691f2
SR		 634
635static struct resource da8xx_mmcsd0_resources[] = {
636 { /* registers */
637 .start = DA8XX_MMCSD0_BASE,
638 .end = DA8XX_MMCSD0_BASE + SZ_4K - 1,
639 .flags = IORESOURCE_MEM,
640 },
641 { /* interrupt */
642 .start = IRQ_DA8XX_MMCSDINT0,
643 .end = IRQ_DA8XX_MMCSDINT0,
644 .flags = IORESOURCE_IRQ,
645 },
646 { /* DMA RX */
e38c2b22
MW		 647 .start = DA8XX_DMA_MMCSD0_RX,
648 .end = DA8XX_DMA_MMCSD0_RX,
700691f2
SR		 649 .flags = IORESOURCE_DMA,
650 },
651 { /* DMA TX */
e38c2b22
MW		 652 .start = DA8XX_DMA_MMCSD0_TX,
653 .end = DA8XX_DMA_MMCSD0_TX,
700691f2
SR		 654 .flags = IORESOURCE_DMA,
655 },
656};
657
658static struct platform_device da8xx_mmcsd0_device = {
659 .name = "davinci_mmc",
660 .id = 0,
661 .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources),
662 .resource = da8xx_mmcsd0_resources,
663};
664
665int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
666{
667 da8xx_mmcsd0_device.dev.platform_data = config;
668 return platform_device_register(&da8xx_mmcsd0_device);
669}
c51df70b 670
b8241aef
JK		 671#ifdef CONFIG_ARCH_DAVINCI_DA850
672static struct resource da850_mmcsd1_resources[] = {
673 { /* registers */
674 .start = DA850_MMCSD1_BASE,
675 .end = DA850_MMCSD1_BASE + SZ_4K - 1,
676 .flags = IORESOURCE_MEM,
677 },
678 { /* interrupt */
679 .start = IRQ_DA850_MMCSDINT0_1,
680 .end = IRQ_DA850_MMCSDINT0_1,
681 .flags = IORESOURCE_IRQ,
682 },
683 { /* DMA RX */
e38c2b22
MW		 684 .start = DA850_DMA_MMCSD1_RX,
685 .end = DA850_DMA_MMCSD1_RX,
b8241aef
JK		 686 .flags = IORESOURCE_DMA,
687 },
688 { /* DMA TX */
e38c2b22
MW		 689 .start = DA850_DMA_MMCSD1_TX,
690 .end = DA850_DMA_MMCSD1_TX,
b8241aef
JK		 691 .flags = IORESOURCE_DMA,
692 },
693};
694
695static struct platform_device da850_mmcsd1_device = {
696 .name = "davinci_mmc",
697 .id = 1,
698 .num_resources = ARRAY_SIZE(da850_mmcsd1_resources),
699 .resource = da850_mmcsd1_resources,
700};
701
702int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
703{
704 da850_mmcsd1_device.dev.platform_data = config;
705 return platform_device_register(&da850_mmcsd1_device);
706}
707#endif
708
c51df70b
MG		 709static struct resource da8xx_rtc_resources[] = {
710 {
711 .start = DA8XX_RTC_BASE,
712 .end = DA8XX_RTC_BASE + SZ_4K - 1,
713 .flags = IORESOURCE_MEM,
714 },
715 { /* timer irq */
716 .start = IRQ_DA8XX_RTC,
717 .end = IRQ_DA8XX_RTC,
718 .flags = IORESOURCE_IRQ,
719 },
720 { /* alarm irq */
721 .start = IRQ_DA8XX_RTC,
722 .end = IRQ_DA8XX_RTC,
723 .flags = IORESOURCE_IRQ,
724 },
725};
726
727static struct platform_device da8xx_rtc_device = {
852168c9 728 .name = "da830-rtc",
c51df70b
MG		 729 .id = -1,
730 .num_resources = ARRAY_SIZE(da8xx_rtc_resources),
731 .resource = da8xx_rtc_resources,
732};
733
734int da8xx_register_rtc(void)
735{
75c99bb0 736 int ret;
c51df70b 737
75c99bb0
SN		 738 ret = platform_device_register(&da8xx_rtc_device);
739 if (!ret)
740 /* Atleast on DA850, RTC is a wakeup source */
741 device_init_wakeup(&da8xx_rtc_device.dev, true);
742
743 return ret;
c51df70b 744}
1960e693 745
948c66df
SN		 746static void __iomem *da8xx_ddr2_ctlr_base;
747void __iomem * __init da8xx_get_mem_ctlr(void)
748{
749 if (da8xx_ddr2_ctlr_base)
750 return da8xx_ddr2_ctlr_base;
751
752 da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
753 if (!da8xx_ddr2_ctlr_base)
754 pr_warning("%s: Unable to map DDR2 controller", __func__);
755
756 return da8xx_ddr2_ctlr_base;
757}
758
1960e693
SN		 759static struct resource da8xx_cpuidle_resources[] = {
760 {
761 .start = DA8XX_DDR2_CTL_BASE,
762 .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
763 .flags = IORESOURCE_MEM,
764 },
765};
766
767/* DA8XX devices support DDR2 power down */
768static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
769 .ddr2_pdown = 1,
770};
771
772
773static struct platform_device da8xx_cpuidle_device = {
774 .name = "cpuidle-davinci",
775 .num_resources = ARRAY_SIZE(da8xx_cpuidle_resources),
776 .resource = da8xx_cpuidle_resources,
777 .dev = {
778 .platform_data = &da8xx_cpuidle_pdata,
779 },
780};
781
782int __init da8xx_register_cpuidle(void)
783{
948c66df
SN		 784 da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
785
1960e693
SN		 786 return platform_device_register(&da8xx_cpuidle_device);
787}
54ce6883
MW		 788
789static struct resource da8xx_spi0_resources[] = {
790 [0] = {
791 .start = DA8XX_SPI0_BASE,
792 .end = DA8XX_SPI0_BASE + SZ_4K - 1,
793 .flags = IORESOURCE_MEM,
794 },
795 [1] = {
796 .start = IRQ_DA8XX_SPINT0,
797 .end = IRQ_DA8XX_SPINT0,
798 .flags = IORESOURCE_IRQ,
799 },
800 [2] = {
801 .start = DA8XX_DMA_SPI0_RX,
802 .end = DA8XX_DMA_SPI0_RX,
803 .flags = IORESOURCE_DMA,
804 },
805 [3] = {
806 .start = DA8XX_DMA_SPI0_TX,
807 .end = DA8XX_DMA_SPI0_TX,
808 .flags = IORESOURCE_DMA,
809 },
810};
811
812static struct resource da8xx_spi1_resources[] = {
813 [0] = {
9e7d24f6
SS		 814 .start = DA830_SPI1_BASE,
815 .end = DA830_SPI1_BASE + SZ_4K - 1,
54ce6883
MW		 816 .flags = IORESOURCE_MEM,
817 },
818 [1] = {
819 .start = IRQ_DA8XX_SPINT1,
820 .end = IRQ_DA8XX_SPINT1,
821 .flags = IORESOURCE_IRQ,
822 },
823 [2] = {
824 .start = DA8XX_DMA_SPI1_RX,
825 .end = DA8XX_DMA_SPI1_RX,
826 .flags = IORESOURCE_DMA,
827 },
828 [3] = {
829 .start = DA8XX_DMA_SPI1_TX,
830 .end = DA8XX_DMA_SPI1_TX,
831 .flags = IORESOURCE_DMA,
832 },
833};
834
835struct davinci_spi_platform_data da8xx_spi_pdata[] = {
836 [0] = {
837 .version = SPI_VERSION_2,
838 .intr_line = 1,
839 .dma_event_q = EVENTQ_0,
840 },
841 [1] = {
842 .version = SPI_VERSION_2,
843 .intr_line = 1,
844 .dma_event_q = EVENTQ_0,
845 },
846};
847
848static struct platform_device da8xx_spi_device[] = {
849 [0] = {
850 .name = "spi_davinci",
851 .id = 0,
852 .num_resources = ARRAY_SIZE(da8xx_spi0_resources),
853 .resource = da8xx_spi0_resources,
854 .dev = {
855 .platform_data = &da8xx_spi_pdata[0],
856 },
857 },
858 [1] = {
859 .name = "spi_davinci",
860 .id = 1,
861 .num_resources = ARRAY_SIZE(da8xx_spi1_resources),
862 .resource = da8xx_spi1_resources,
863 .dev = {
864 .platform_data = &da8xx_spi_pdata[1],
865 },
866 },
867};
868
d65566e5 869int __init da8xx_register_spi(int instance, const struct spi_board_info *info,
54ce6883
MW		 870 unsigned len)
871{
872 int ret;
873
874 if (instance < 0 || instance > 1)
875 return -EINVAL;
876
877 ret = spi_register_board_info(info, len);
878 if (ret)
879 pr_warning("%s: failed to register board info for spi %d :"
880 " %d\n", __func__, instance, ret);
881
882 da8xx_spi_pdata[instance].num_chipselect = len;
883
9e7d24f6
SS		 884 if (instance == 1 && cpu_is_davinci_da850()) {
885 da8xx_spi1_resources[0].start = DA850_SPI1_BASE;
886 da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1;
887 }
888
54ce6883
MW		 889 return platform_device_register(&da8xx_spi_device[instance]);
890}
cbb2c961
SN		 891
892#ifdef CONFIG_ARCH_DAVINCI_DA850
893
894static struct resource da850_sata_resources[] = {
895 {
896 .start = DA850_SATA_BASE,
897 .end = DA850_SATA_BASE + 0x1fff,
898 .flags = IORESOURCE_MEM,
899 },
900 {
901 .start = IRQ_DA850_SATAINT,
902 .flags = IORESOURCE_IRQ,
903 },
904};
905
906/* SATA PHY Control Register offset from AHCI base */
907#define SATA_P0PHYCR_REG 0x178
908
909#define SATA_PHY_MPY(x) ((x) << 0)
910#define SATA_PHY_LOS(x) ((x) << 6)
911#define SATA_PHY_RXCDR(x) ((x) << 10)
912#define SATA_PHY_RXEQ(x) ((x) << 13)
913#define SATA_PHY_TXSWING(x) ((x) << 19)
914#define SATA_PHY_ENPLL(x) ((x) << 31)
915
916static struct clk *da850_sata_clk;
917static unsigned long da850_sata_refclkpn;
918
919/* Supported DA850 SATA crystal frequencies */
920#define KHZ_TO_HZ(freq) ((freq) * 1000)
921static unsigned long da850_sata_xtal[] = {
922 KHZ_TO_HZ(300000),
923 KHZ_TO_HZ(250000),
924 0, /* Reserved */
925 KHZ_TO_HZ(187500),
926 KHZ_TO_HZ(150000),
927 KHZ_TO_HZ(125000),
928 KHZ_TO_HZ(120000),
929 KHZ_TO_HZ(100000),
930 KHZ_TO_HZ(75000),
931 KHZ_TO_HZ(60000),
932};
933
934static int da850_sata_init(struct device *dev, void __iomem *addr)
935{
936 int i, ret;
937 unsigned int val;
938
939 da850_sata_clk = clk_get(dev, NULL);
940 if (IS_ERR(da850_sata_clk))
941 return PTR_ERR(da850_sata_clk);
942
b6f1ffed 943 ret = clk_prepare_enable(da850_sata_clk);
cbb2c961
SN		 944 if (ret)
945 goto err0;
946
947 /* Enable SATA clock receiver */
948 val = __raw_readl(DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG));
949 val &= ~BIT(0);
950 __raw_writel(val, DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG));
951
952 /* Get the multiplier needed for 1.5GHz PLL output */
953 for (i = 0; i < ARRAY_SIZE(da850_sata_xtal); i++)
954 if (da850_sata_xtal[i] == da850_sata_refclkpn)
955 break;
956
957 if (i == ARRAY_SIZE(da850_sata_xtal)) {
958 ret = -EINVAL;
959 goto err1;
960 }
961
962 val = SATA_PHY_MPY(i + 1) |
963 SATA_PHY_LOS(1) |
964 SATA_PHY_RXCDR(4) |
965 SATA_PHY_RXEQ(1) |
966 SATA_PHY_TXSWING(3) |
967 SATA_PHY_ENPLL(1);
968
969 __raw_writel(val, addr + SATA_P0PHYCR_REG);
970
971 return 0;
972
973err1:
b6f1ffed 974 clk_disable_unprepare(da850_sata_clk);
cbb2c961
SN		 975err0:
976 clk_put(da850_sata_clk);
977 return ret;
978}
979
980static void da850_sata_exit(struct device *dev)
981{
b6f1ffed 982 clk_disable_unprepare(da850_sata_clk);
cbb2c961
SN		 983 clk_put(da850_sata_clk);
984}
985
986static struct ahci_platform_data da850_sata_pdata = {
987 .init = da850_sata_init,
988 .exit = da850_sata_exit,
989};
990
991static u64 da850_sata_dmamask = DMA_BIT_MASK(32);
992
993static struct platform_device da850_sata_device = {
994 .name = "ahci",
995 .id = -1,
996 .dev = {
997 .platform_data = &da850_sata_pdata,
998 .dma_mask = &da850_sata_dmamask,
999 .coherent_dma_mask = DMA_BIT_MASK(32),
1000 },
1001 .num_resources = ARRAY_SIZE(da850_sata_resources),
1002 .resource = da850_sata_resources,
1003};
1004
1005int __init da850_register_sata(unsigned long refclkpn)
1006{
1007 da850_sata_refclkpn = refclkpn;
1008 if (!da850_sata_refclkpn)
1009 return -EINVAL;
1010
1011 return platform_device_register(&da850_sata_device);
1012}
1013#endif
Linux kernel - Deliverables
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