[deliverable/linux.git] / arch / arm / mach-davinci / devices-da8xx.c

/*
 * DA8XX/OMAP L1XX platform device data
 *
 * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
 * Derived from code that was:
 *	Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/serial_8250.h>

#include <mach/cputype.h>
#include <mach/common.h>
#include <mach/time.h>
#include <mach/da8xx.h>
#include <mach/cpuidle.h>

#include "clock.h"

#define DA8XX_TPCC_BASE			0x01c00000
#define DA850_TPCC1_BASE		0x01e30000
#define DA8XX_TPTC0_BASE		0x01c08000
#define DA8XX_TPTC1_BASE		0x01c08400
#define DA850_TPTC2_BASE		0x01e38000
#define DA8XX_WDOG_BASE			0x01c21000 /* DA8XX_TIMER64P1_BASE */
#define DA8XX_I2C0_BASE			0x01c22000
#define DA8XX_RTC_BASE			0x01C23000
#define DA8XX_EMAC_CPPI_PORT_BASE	0x01e20000
#define DA8XX_EMAC_CPGMACSS_BASE	0x01e22000
#define DA8XX_EMAC_CPGMAC_BASE		0x01e23000
#define DA8XX_EMAC_MDIO_BASE		0x01e24000
#define DA8XX_GPIO_BASE			0x01e26000
#define DA8XX_I2C1_BASE			0x01e28000

#define DA8XX_EMAC_CTRL_REG_OFFSET	0x3000
#define DA8XX_EMAC_MOD_REG_OFFSET	0x2000
#define DA8XX_EMAC_RAM_OFFSET		0x0000
#define DA8XX_MDIO_REG_OFFSET		0x4000
#define DA8XX_EMAC_CTRL_RAM_SIZE	SZ_8K

void __iomem *da8xx_syscfg0_base;
void __iomem *da8xx_syscfg1_base;

static struct plat_serial8250_port da8xx_serial_pdata[] = {
	{
		.mapbase	= DA8XX_UART0_BASE,
		.irq		= IRQ_DA8XX_UARTINT0,
		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
					UPF_IOREMAP,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
	},
	{
		.mapbase	= DA8XX_UART1_BASE,
		.irq		= IRQ_DA8XX_UARTINT1,
		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
					UPF_IOREMAP,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
	},
	{
		.mapbase	= DA8XX_UART2_BASE,
		.irq		= IRQ_DA8XX_UARTINT2,
		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
					UPF_IOREMAP,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
	},
	{
		.flags	= 0,
	},
};

struct platform_device da8xx_serial_device = {
	.name	= "serial8250",
	.id	= PLAT8250_DEV_PLATFORM,
	.dev	= {
		.platform_data	= da8xx_serial_pdata,
	},
};

static const s8 da8xx_queue_tc_mapping[][2] = {
	/* {event queue no, TC no} */
	{0, 0},
	{1, 1},
	{-1, -1}
};

static const s8 da8xx_queue_priority_mapping[][2] = {
	/* {event queue no, Priority} */
	{0, 3},
	{1, 7},
	{-1, -1}
};

static const s8 da850_queue_tc_mapping[][2] = {
	/* {event queue no, TC no} */
	{0, 0},
	{-1, -1}
};

static const s8 da850_queue_priority_mapping[][2] = {
	/* {event queue no, Priority} */
	{0, 3},
	{-1, -1}
};

static struct edma_soc_info da830_edma_cc0_info = {
	.n_channel		= 32,
	.n_region		= 4,
	.n_slot			= 128,
	.n_tc			= 2,
	.n_cc			= 1,
	.queue_tc_mapping	= da8xx_queue_tc_mapping,
	.queue_priority_mapping	= da8xx_queue_priority_mapping,
};

static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = {
	&da830_edma_cc0_info,
};

static struct edma_soc_info da850_edma_cc_info[] = {
	{
		.n_channel		= 32,
		.n_region		= 4,
		.n_slot			= 128,
		.n_tc			= 2,
		.n_cc			= 1,
		.queue_tc_mapping	= da8xx_queue_tc_mapping,
		.queue_priority_mapping	= da8xx_queue_priority_mapping,
	},
	{
		.n_channel		= 32,
		.n_region		= 4,
		.n_slot			= 128,
		.n_tc			= 1,
		.n_cc			= 1,
		.queue_tc_mapping	= da850_queue_tc_mapping,
		.queue_priority_mapping	= da850_queue_priority_mapping,
	},
};

static struct edma_soc_info *da850_edma_info[EDMA_MAX_CC] = {
	&da850_edma_cc_info[0],
	&da850_edma_cc_info[1],
};

static struct resource da830_edma_resources[] = {
	{
		.name	= "edma_cc0",
		.start	= DA8XX_TPCC_BASE,
		.end	= DA8XX_TPCC_BASE + SZ_32K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma_tc0",
		.start	= DA8XX_TPTC0_BASE,
		.end	= DA8XX_TPTC0_BASE + SZ_1K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma_tc1",
		.start	= DA8XX_TPTC1_BASE,
		.end	= DA8XX_TPTC1_BASE + SZ_1K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma0",
		.start	= IRQ_DA8XX_CCINT0,
		.flags	= IORESOURCE_IRQ,
	},
	{
		.name	= "edma0_err",
		.start	= IRQ_DA8XX_CCERRINT,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct resource da850_edma_resources[] = {
	{
		.name	= "edma_cc0",
		.start	= DA8XX_TPCC_BASE,
		.end	= DA8XX_TPCC_BASE + SZ_32K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma_tc0",
		.start	= DA8XX_TPTC0_BASE,
		.end	= DA8XX_TPTC0_BASE + SZ_1K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma_tc1",
		.start	= DA8XX_TPTC1_BASE,
		.end	= DA8XX_TPTC1_BASE + SZ_1K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma_cc1",
		.start	= DA850_TPCC1_BASE,
		.end	= DA850_TPCC1_BASE + SZ_32K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma_tc2",
		.start	= DA850_TPTC2_BASE,
		.end	= DA850_TPTC2_BASE + SZ_1K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma0",
		.start	= IRQ_DA8XX_CCINT0,
		.flags	= IORESOURCE_IRQ,
	},
	{
		.name	= "edma0_err",
		.start	= IRQ_DA8XX_CCERRINT,
		.flags	= IORESOURCE_IRQ,
	},
	{
		.name	= "edma1",
		.start	= IRQ_DA850_CCINT1,
		.flags	= IORESOURCE_IRQ,
	},
	{
		.name	= "edma1_err",
		.start	= IRQ_DA850_CCERRINT1,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device da830_edma_device = {
	.name		= "edma",
	.id		= -1,
	.dev = {
		.platform_data = da830_edma_info,
	},
	.num_resources	= ARRAY_SIZE(da830_edma_resources),
	.resource	= da830_edma_resources,
};

static struct platform_device da850_edma_device = {
	.name		= "edma",
	.id		= -1,
	.dev = {
		.platform_data = da850_edma_info,
	},
	.num_resources	= ARRAY_SIZE(da850_edma_resources),
	.resource	= da850_edma_resources,
};

int __init da8xx_register_edma(void)
{
	struct platform_device *pdev;

	if (cpu_is_davinci_da830())
		pdev = &da830_edma_device;
	else if (cpu_is_davinci_da850())
		pdev = &da850_edma_device;
	else
		return -ENODEV;

	return platform_device_register(pdev);
}

static struct resource da8xx_i2c_resources0[] = {
	{
		.start	= DA8XX_I2C0_BASE,
		.end	= DA8XX_I2C0_BASE + SZ_4K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= IRQ_DA8XX_I2CINT0,
		.end	= IRQ_DA8XX_I2CINT0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device da8xx_i2c_device0 = {
	.name		= "i2c_davinci",
	.id		= 1,
	.num_resources	= ARRAY_SIZE(da8xx_i2c_resources0),
	.resource	= da8xx_i2c_resources0,
};

static struct resource da8xx_i2c_resources1[] = {
	{
		.start	= DA8XX_I2C1_BASE,
		.end	= DA8XX_I2C1_BASE + SZ_4K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= IRQ_DA8XX_I2CINT1,
		.end	= IRQ_DA8XX_I2CINT1,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device da8xx_i2c_device1 = {
	.name		= "i2c_davinci",
	.id		= 2,
	.num_resources	= ARRAY_SIZE(da8xx_i2c_resources1),
	.resource	= da8xx_i2c_resources1,
};

int __init da8xx_register_i2c(int instance,
		struct davinci_i2c_platform_data *pdata)
{
	struct platform_device *pdev;

	if (instance == 0)
		pdev = &da8xx_i2c_device0;
	else if (instance == 1)
		pdev = &da8xx_i2c_device1;
	else
		return -EINVAL;

	pdev->dev.platform_data = pdata;
	return platform_device_register(pdev);
}

static struct resource da8xx_watchdog_resources[] = {
	{
		.start	= DA8XX_WDOG_BASE,
		.end	= DA8XX_WDOG_BASE + SZ_4K - 1,
		.flags	= IORESOURCE_MEM,
	},
};

struct platform_device da8xx_wdt_device = {
	.name		= "watchdog",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(da8xx_watchdog_resources),
	.resource	= da8xx_watchdog_resources,
};

int __init da8xx_register_watchdog(void)
{
	return platform_device_register(&da8xx_wdt_device);
}

static struct resource da8xx_emac_resources[] = {
	{
		.start	= DA8XX_EMAC_CPPI_PORT_BASE,
		.end	= DA8XX_EMAC_CPPI_PORT_BASE + 0x5000 - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= IRQ_DA8XX_C0_RX_THRESH_PULSE,
		.end	= IRQ_DA8XX_C0_RX_THRESH_PULSE,
		.flags	= IORESOURCE_IRQ,
	},
	{
		.start	= IRQ_DA8XX_C0_RX_PULSE,
		.end	= IRQ_DA8XX_C0_RX_PULSE,
		.flags	= IORESOURCE_IRQ,
	},
	{
		.start	= IRQ_DA8XX_C0_TX_PULSE,
		.end	= IRQ_DA8XX_C0_TX_PULSE,
		.flags	= IORESOURCE_IRQ,
	},
	{
		.start	= IRQ_DA8XX_C0_MISC_PULSE,
		.end	= IRQ_DA8XX_C0_MISC_PULSE,
		.flags	= IORESOURCE_IRQ,
	},
};

struct emac_platform_data da8xx_emac_pdata = {
	.ctrl_reg_offset	= DA8XX_EMAC_CTRL_REG_OFFSET,
	.ctrl_mod_reg_offset	= DA8XX_EMAC_MOD_REG_OFFSET,
	.ctrl_ram_offset	= DA8XX_EMAC_RAM_OFFSET,
	.mdio_reg_offset	= DA8XX_MDIO_REG_OFFSET,
	.ctrl_ram_size		= DA8XX_EMAC_CTRL_RAM_SIZE,
	.version		= EMAC_VERSION_2,
};

static struct platform_device da8xx_emac_device = {
	.name		= "davinci_emac",
	.id		= 1,
	.dev = {
		.platform_data	= &da8xx_emac_pdata,
	},
	.num_resources	= ARRAY_SIZE(da8xx_emac_resources),
	.resource	= da8xx_emac_resources,
};

int __init da8xx_register_emac(void)
{
	return platform_device_register(&da8xx_emac_device);
}

static struct resource da830_mcasp1_resources[] = {
	{
		.name	= "mcasp1",
		.start	= DAVINCI_DA830_MCASP1_REG_BASE,
		.end	= DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
		.flags	= IORESOURCE_MEM,
	},
	/* TX event */
	{
		.start	= DAVINCI_DA830_DMA_MCASP1_AXEVT,
		.end	= DAVINCI_DA830_DMA_MCASP1_AXEVT,
		.flags	= IORESOURCE_DMA,
	},
	/* RX event */
	{
		.start	= DAVINCI_DA830_DMA_MCASP1_AREVT,
		.end	= DAVINCI_DA830_DMA_MCASP1_AREVT,
		.flags	= IORESOURCE_DMA,
	},
};

static struct platform_device da830_mcasp1_device = {
	.name		= "davinci-mcasp",
	.id		= 1,
	.num_resources	= ARRAY_SIZE(da830_mcasp1_resources),
	.resource	= da830_mcasp1_resources,
};

static struct resource da850_mcasp_resources[] = {
	{
		.name	= "mcasp",
		.start	= DAVINCI_DA8XX_MCASP0_REG_BASE,
		.end	= DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
		.flags	= IORESOURCE_MEM,
	},
	/* TX event */
	{
		.start	= DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
		.end	= DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
		.flags	= IORESOURCE_DMA,
	},
	/* RX event */
	{
		.start	= DAVINCI_DA8XX_DMA_MCASP0_AREVT,
		.end	= DAVINCI_DA8XX_DMA_MCASP0_AREVT,
		.flags	= IORESOURCE_DMA,
	},
};

static struct platform_device da850_mcasp_device = {
	.name		= "davinci-mcasp",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(da850_mcasp_resources),
	.resource	= da850_mcasp_resources,
};

void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
{
	/* DA830/OMAP-L137 has 3 instances of McASP */
	if (cpu_is_davinci_da830() && id == 1) {
		da830_mcasp1_device.dev.platform_data = pdata;
		platform_device_register(&da830_mcasp1_device);
	} else if (cpu_is_davinci_da850()) {
		da850_mcasp_device.dev.platform_data = pdata;
		platform_device_register(&da850_mcasp_device);
	}
}

static const struct display_panel disp_panel = {
	QVGA,
	16,
	16,
	COLOR_ACTIVE,
};

static struct lcd_ctrl_config lcd_cfg = {
	&disp_panel,
	.ac_bias		= 255,
	.ac_bias_intrpt		= 0,
	.dma_burst_sz		= 16,
	.bpp			= 16,
	.fdd			= 255,
	.tft_alt_mode		= 0,
	.stn_565_mode		= 0,
	.mono_8bit_mode		= 0,
	.invert_line_clock	= 1,
	.invert_frm_clock	= 1,
	.sync_edge		= 0,
	.sync_ctrl		= 1,
	.raster_order		= 0,
};

struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
	.manu_name		= "sharp",
	.controller_data	= &lcd_cfg,
	.type			= "Sharp_LCD035Q3DG01",
};

struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
	.manu_name		= "sharp",
	.controller_data	= &lcd_cfg,
	.type			= "Sharp_LK043T1DG01",
};

static struct resource da8xx_lcdc_resources[] = {
	[0] = { /* registers */
		.start  = DA8XX_LCD_CNTRL_BASE,
		.end    = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
		.flags  = IORESOURCE_MEM,
	},
	[1] = { /* interrupt */
		.start  = IRQ_DA8XX_LCDINT,
		.end    = IRQ_DA8XX_LCDINT,
		.flags  = IORESOURCE_IRQ,
	},
};

static struct platform_device da8xx_lcdc_device = {
	.name		= "da8xx_lcdc",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(da8xx_lcdc_resources),
	.resource	= da8xx_lcdc_resources,
};

int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
{
	da8xx_lcdc_device.dev.platform_data = pdata;
	return platform_device_register(&da8xx_lcdc_device);
}

static struct resource da8xx_mmcsd0_resources[] = {
	{		/* registers */
		.start	= DA8XX_MMCSD0_BASE,
		.end	= DA8XX_MMCSD0_BASE + SZ_4K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{		/* interrupt */
		.start	= IRQ_DA8XX_MMCSDINT0,
		.end	= IRQ_DA8XX_MMCSDINT0,
		.flags	= IORESOURCE_IRQ,
	},
	{		/* DMA RX */
		.start	= EDMA_CTLR_CHAN(0, 16),
		.end	= EDMA_CTLR_CHAN(0, 16),
		.flags	= IORESOURCE_DMA,
	},
	{		/* DMA TX */
		.start	= EDMA_CTLR_CHAN(0, 17),
		.end	= EDMA_CTLR_CHAN(0, 17),
		.flags	= IORESOURCE_DMA,
	},
};

static struct platform_device da8xx_mmcsd0_device = {
	.name		= "davinci_mmc",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(da8xx_mmcsd0_resources),
	.resource	= da8xx_mmcsd0_resources,
};

int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
{
	da8xx_mmcsd0_device.dev.platform_data = config;
	return platform_device_register(&da8xx_mmcsd0_device);
}

static struct resource da8xx_rtc_resources[] = {
	{
		.start		= DA8XX_RTC_BASE,
		.end		= DA8XX_RTC_BASE + SZ_4K - 1,
		.flags		= IORESOURCE_MEM,
	},
	{ /* timer irq */
		.start		= IRQ_DA8XX_RTC,
		.end		= IRQ_DA8XX_RTC,
		.flags		= IORESOURCE_IRQ,
	},
	{ /* alarm irq */
		.start		= IRQ_DA8XX_RTC,
		.end		= IRQ_DA8XX_RTC,
		.flags		= IORESOURCE_IRQ,
	},
};

static struct platform_device da8xx_rtc_device = {
	.name           = "omap_rtc",
	.id             = -1,
	.num_resources	= ARRAY_SIZE(da8xx_rtc_resources),
	.resource	= da8xx_rtc_resources,
};

int da8xx_register_rtc(void)
{
	int ret;
	void __iomem *base;

	base = ioremap(DA8XX_RTC_BASE, SZ_4K);
	if (WARN_ON(!base))
		return -ENOMEM;

	/* Unlock the rtc's registers */
	__raw_writel(0x83e70b13, base + 0x6c);
	__raw_writel(0x95a4f1e0, base + 0x70);

	iounmap(base);

	ret = platform_device_register(&da8xx_rtc_device);
	if (!ret)
		/* Atleast on DA850, RTC is a wakeup source */
		device_init_wakeup(&da8xx_rtc_device.dev, true);

	return ret;
}

static void __iomem *da8xx_ddr2_ctlr_base;
void __iomem * __init da8xx_get_mem_ctlr(void)
{
	if (da8xx_ddr2_ctlr_base)
		return da8xx_ddr2_ctlr_base;

	da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
	if (!da8xx_ddr2_ctlr_base)
		pr_warning("%s: Unable to map DDR2 controller",	__func__);

	return da8xx_ddr2_ctlr_base;
}

static struct resource da8xx_cpuidle_resources[] = {
	{
		.start		= DA8XX_DDR2_CTL_BASE,
		.end		= DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
		.flags		= IORESOURCE_MEM,
	},
};

/* DA8XX devices support DDR2 power down */
static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
	.ddr2_pdown	= 1,
};


static struct platform_device da8xx_cpuidle_device = {
	.name			= "cpuidle-davinci",
	.num_resources		= ARRAY_SIZE(da8xx_cpuidle_resources),
	.resource		= da8xx_cpuidle_resources,
	.dev = {
		.platform_data	= &da8xx_cpuidle_pdata,
	},
};

int __init da8xx_register_cpuidle(void)
{
	da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();

	return platform_device_register(&da8xx_cpuidle_device);
}
Commit	Line	Data
55c79a40 MG	1	/*
	2	* DA8XX/OMAP L1XX platform device data
	3	*
	4	* Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
	5	* Derived from code that was:
	6	* Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*/
55c79a40 MG	13	#include <linux/init.h>
	14	#include <linux/platform_device.h>
	15	#include <linux/dma-mapping.h>
	16	#include <linux/serial_8250.h>
	17
	18	#include <mach/cputype.h>
	19	#include <mach/common.h>
	20	#include <mach/time.h>
	21	#include <mach/da8xx.h>
1960e693	22	#include <mach/cpuidle.h>
55c79a40 MG	23
	24	#include "clock.h"
	25
	26	#define DA8XX_TPCC_BASE 0x01c00000
3f995f2f	27	#define DA850_TPCC1_BASE 0x01e30000
55c79a40 MG	28	#define DA8XX_TPTC0_BASE 0x01c08000
55c79a40 MG	29	#define DA8XX_TPTC1_BASE 0x01c08400
3f995f2f	30	#define DA850_TPTC2_BASE 0x01e38000
55c79a40 MG	31	#define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
55c79a40 MG	32	#define DA8XX_I2C0_BASE 0x01c22000
c51df70b	33	#define DA8XX_RTC_BASE 0x01C23000
55c79a40 MG	34	#define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000
	35	#define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000
	36	#define DA8XX_EMAC_CPGMAC_BASE 0x01e23000
	37	#define DA8XX_EMAC_MDIO_BASE 0x01e24000
	38	#define DA8XX_GPIO_BASE 0x01e26000
	39	#define DA8XX_I2C1_BASE 0x01e28000
	40
	41	#define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000
	42	#define DA8XX_EMAC_MOD_REG_OFFSET 0x2000
	43	#define DA8XX_EMAC_RAM_OFFSET 0x0000
	44	#define DA8XX_MDIO_REG_OFFSET 0x4000
	45	#define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
	46
d2de0582 SN	47	void __iomem *da8xx_syscfg0_base;
d2de0582 SN	48	void __iomem *da8xx_syscfg1_base;
6a28adef	49
55c79a40 MG	50	static struct plat_serial8250_port da8xx_serial_pdata[] = {
	51	{
	52	.mapbase = DA8XX_UART0_BASE,
	53	.irq = IRQ_DA8XX_UARTINT0,
	54	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST \|
	55	UPF_IOREMAP,
	56	.iotype = UPIO_MEM,
	57	.regshift = 2,
	58	},
	59	{
	60	.mapbase = DA8XX_UART1_BASE,
	61	.irq = IRQ_DA8XX_UARTINT1,
	62	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST \|
	63	UPF_IOREMAP,
	64	.iotype = UPIO_MEM,
	65	.regshift = 2,
	66	},
	67	{
	68	.mapbase = DA8XX_UART2_BASE,
	69	.irq = IRQ_DA8XX_UARTINT2,
	70	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST \|
	71	UPF_IOREMAP,
	72	.iotype = UPIO_MEM,
	73	.regshift = 2,
	74	},
	75	{
	76	.flags = 0,
	77	},
	78	};
	79
	80	struct platform_device da8xx_serial_device = {
	81	.name = "serial8250",
	82	.id = PLAT8250_DEV_PLATFORM,
	83	.dev = {
	84	.platform_data = da8xx_serial_pdata,
	85	},
	86	};
	87
55c79a40 MG	88	static const s8 da8xx_queue_tc_mapping[][2] = {
	89	/* {event queue no, TC no} */
	90	{0, 0},
	91	{1, 1},
	92	{-1, -1}
	93	};
	94
	95	static const s8 da8xx_queue_priority_mapping[][2] = {
	96	/* {event queue no, Priority} */
	97	{0, 3},
	98	{1, 7},
	99	{-1, -1}
	100	};
	101
3f995f2f SR	102	static const s8 da850_queue_tc_mapping[][2] = {
	103	/* {event queue no, TC no} */
	104	{0, 0},
	105	{-1, -1}
	106	};
	107
	108	static const s8 da850_queue_priority_mapping[][2] = {
	109	/* {event queue no, Priority} */
	110	{0, 3},
	111	{-1, -1}
	112	};
	113
bc3ac9f3 SN	114	static struct edma_soc_info da830_edma_cc0_info = {
	115	.n_channel = 32,
	116	.n_region = 4,
	117	.n_slot = 128,
	118	.n_tc = 2,
	119	.n_cc = 1,
	120	.queue_tc_mapping = da8xx_queue_tc_mapping,
	121	.queue_priority_mapping = da8xx_queue_priority_mapping,
	122	};
	123
	124	static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = {
	125	&da830_edma_cc0_info,
55c79a40 MG	126	};
55c79a40 MG	127
bc3ac9f3	128	static struct edma_soc_info da850_edma_cc_info[] = {
3f995f2f SR	129	{
	130	.n_channel = 32,
	131	.n_region = 4,
	132	.n_slot = 128,
	133	.n_tc = 2,
	134	.n_cc = 1,
	135	.queue_tc_mapping = da8xx_queue_tc_mapping,
	136	.queue_priority_mapping = da8xx_queue_priority_mapping,
	137	},
	138	{
	139	.n_channel = 32,
	140	.n_region = 4,
	141	.n_slot = 128,
	142	.n_tc = 1,
	143	.n_cc = 1,
	144	.queue_tc_mapping = da850_queue_tc_mapping,
	145	.queue_priority_mapping = da850_queue_priority_mapping,
	146	},
	147	};
	148
bc3ac9f3 SN	149	static struct edma_soc_info *da850_edma_info[EDMA_MAX_CC] = {
	150	&da850_edma_cc_info[0],
	151	&da850_edma_cc_info[1],
	152	};
	153
3f995f2f	154	static struct resource da830_edma_resources[] = {
55c79a40 MG	155	{
	156	.name = "edma_cc0",
	157	.start = DA8XX_TPCC_BASE,
	158	.end = DA8XX_TPCC_BASE + SZ_32K - 1,
	159	.flags = IORESOURCE_MEM,
	160	},
	161	{
	162	.name = "edma_tc0",
	163	.start = DA8XX_TPTC0_BASE,
	164	.end = DA8XX_TPTC0_BASE + SZ_1K - 1,
	165	.flags = IORESOURCE_MEM,
	166	},
	167	{
	168	.name = "edma_tc1",
	169	.start = DA8XX_TPTC1_BASE,
	170	.end = DA8XX_TPTC1_BASE + SZ_1K - 1,
	171	.flags = IORESOURCE_MEM,
	172	},
	173	{
	174	.name = "edma0",
2259bbd4	175	.start = IRQ_DA8XX_CCINT0,
55c79a40 MG	176	.flags = IORESOURCE_IRQ,
	177	},
	178	{
	179	.name = "edma0_err",
	180	.start = IRQ_DA8XX_CCERRINT,
	181	.flags = IORESOURCE_IRQ,
	182	},
	183	};
	184
3f995f2f SR	185	static struct resource da850_edma_resources[] = {
	186	{
	187	.name = "edma_cc0",
	188	.start = DA8XX_TPCC_BASE,
	189	.end = DA8XX_TPCC_BASE + SZ_32K - 1,
	190	.flags = IORESOURCE_MEM,
	191	},
	192	{
	193	.name = "edma_tc0",
	194	.start = DA8XX_TPTC0_BASE,
	195	.end = DA8XX_TPTC0_BASE + SZ_1K - 1,
	196	.flags = IORESOURCE_MEM,
	197	},
	198	{
	199	.name = "edma_tc1",
	200	.start = DA8XX_TPTC1_BASE,
	201	.end = DA8XX_TPTC1_BASE + SZ_1K - 1,
	202	.flags = IORESOURCE_MEM,
	203	},
	204	{
	205	.name = "edma_cc1",
	206	.start = DA850_TPCC1_BASE,
	207	.end = DA850_TPCC1_BASE + SZ_32K - 1,
	208	.flags = IORESOURCE_MEM,
	209	},
	210	{
	211	.name = "edma_tc2",
	212	.start = DA850_TPTC2_BASE,
	213	.end = DA850_TPTC2_BASE + SZ_1K - 1,
	214	.flags = IORESOURCE_MEM,
	215	},
	216	{
	217	.name = "edma0",
	218	.start = IRQ_DA8XX_CCINT0,
	219	.flags = IORESOURCE_IRQ,
	220	},
	221	{
	222	.name = "edma0_err",
	223	.start = IRQ_DA8XX_CCERRINT,
	224	.flags = IORESOURCE_IRQ,
	225	},
	226	{
	227	.name = "edma1",
	228	.start = IRQ_DA850_CCINT1,
	229	.flags = IORESOURCE_IRQ,
	230	},
	231	{
	232	.name = "edma1_err",
	233	.start = IRQ_DA850_CCERRINT1,
	234	.flags = IORESOURCE_IRQ,
	235	},
	236	};
	237
	238	static struct platform_device da830_edma_device = {
55c79a40 MG	239	.name = "edma",
	240	.id = -1,
	241	.dev = {
3f995f2f	242	.platform_data = da830_edma_info,
55c79a40	243	},
3f995f2f SR	244	.num_resources = ARRAY_SIZE(da830_edma_resources),
	245	.resource = da830_edma_resources,
	246	};
	247
	248	static struct platform_device da850_edma_device = {
	249	.name = "edma",
	250	.id = -1,
	251	.dev = {
	252	.platform_data = da850_edma_info,
	253	},
	254	.num_resources = ARRAY_SIZE(da850_edma_resources),
	255	.resource = da850_edma_resources,
55c79a40 MG	256	};
	257
	258	int __init da8xx_register_edma(void)
	259	{
3f995f2f SR	260	struct platform_device *pdev;
	261
	262	if (cpu_is_davinci_da830())
	263	pdev = &da830_edma_device;
	264	else if (cpu_is_davinci_da850())
	265	pdev = &da850_edma_device;
	266	else
	267	return -ENODEV;
	268
	269	return platform_device_register(pdev);
55c79a40 MG	270	}
	271
	272	static struct resource da8xx_i2c_resources0[] = {
	273	{
	274	.start = DA8XX_I2C0_BASE,
	275	.end = DA8XX_I2C0_BASE + SZ_4K - 1,
	276	.flags = IORESOURCE_MEM,
	277	},
	278	{
	279	.start = IRQ_DA8XX_I2CINT0,
	280	.end = IRQ_DA8XX_I2CINT0,
	281	.flags = IORESOURCE_IRQ,
	282	},
	283	};
	284
	285	static struct platform_device da8xx_i2c_device0 = {
	286	.name = "i2c_davinci",
	287	.id = 1,
	288	.num_resources = ARRAY_SIZE(da8xx_i2c_resources0),
	289	.resource = da8xx_i2c_resources0,
	290	};
	291
	292	static struct resource da8xx_i2c_resources1[] = {
	293	{
	294	.start = DA8XX_I2C1_BASE,
	295	.end = DA8XX_I2C1_BASE + SZ_4K - 1,
	296	.flags = IORESOURCE_MEM,
	297	},
	298	{
	299	.start = IRQ_DA8XX_I2CINT1,
	300	.end = IRQ_DA8XX_I2CINT1,
	301	.flags = IORESOURCE_IRQ,
	302	},
	303	};
	304
	305	static struct platform_device da8xx_i2c_device1 = {
	306	.name = "i2c_davinci",
	307	.id = 2,
	308	.num_resources = ARRAY_SIZE(da8xx_i2c_resources1),
	309	.resource = da8xx_i2c_resources1,
	310	};
	311
	312	int __init da8xx_register_i2c(int instance,
	313	struct davinci_i2c_platform_data *pdata)
	314	{
	315	struct platform_device *pdev;
	316
	317	if (instance == 0)
	318	pdev = &da8xx_i2c_device0;
	319	else if (instance == 1)
	320	pdev = &da8xx_i2c_device1;
	321	else
	322	return -EINVAL;
	323
	324	pdev->dev.platform_data = pdata;
	325	return platform_device_register(pdev);
	326	}
	327
	328	static struct resource da8xx_watchdog_resources[] = {
	329	{
	330	.start = DA8XX_WDOG_BASE,
	331	.end = DA8XX_WDOG_BASE + SZ_4K - 1,
	332	.flags = IORESOURCE_MEM,
	333	},
334	};
335
c78a5bc2	336	struct platform_device da8xx_wdt_device = {
55c79a40 MG	337	.name = "watchdog",
	338	.id = -1,
	339	.num_resources = ARRAY_SIZE(da8xx_watchdog_resources),
	340	.resource = da8xx_watchdog_resources,
	341	};
	342
	343	int __init da8xx_register_watchdog(void)
	344	{
c78a5bc2	345	return platform_device_register(&da8xx_wdt_device);
55c79a40 MG	346	}
	347
	348	static struct resource da8xx_emac_resources[] = {
	349	{
	350	.start = DA8XX_EMAC_CPPI_PORT_BASE,
	351	.end = DA8XX_EMAC_CPPI_PORT_BASE + 0x5000 - 1,
	352	.flags = IORESOURCE_MEM,
	353	},
	354	{
	355	.start = IRQ_DA8XX_C0_RX_THRESH_PULSE,
	356	.end = IRQ_DA8XX_C0_RX_THRESH_PULSE,
	357	.flags = IORESOURCE_IRQ,
	358	},
	359	{
	360	.start = IRQ_DA8XX_C0_RX_PULSE,
	361	.end = IRQ_DA8XX_C0_RX_PULSE,
	362	.flags = IORESOURCE_IRQ,
	363	},
	364	{
	365	.start = IRQ_DA8XX_C0_TX_PULSE,
	366	.end = IRQ_DA8XX_C0_TX_PULSE,
	367	.flags = IORESOURCE_IRQ,
	368	},
	369	{
	370	.start = IRQ_DA8XX_C0_MISC_PULSE,
	371	.end = IRQ_DA8XX_C0_MISC_PULSE,
	372	.flags = IORESOURCE_IRQ,
	373	},
	374	};
	375
	376	struct emac_platform_data da8xx_emac_pdata = {
	377	.ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET,
	378	.ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET,
	379	.ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET,
	380	.mdio_reg_offset = DA8XX_MDIO_REG_OFFSET,
	381	.ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE,
	382	.version = EMAC_VERSION_2,
	383	};
	384
	385	static struct platform_device da8xx_emac_device = {
	386	.name = "davinci_emac",
	387	.id = 1,
	388	.dev = {
	389	.platform_data = &da8xx_emac_pdata,
	390	},
	391	.num_resources = ARRAY_SIZE(da8xx_emac_resources),
	392	.resource = da8xx_emac_resources,
	393	};
	394
31f53cf3 MG	395	int __init da8xx_register_emac(void)
	396	{
	397	return platform_device_register(&da8xx_emac_device);
	398	}
	399
e33ef5e3 C	400	static struct resource da830_mcasp1_resources[] = {
	401	{
	402	.name = "mcasp1",
	403	.start = DAVINCI_DA830_MCASP1_REG_BASE,
	404	.end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
	405	.flags = IORESOURCE_MEM,
	406	},
	407	/* TX event */
	408	{
	409	.start = DAVINCI_DA830_DMA_MCASP1_AXEVT,
	410	.end = DAVINCI_DA830_DMA_MCASP1_AXEVT,
	411	.flags = IORESOURCE_DMA,
	412	},
	413	/* RX event */
	414	{
	415	.start = DAVINCI_DA830_DMA_MCASP1_AREVT,
	416	.end = DAVINCI_DA830_DMA_MCASP1_AREVT,
	417	.flags = IORESOURCE_DMA,
	418	},
	419	};
	420
	421	static struct platform_device da830_mcasp1_device = {
	422	.name = "davinci-mcasp",
	423	.id = 1,
	424	.num_resources = ARRAY_SIZE(da830_mcasp1_resources),
	425	.resource = da830_mcasp1_resources,
	426	};
	427
491214e1 C	428	static struct resource da850_mcasp_resources[] = {
	429	{
	430	.name = "mcasp",
	431	.start = DAVINCI_DA8XX_MCASP0_REG_BASE,
	432	.end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
	433	.flags = IORESOURCE_MEM,
	434	},
	435	/* TX event */
	436	{
	437	.start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
	438	.end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
	439	.flags = IORESOURCE_DMA,
	440	},
	441	/* RX event */
	442	{
	443	.start = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
	444	.end = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
	445	.flags = IORESOURCE_DMA,
	446	},
	447	};
	448
	449	static struct platform_device da850_mcasp_device = {
	450	.name = "davinci-mcasp",
	451	.id = 0,
	452	.num_resources = ARRAY_SIZE(da850_mcasp_resources),
	453	.resource = da850_mcasp_resources,
	454	};
	455
b8864aa4	456	void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
e33ef5e3	457	{
491214e1 C	458	/* DA830/OMAP-L137 has 3 instances of McASP */
491214e1 C	459	if (cpu_is_davinci_da830() && id == 1) {
e33ef5e3 C	460	da830_mcasp1_device.dev.platform_data = pdata;
e33ef5e3 C	461	platform_device_register(&da830_mcasp1_device);
491214e1 C	462	} else if (cpu_is_davinci_da850()) {
	463	da850_mcasp_device.dev.platform_data = pdata;
	464	platform_device_register(&da850_mcasp_device);
e33ef5e3 C	465	}
e33ef5e3 C	466	}
5cbdf276 SR	467
	468	static const struct display_panel disp_panel = {
	469	QVGA,
	470	16,
	471	16,
	472	COLOR_ACTIVE,
	473	};
	474
	475	static struct lcd_ctrl_config lcd_cfg = {
	476	&disp_panel,
	477	.ac_bias = 255,
	478	.ac_bias_intrpt = 0,
	479	.dma_burst_sz = 16,
	480	.bpp = 16,
	481	.fdd = 255,
	482	.tft_alt_mode = 0,
	483	.stn_565_mode = 0,
	484	.mono_8bit_mode = 0,
	485	.invert_line_clock = 1,
	486	.invert_frm_clock = 1,
	487	.sync_edge = 0,
	488	.sync_ctrl = 1,
	489	.raster_order = 0,
	490	};
	491
b9e6342b MG	492	struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
	493	.manu_name = "sharp",
	494	.controller_data = &lcd_cfg,
	495	.type = "Sharp_LCD035Q3DG01",
	496	};
	497
	498	struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
	499	.manu_name = "sharp",
	500	.controller_data = &lcd_cfg,
	501	.type = "Sharp_LK043T1DG01",
5cbdf276 SR	502	};
	503
	504	static struct resource da8xx_lcdc_resources[] = {
	505	[0] = { /* registers */
	506	.start = DA8XX_LCD_CNTRL_BASE,
	507	.end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
	508	.flags = IORESOURCE_MEM,
	509	},
	510	[1] = { /* interrupt */
	511	.start = IRQ_DA8XX_LCDINT,
	512	.end = IRQ_DA8XX_LCDINT,
	513	.flags = IORESOURCE_IRQ,
	514	},
	515	};
	516
b9e6342b	517	static struct platform_device da8xx_lcdc_device = {
5cbdf276 SR	518	.name = "da8xx_lcdc",
	519	.id = 0,
	520	.num_resources = ARRAY_SIZE(da8xx_lcdc_resources),
	521	.resource = da8xx_lcdc_resources,
5cbdf276 SR	522	};
5cbdf276 SR	523
b9e6342b	524	int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
5cbdf276	525	{
b9e6342b MG	526	da8xx_lcdc_device.dev.platform_data = pdata;
b9e6342b MG	527	return platform_device_register(&da8xx_lcdc_device);
5cbdf276	528	}
700691f2 SR	529
	530	static struct resource da8xx_mmcsd0_resources[] = {
	531	{ /* registers */
	532	.start = DA8XX_MMCSD0_BASE,
	533	.end = DA8XX_MMCSD0_BASE + SZ_4K - 1,
	534	.flags = IORESOURCE_MEM,
	535	},
	536	{ /* interrupt */
	537	.start = IRQ_DA8XX_MMCSDINT0,
	538	.end = IRQ_DA8XX_MMCSDINT0,
	539	.flags = IORESOURCE_IRQ,
	540	},
	541	{ /* DMA RX */
	542	.start = EDMA_CTLR_CHAN(0, 16),
	543	.end = EDMA_CTLR_CHAN(0, 16),
	544	.flags = IORESOURCE_DMA,
	545	},
	546	{ /* DMA TX */
	547	.start = EDMA_CTLR_CHAN(0, 17),
	548	.end = EDMA_CTLR_CHAN(0, 17),
	549	.flags = IORESOURCE_DMA,
	550	},
	551	};
	552
	553	static struct platform_device da8xx_mmcsd0_device = {
	554	.name = "davinci_mmc",
	555	.id = 0,
	556	.num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources),
	557	.resource = da8xx_mmcsd0_resources,
	558	};
	559
	560	int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
	561	{
	562	da8xx_mmcsd0_device.dev.platform_data = config;
	563	return platform_device_register(&da8xx_mmcsd0_device);
	564	}
c51df70b MG	565
	566	static struct resource da8xx_rtc_resources[] = {
	567	{
	568	.start = DA8XX_RTC_BASE,
	569	.end = DA8XX_RTC_BASE + SZ_4K - 1,
	570	.flags = IORESOURCE_MEM,
	571	},
	572	{ /* timer irq */
	573	.start = IRQ_DA8XX_RTC,
	574	.end = IRQ_DA8XX_RTC,
	575	.flags = IORESOURCE_IRQ,
	576	},
	577	{ /* alarm irq */
	578	.start = IRQ_DA8XX_RTC,
	579	.end = IRQ_DA8XX_RTC,
	580	.flags = IORESOURCE_IRQ,
	581	},
	582	};
	583
	584	static struct platform_device da8xx_rtc_device = {
	585	.name = "omap_rtc",
	586	.id = -1,
	587	.num_resources = ARRAY_SIZE(da8xx_rtc_resources),
	588	.resource = da8xx_rtc_resources,
	589	};
	590
	591	int da8xx_register_rtc(void)
	592	{
75c99bb0	593	int ret;
db6db5d8 CC	594	void __iomem *base;
	595
	596	base = ioremap(DA8XX_RTC_BASE, SZ_4K);
	597	if (WARN_ON(!base))
	598	return -ENOMEM;
75c99bb0	599
c51df70b	600	/* Unlock the rtc's registers */
db6db5d8 CC	601	__raw_writel(0x83e70b13, base + 0x6c);
	602	__raw_writel(0x95a4f1e0, base + 0x70);
	603
	604	iounmap(base);
c51df70b	605
75c99bb0 SN	606	ret = platform_device_register(&da8xx_rtc_device);
	607	if (!ret)
	608	/* Atleast on DA850, RTC is a wakeup source */
	609	device_init_wakeup(&da8xx_rtc_device.dev, true);
	610
	611	return ret;
c51df70b	612	}
1960e693	613
948c66df SN	614	static void __iomem *da8xx_ddr2_ctlr_base;
	615	void __iomem * __init da8xx_get_mem_ctlr(void)
	616	{
	617	if (da8xx_ddr2_ctlr_base)
	618	return da8xx_ddr2_ctlr_base;
	619
	620	da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
	621	if (!da8xx_ddr2_ctlr_base)
	622	pr_warning("%s: Unable to map DDR2 controller", __func__);
	623
	624	return da8xx_ddr2_ctlr_base;
	625	}
	626
1960e693 SN	627	static struct resource da8xx_cpuidle_resources[] = {
	628	{
	629	.start = DA8XX_DDR2_CTL_BASE,
	630	.end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
	631	.flags = IORESOURCE_MEM,
	632	},
	633	};
	634
	635	/* DA8XX devices support DDR2 power down */
	636	static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
	637	.ddr2_pdown = 1,
	638	};
	639
	640
	641	static struct platform_device da8xx_cpuidle_device = {
	642	.name = "cpuidle-davinci",
	643	.num_resources = ARRAY_SIZE(da8xx_cpuidle_resources),
	644	.resource = da8xx_cpuidle_resources,
	645	.dev = {
	646	.platform_data = &da8xx_cpuidle_pdata,
	647	},
	648	};
	649
	650	int __init da8xx_register_cpuidle(void)
	651	{
948c66df SN	652	da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
948c66df SN	653
1960e693 SN	654	return platform_device_register(&da8xx_cpuidle_device);
1960e693 SN	655	}