Commit | Line | Data |
---|---|---|
55c79a40 MG |
1 | /* |
2 | * DA8XX/OMAP L1XX platform device data | |
3 | * | |
4 | * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com> | |
5 | * Derived from code that was: | |
6 | * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
13 | #include <linux/module.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/dma-mapping.h> | |
18 | #include <linux/serial_8250.h> | |
19 | ||
20 | #include <mach/cputype.h> | |
21 | #include <mach/common.h> | |
22 | #include <mach/time.h> | |
23 | #include <mach/da8xx.h> | |
24 | ||
25 | #include "clock.h" | |
26 | ||
27 | #define DA8XX_TPCC_BASE 0x01c00000 | |
28 | #define DA8XX_TPTC0_BASE 0x01c08000 | |
29 | #define DA8XX_TPTC1_BASE 0x01c08400 | |
30 | #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */ | |
31 | #define DA8XX_I2C0_BASE 0x01c22000 | |
32 | #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000 | |
33 | #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000 | |
34 | #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000 | |
35 | #define DA8XX_EMAC_MDIO_BASE 0x01e24000 | |
36 | #define DA8XX_GPIO_BASE 0x01e26000 | |
37 | #define DA8XX_I2C1_BASE 0x01e28000 | |
38 | ||
39 | #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000 | |
40 | #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000 | |
41 | #define DA8XX_EMAC_RAM_OFFSET 0x0000 | |
42 | #define DA8XX_MDIO_REG_OFFSET 0x4000 | |
43 | #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K | |
44 | ||
45 | static struct plat_serial8250_port da8xx_serial_pdata[] = { | |
46 | { | |
47 | .mapbase = DA8XX_UART0_BASE, | |
48 | .irq = IRQ_DA8XX_UARTINT0, | |
49 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | |
50 | UPF_IOREMAP, | |
51 | .iotype = UPIO_MEM, | |
52 | .regshift = 2, | |
53 | }, | |
54 | { | |
55 | .mapbase = DA8XX_UART1_BASE, | |
56 | .irq = IRQ_DA8XX_UARTINT1, | |
57 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | |
58 | UPF_IOREMAP, | |
59 | .iotype = UPIO_MEM, | |
60 | .regshift = 2, | |
61 | }, | |
62 | { | |
63 | .mapbase = DA8XX_UART2_BASE, | |
64 | .irq = IRQ_DA8XX_UARTINT2, | |
65 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | |
66 | UPF_IOREMAP, | |
67 | .iotype = UPIO_MEM, | |
68 | .regshift = 2, | |
69 | }, | |
70 | { | |
71 | .flags = 0, | |
72 | }, | |
73 | }; | |
74 | ||
75 | struct platform_device da8xx_serial_device = { | |
76 | .name = "serial8250", | |
77 | .id = PLAT8250_DEV_PLATFORM, | |
78 | .dev = { | |
79 | .platform_data = da8xx_serial_pdata, | |
80 | }, | |
81 | }; | |
82 | ||
83 | static const s8 da8xx_dma_chan_no_event[] = { | |
84 | 20, 21, | |
85 | -1 | |
86 | }; | |
87 | ||
88 | static const s8 da8xx_queue_tc_mapping[][2] = { | |
89 | /* {event queue no, TC no} */ | |
90 | {0, 0}, | |
91 | {1, 1}, | |
92 | {-1, -1} | |
93 | }; | |
94 | ||
95 | static const s8 da8xx_queue_priority_mapping[][2] = { | |
96 | /* {event queue no, Priority} */ | |
97 | {0, 3}, | |
98 | {1, 7}, | |
99 | {-1, -1} | |
100 | }; | |
101 | ||
102 | static struct edma_soc_info da8xx_edma_info[] = { | |
103 | { | |
104 | .n_channel = 32, | |
105 | .n_region = 4, | |
106 | .n_slot = 128, | |
107 | .n_tc = 2, | |
108 | .n_cc = 1, | |
109 | .noevent = da8xx_dma_chan_no_event, | |
110 | .queue_tc_mapping = da8xx_queue_tc_mapping, | |
111 | .queue_priority_mapping = da8xx_queue_priority_mapping, | |
112 | }, | |
113 | }; | |
114 | ||
115 | static struct resource da8xx_edma_resources[] = { | |
116 | { | |
117 | .name = "edma_cc0", | |
118 | .start = DA8XX_TPCC_BASE, | |
119 | .end = DA8XX_TPCC_BASE + SZ_32K - 1, | |
120 | .flags = IORESOURCE_MEM, | |
121 | }, | |
122 | { | |
123 | .name = "edma_tc0", | |
124 | .start = DA8XX_TPTC0_BASE, | |
125 | .end = DA8XX_TPTC0_BASE + SZ_1K - 1, | |
126 | .flags = IORESOURCE_MEM, | |
127 | }, | |
128 | { | |
129 | .name = "edma_tc1", | |
130 | .start = DA8XX_TPTC1_BASE, | |
131 | .end = DA8XX_TPTC1_BASE + SZ_1K - 1, | |
132 | .flags = IORESOURCE_MEM, | |
133 | }, | |
134 | { | |
135 | .name = "edma0", | |
2259bbd4 | 136 | .start = IRQ_DA8XX_CCINT0, |
55c79a40 MG |
137 | .flags = IORESOURCE_IRQ, |
138 | }, | |
139 | { | |
140 | .name = "edma0_err", | |
141 | .start = IRQ_DA8XX_CCERRINT, | |
142 | .flags = IORESOURCE_IRQ, | |
143 | }, | |
144 | }; | |
145 | ||
146 | static struct platform_device da8xx_edma_device = { | |
147 | .name = "edma", | |
148 | .id = -1, | |
149 | .dev = { | |
150 | .platform_data = da8xx_edma_info, | |
151 | }, | |
152 | .num_resources = ARRAY_SIZE(da8xx_edma_resources), | |
153 | .resource = da8xx_edma_resources, | |
154 | }; | |
155 | ||
156 | int __init da8xx_register_edma(void) | |
157 | { | |
158 | return platform_device_register(&da8xx_edma_device); | |
159 | } | |
160 | ||
161 | static struct resource da8xx_i2c_resources0[] = { | |
162 | { | |
163 | .start = DA8XX_I2C0_BASE, | |
164 | .end = DA8XX_I2C0_BASE + SZ_4K - 1, | |
165 | .flags = IORESOURCE_MEM, | |
166 | }, | |
167 | { | |
168 | .start = IRQ_DA8XX_I2CINT0, | |
169 | .end = IRQ_DA8XX_I2CINT0, | |
170 | .flags = IORESOURCE_IRQ, | |
171 | }, | |
172 | }; | |
173 | ||
174 | static struct platform_device da8xx_i2c_device0 = { | |
175 | .name = "i2c_davinci", | |
176 | .id = 1, | |
177 | .num_resources = ARRAY_SIZE(da8xx_i2c_resources0), | |
178 | .resource = da8xx_i2c_resources0, | |
179 | }; | |
180 | ||
181 | static struct resource da8xx_i2c_resources1[] = { | |
182 | { | |
183 | .start = DA8XX_I2C1_BASE, | |
184 | .end = DA8XX_I2C1_BASE + SZ_4K - 1, | |
185 | .flags = IORESOURCE_MEM, | |
186 | }, | |
187 | { | |
188 | .start = IRQ_DA8XX_I2CINT1, | |
189 | .end = IRQ_DA8XX_I2CINT1, | |
190 | .flags = IORESOURCE_IRQ, | |
191 | }, | |
192 | }; | |
193 | ||
194 | static struct platform_device da8xx_i2c_device1 = { | |
195 | .name = "i2c_davinci", | |
196 | .id = 2, | |
197 | .num_resources = ARRAY_SIZE(da8xx_i2c_resources1), | |
198 | .resource = da8xx_i2c_resources1, | |
199 | }; | |
200 | ||
201 | int __init da8xx_register_i2c(int instance, | |
202 | struct davinci_i2c_platform_data *pdata) | |
203 | { | |
204 | struct platform_device *pdev; | |
205 | ||
206 | if (instance == 0) | |
207 | pdev = &da8xx_i2c_device0; | |
208 | else if (instance == 1) | |
209 | pdev = &da8xx_i2c_device1; | |
210 | else | |
211 | return -EINVAL; | |
212 | ||
213 | pdev->dev.platform_data = pdata; | |
214 | return platform_device_register(pdev); | |
215 | } | |
216 | ||
217 | static struct resource da8xx_watchdog_resources[] = { | |
218 | { | |
219 | .start = DA8XX_WDOG_BASE, | |
220 | .end = DA8XX_WDOG_BASE + SZ_4K - 1, | |
221 | .flags = IORESOURCE_MEM, | |
222 | }, | |
223 | }; | |
224 | ||
225 | struct platform_device davinci_wdt_device = { | |
226 | .name = "watchdog", | |
227 | .id = -1, | |
228 | .num_resources = ARRAY_SIZE(da8xx_watchdog_resources), | |
229 | .resource = da8xx_watchdog_resources, | |
230 | }; | |
231 | ||
232 | int __init da8xx_register_watchdog(void) | |
233 | { | |
234 | return platform_device_register(&davinci_wdt_device); | |
235 | } | |
236 | ||
237 | static struct resource da8xx_emac_resources[] = { | |
238 | { | |
239 | .start = DA8XX_EMAC_CPPI_PORT_BASE, | |
240 | .end = DA8XX_EMAC_CPPI_PORT_BASE + 0x5000 - 1, | |
241 | .flags = IORESOURCE_MEM, | |
242 | }, | |
243 | { | |
244 | .start = IRQ_DA8XX_C0_RX_THRESH_PULSE, | |
245 | .end = IRQ_DA8XX_C0_RX_THRESH_PULSE, | |
246 | .flags = IORESOURCE_IRQ, | |
247 | }, | |
248 | { | |
249 | .start = IRQ_DA8XX_C0_RX_PULSE, | |
250 | .end = IRQ_DA8XX_C0_RX_PULSE, | |
251 | .flags = IORESOURCE_IRQ, | |
252 | }, | |
253 | { | |
254 | .start = IRQ_DA8XX_C0_TX_PULSE, | |
255 | .end = IRQ_DA8XX_C0_TX_PULSE, | |
256 | .flags = IORESOURCE_IRQ, | |
257 | }, | |
258 | { | |
259 | .start = IRQ_DA8XX_C0_MISC_PULSE, | |
260 | .end = IRQ_DA8XX_C0_MISC_PULSE, | |
261 | .flags = IORESOURCE_IRQ, | |
262 | }, | |
263 | }; | |
264 | ||
265 | struct emac_platform_data da8xx_emac_pdata = { | |
266 | .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET, | |
267 | .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET, | |
268 | .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET, | |
269 | .mdio_reg_offset = DA8XX_MDIO_REG_OFFSET, | |
270 | .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE, | |
271 | .version = EMAC_VERSION_2, | |
272 | }; | |
273 | ||
274 | static struct platform_device da8xx_emac_device = { | |
275 | .name = "davinci_emac", | |
276 | .id = 1, | |
277 | .dev = { | |
278 | .platform_data = &da8xx_emac_pdata, | |
279 | }, | |
280 | .num_resources = ARRAY_SIZE(da8xx_emac_resources), | |
281 | .resource = da8xx_emac_resources, | |
282 | }; | |
283 | ||
e33ef5e3 C |
284 | static struct resource da830_mcasp1_resources[] = { |
285 | { | |
286 | .name = "mcasp1", | |
287 | .start = DAVINCI_DA830_MCASP1_REG_BASE, | |
288 | .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1, | |
289 | .flags = IORESOURCE_MEM, | |
290 | }, | |
291 | /* TX event */ | |
292 | { | |
293 | .start = DAVINCI_DA830_DMA_MCASP1_AXEVT, | |
294 | .end = DAVINCI_DA830_DMA_MCASP1_AXEVT, | |
295 | .flags = IORESOURCE_DMA, | |
296 | }, | |
297 | /* RX event */ | |
298 | { | |
299 | .start = DAVINCI_DA830_DMA_MCASP1_AREVT, | |
300 | .end = DAVINCI_DA830_DMA_MCASP1_AREVT, | |
301 | .flags = IORESOURCE_DMA, | |
302 | }, | |
303 | }; | |
304 | ||
305 | static struct platform_device da830_mcasp1_device = { | |
306 | .name = "davinci-mcasp", | |
307 | .id = 1, | |
308 | .num_resources = ARRAY_SIZE(da830_mcasp1_resources), | |
309 | .resource = da830_mcasp1_resources, | |
310 | }; | |
311 | ||
491214e1 C |
312 | static struct resource da850_mcasp_resources[] = { |
313 | { | |
314 | .name = "mcasp", | |
315 | .start = DAVINCI_DA8XX_MCASP0_REG_BASE, | |
316 | .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1, | |
317 | .flags = IORESOURCE_MEM, | |
318 | }, | |
319 | /* TX event */ | |
320 | { | |
321 | .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, | |
322 | .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, | |
323 | .flags = IORESOURCE_DMA, | |
324 | }, | |
325 | /* RX event */ | |
326 | { | |
327 | .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT, | |
328 | .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT, | |
329 | .flags = IORESOURCE_DMA, | |
330 | }, | |
331 | }; | |
332 | ||
333 | static struct platform_device da850_mcasp_device = { | |
334 | .name = "davinci-mcasp", | |
335 | .id = 0, | |
336 | .num_resources = ARRAY_SIZE(da850_mcasp_resources), | |
337 | .resource = da850_mcasp_resources, | |
338 | }; | |
339 | ||
55c79a40 MG |
340 | int __init da8xx_register_emac(void) |
341 | { | |
342 | return platform_device_register(&da8xx_emac_device); | |
343 | } | |
e33ef5e3 C |
344 | |
345 | void __init da8xx_init_mcasp(int id, struct snd_platform_data *pdata) | |
346 | { | |
491214e1 C |
347 | /* DA830/OMAP-L137 has 3 instances of McASP */ |
348 | if (cpu_is_davinci_da830() && id == 1) { | |
e33ef5e3 C |
349 | da830_mcasp1_device.dev.platform_data = pdata; |
350 | platform_device_register(&da830_mcasp1_device); | |
491214e1 C |
351 | } else if (cpu_is_davinci_da850()) { |
352 | da850_mcasp_device.dev.platform_data = pdata; | |
353 | platform_device_register(&da850_mcasp_device); | |
e33ef5e3 C |
354 | } |
355 | } |