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55c79a40 MG |
1 | /* |
2 | * DA8XX/OMAP L1XX platform device data | |
3 | * | |
4 | * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com> | |
5 | * Derived from code that was: | |
6 | * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
55c79a40 MG |
13 | #include <linux/init.h> |
14 | #include <linux/platform_device.h> | |
15 | #include <linux/dma-mapping.h> | |
16 | #include <linux/serial_8250.h> | |
17 | ||
18 | #include <mach/cputype.h> | |
19 | #include <mach/common.h> | |
20 | #include <mach/time.h> | |
21 | #include <mach/da8xx.h> | |
1960e693 | 22 | #include <mach/cpuidle.h> |
55c79a40 MG |
23 | |
24 | #include "clock.h" | |
25 | ||
26 | #define DA8XX_TPCC_BASE 0x01c00000 | |
27 | #define DA8XX_TPTC0_BASE 0x01c08000 | |
28 | #define DA8XX_TPTC1_BASE 0x01c08400 | |
29 | #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */ | |
30 | #define DA8XX_I2C0_BASE 0x01c22000 | |
c51df70b | 31 | #define DA8XX_RTC_BASE 0x01C23000 |
55c79a40 MG |
32 | #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000 |
33 | #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000 | |
34 | #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000 | |
35 | #define DA8XX_EMAC_MDIO_BASE 0x01e24000 | |
36 | #define DA8XX_GPIO_BASE 0x01e26000 | |
37 | #define DA8XX_I2C1_BASE 0x01e28000 | |
38 | ||
39 | #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000 | |
40 | #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000 | |
41 | #define DA8XX_EMAC_RAM_OFFSET 0x0000 | |
42 | #define DA8XX_MDIO_REG_OFFSET 0x4000 | |
43 | #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K | |
44 | ||
d2de0582 SN |
45 | void __iomem *da8xx_syscfg0_base; |
46 | void __iomem *da8xx_syscfg1_base; | |
6a28adef | 47 | |
55c79a40 MG |
48 | static struct plat_serial8250_port da8xx_serial_pdata[] = { |
49 | { | |
50 | .mapbase = DA8XX_UART0_BASE, | |
51 | .irq = IRQ_DA8XX_UARTINT0, | |
52 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | |
53 | UPF_IOREMAP, | |
54 | .iotype = UPIO_MEM, | |
55 | .regshift = 2, | |
56 | }, | |
57 | { | |
58 | .mapbase = DA8XX_UART1_BASE, | |
59 | .irq = IRQ_DA8XX_UARTINT1, | |
60 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | |
61 | UPF_IOREMAP, | |
62 | .iotype = UPIO_MEM, | |
63 | .regshift = 2, | |
64 | }, | |
65 | { | |
66 | .mapbase = DA8XX_UART2_BASE, | |
67 | .irq = IRQ_DA8XX_UARTINT2, | |
68 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | |
69 | UPF_IOREMAP, | |
70 | .iotype = UPIO_MEM, | |
71 | .regshift = 2, | |
72 | }, | |
73 | { | |
74 | .flags = 0, | |
75 | }, | |
76 | }; | |
77 | ||
78 | struct platform_device da8xx_serial_device = { | |
79 | .name = "serial8250", | |
80 | .id = PLAT8250_DEV_PLATFORM, | |
81 | .dev = { | |
82 | .platform_data = da8xx_serial_pdata, | |
83 | }, | |
84 | }; | |
85 | ||
86 | static const s8 da8xx_dma_chan_no_event[] = { | |
87 | 20, 21, | |
88 | -1 | |
89 | }; | |
90 | ||
91 | static const s8 da8xx_queue_tc_mapping[][2] = { | |
92 | /* {event queue no, TC no} */ | |
93 | {0, 0}, | |
94 | {1, 1}, | |
95 | {-1, -1} | |
96 | }; | |
97 | ||
98 | static const s8 da8xx_queue_priority_mapping[][2] = { | |
99 | /* {event queue no, Priority} */ | |
100 | {0, 3}, | |
101 | {1, 7}, | |
102 | {-1, -1} | |
103 | }; | |
104 | ||
105 | static struct edma_soc_info da8xx_edma_info[] = { | |
106 | { | |
107 | .n_channel = 32, | |
108 | .n_region = 4, | |
109 | .n_slot = 128, | |
110 | .n_tc = 2, | |
111 | .n_cc = 1, | |
112 | .noevent = da8xx_dma_chan_no_event, | |
113 | .queue_tc_mapping = da8xx_queue_tc_mapping, | |
114 | .queue_priority_mapping = da8xx_queue_priority_mapping, | |
115 | }, | |
116 | }; | |
117 | ||
118 | static struct resource da8xx_edma_resources[] = { | |
119 | { | |
120 | .name = "edma_cc0", | |
121 | .start = DA8XX_TPCC_BASE, | |
122 | .end = DA8XX_TPCC_BASE + SZ_32K - 1, | |
123 | .flags = IORESOURCE_MEM, | |
124 | }, | |
125 | { | |
126 | .name = "edma_tc0", | |
127 | .start = DA8XX_TPTC0_BASE, | |
128 | .end = DA8XX_TPTC0_BASE + SZ_1K - 1, | |
129 | .flags = IORESOURCE_MEM, | |
130 | }, | |
131 | { | |
132 | .name = "edma_tc1", | |
133 | .start = DA8XX_TPTC1_BASE, | |
134 | .end = DA8XX_TPTC1_BASE + SZ_1K - 1, | |
135 | .flags = IORESOURCE_MEM, | |
136 | }, | |
137 | { | |
138 | .name = "edma0", | |
2259bbd4 | 139 | .start = IRQ_DA8XX_CCINT0, |
55c79a40 MG |
140 | .flags = IORESOURCE_IRQ, |
141 | }, | |
142 | { | |
143 | .name = "edma0_err", | |
144 | .start = IRQ_DA8XX_CCERRINT, | |
145 | .flags = IORESOURCE_IRQ, | |
146 | }, | |
147 | }; | |
148 | ||
149 | static struct platform_device da8xx_edma_device = { | |
150 | .name = "edma", | |
151 | .id = -1, | |
152 | .dev = { | |
153 | .platform_data = da8xx_edma_info, | |
154 | }, | |
155 | .num_resources = ARRAY_SIZE(da8xx_edma_resources), | |
156 | .resource = da8xx_edma_resources, | |
157 | }; | |
158 | ||
159 | int __init da8xx_register_edma(void) | |
160 | { | |
161 | return platform_device_register(&da8xx_edma_device); | |
162 | } | |
163 | ||
164 | static struct resource da8xx_i2c_resources0[] = { | |
165 | { | |
166 | .start = DA8XX_I2C0_BASE, | |
167 | .end = DA8XX_I2C0_BASE + SZ_4K - 1, | |
168 | .flags = IORESOURCE_MEM, | |
169 | }, | |
170 | { | |
171 | .start = IRQ_DA8XX_I2CINT0, | |
172 | .end = IRQ_DA8XX_I2CINT0, | |
173 | .flags = IORESOURCE_IRQ, | |
174 | }, | |
175 | }; | |
176 | ||
177 | static struct platform_device da8xx_i2c_device0 = { | |
178 | .name = "i2c_davinci", | |
179 | .id = 1, | |
180 | .num_resources = ARRAY_SIZE(da8xx_i2c_resources0), | |
181 | .resource = da8xx_i2c_resources0, | |
182 | }; | |
183 | ||
184 | static struct resource da8xx_i2c_resources1[] = { | |
185 | { | |
186 | .start = DA8XX_I2C1_BASE, | |
187 | .end = DA8XX_I2C1_BASE + SZ_4K - 1, | |
188 | .flags = IORESOURCE_MEM, | |
189 | }, | |
190 | { | |
191 | .start = IRQ_DA8XX_I2CINT1, | |
192 | .end = IRQ_DA8XX_I2CINT1, | |
193 | .flags = IORESOURCE_IRQ, | |
194 | }, | |
195 | }; | |
196 | ||
197 | static struct platform_device da8xx_i2c_device1 = { | |
198 | .name = "i2c_davinci", | |
199 | .id = 2, | |
200 | .num_resources = ARRAY_SIZE(da8xx_i2c_resources1), | |
201 | .resource = da8xx_i2c_resources1, | |
202 | }; | |
203 | ||
204 | int __init da8xx_register_i2c(int instance, | |
205 | struct davinci_i2c_platform_data *pdata) | |
206 | { | |
207 | struct platform_device *pdev; | |
208 | ||
209 | if (instance == 0) | |
210 | pdev = &da8xx_i2c_device0; | |
211 | else if (instance == 1) | |
212 | pdev = &da8xx_i2c_device1; | |
213 | else | |
214 | return -EINVAL; | |
215 | ||
216 | pdev->dev.platform_data = pdata; | |
217 | return platform_device_register(pdev); | |
218 | } | |
219 | ||
220 | static struct resource da8xx_watchdog_resources[] = { | |
221 | { | |
222 | .start = DA8XX_WDOG_BASE, | |
223 | .end = DA8XX_WDOG_BASE + SZ_4K - 1, | |
224 | .flags = IORESOURCE_MEM, | |
225 | }, | |
226 | }; | |
227 | ||
228 | struct platform_device davinci_wdt_device = { | |
229 | .name = "watchdog", | |
230 | .id = -1, | |
231 | .num_resources = ARRAY_SIZE(da8xx_watchdog_resources), | |
232 | .resource = da8xx_watchdog_resources, | |
233 | }; | |
234 | ||
235 | int __init da8xx_register_watchdog(void) | |
236 | { | |
237 | return platform_device_register(&davinci_wdt_device); | |
238 | } | |
239 | ||
240 | static struct resource da8xx_emac_resources[] = { | |
241 | { | |
242 | .start = DA8XX_EMAC_CPPI_PORT_BASE, | |
243 | .end = DA8XX_EMAC_CPPI_PORT_BASE + 0x5000 - 1, | |
244 | .flags = IORESOURCE_MEM, | |
245 | }, | |
246 | { | |
247 | .start = IRQ_DA8XX_C0_RX_THRESH_PULSE, | |
248 | .end = IRQ_DA8XX_C0_RX_THRESH_PULSE, | |
249 | .flags = IORESOURCE_IRQ, | |
250 | }, | |
251 | { | |
252 | .start = IRQ_DA8XX_C0_RX_PULSE, | |
253 | .end = IRQ_DA8XX_C0_RX_PULSE, | |
254 | .flags = IORESOURCE_IRQ, | |
255 | }, | |
256 | { | |
257 | .start = IRQ_DA8XX_C0_TX_PULSE, | |
258 | .end = IRQ_DA8XX_C0_TX_PULSE, | |
259 | .flags = IORESOURCE_IRQ, | |
260 | }, | |
261 | { | |
262 | .start = IRQ_DA8XX_C0_MISC_PULSE, | |
263 | .end = IRQ_DA8XX_C0_MISC_PULSE, | |
264 | .flags = IORESOURCE_IRQ, | |
265 | }, | |
266 | }; | |
267 | ||
268 | struct emac_platform_data da8xx_emac_pdata = { | |
269 | .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET, | |
270 | .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET, | |
271 | .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET, | |
272 | .mdio_reg_offset = DA8XX_MDIO_REG_OFFSET, | |
273 | .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE, | |
274 | .version = EMAC_VERSION_2, | |
275 | }; | |
276 | ||
277 | static struct platform_device da8xx_emac_device = { | |
278 | .name = "davinci_emac", | |
279 | .id = 1, | |
280 | .dev = { | |
281 | .platform_data = &da8xx_emac_pdata, | |
282 | }, | |
283 | .num_resources = ARRAY_SIZE(da8xx_emac_resources), | |
284 | .resource = da8xx_emac_resources, | |
285 | }; | |
286 | ||
31f53cf3 MG |
287 | int __init da8xx_register_emac(void) |
288 | { | |
289 | return platform_device_register(&da8xx_emac_device); | |
290 | } | |
291 | ||
e33ef5e3 C |
292 | static struct resource da830_mcasp1_resources[] = { |
293 | { | |
294 | .name = "mcasp1", | |
295 | .start = DAVINCI_DA830_MCASP1_REG_BASE, | |
296 | .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1, | |
297 | .flags = IORESOURCE_MEM, | |
298 | }, | |
299 | /* TX event */ | |
300 | { | |
301 | .start = DAVINCI_DA830_DMA_MCASP1_AXEVT, | |
302 | .end = DAVINCI_DA830_DMA_MCASP1_AXEVT, | |
303 | .flags = IORESOURCE_DMA, | |
304 | }, | |
305 | /* RX event */ | |
306 | { | |
307 | .start = DAVINCI_DA830_DMA_MCASP1_AREVT, | |
308 | .end = DAVINCI_DA830_DMA_MCASP1_AREVT, | |
309 | .flags = IORESOURCE_DMA, | |
310 | }, | |
311 | }; | |
312 | ||
313 | static struct platform_device da830_mcasp1_device = { | |
314 | .name = "davinci-mcasp", | |
315 | .id = 1, | |
316 | .num_resources = ARRAY_SIZE(da830_mcasp1_resources), | |
317 | .resource = da830_mcasp1_resources, | |
318 | }; | |
319 | ||
491214e1 C |
320 | static struct resource da850_mcasp_resources[] = { |
321 | { | |
322 | .name = "mcasp", | |
323 | .start = DAVINCI_DA8XX_MCASP0_REG_BASE, | |
324 | .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1, | |
325 | .flags = IORESOURCE_MEM, | |
326 | }, | |
327 | /* TX event */ | |
328 | { | |
329 | .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, | |
330 | .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, | |
331 | .flags = IORESOURCE_DMA, | |
332 | }, | |
333 | /* RX event */ | |
334 | { | |
335 | .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT, | |
336 | .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT, | |
337 | .flags = IORESOURCE_DMA, | |
338 | }, | |
339 | }; | |
340 | ||
341 | static struct platform_device da850_mcasp_device = { | |
342 | .name = "davinci-mcasp", | |
343 | .id = 0, | |
344 | .num_resources = ARRAY_SIZE(da850_mcasp_resources), | |
345 | .resource = da850_mcasp_resources, | |
346 | }; | |
347 | ||
b8864aa4 | 348 | void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata) |
e33ef5e3 | 349 | { |
491214e1 C |
350 | /* DA830/OMAP-L137 has 3 instances of McASP */ |
351 | if (cpu_is_davinci_da830() && id == 1) { | |
e33ef5e3 C |
352 | da830_mcasp1_device.dev.platform_data = pdata; |
353 | platform_device_register(&da830_mcasp1_device); | |
491214e1 C |
354 | } else if (cpu_is_davinci_da850()) { |
355 | da850_mcasp_device.dev.platform_data = pdata; | |
356 | platform_device_register(&da850_mcasp_device); | |
e33ef5e3 C |
357 | } |
358 | } | |
5cbdf276 SR |
359 | |
360 | static const struct display_panel disp_panel = { | |
361 | QVGA, | |
362 | 16, | |
363 | 16, | |
364 | COLOR_ACTIVE, | |
365 | }; | |
366 | ||
367 | static struct lcd_ctrl_config lcd_cfg = { | |
368 | &disp_panel, | |
369 | .ac_bias = 255, | |
370 | .ac_bias_intrpt = 0, | |
371 | .dma_burst_sz = 16, | |
372 | .bpp = 16, | |
373 | .fdd = 255, | |
374 | .tft_alt_mode = 0, | |
375 | .stn_565_mode = 0, | |
376 | .mono_8bit_mode = 0, | |
377 | .invert_line_clock = 1, | |
378 | .invert_frm_clock = 1, | |
379 | .sync_edge = 0, | |
380 | .sync_ctrl = 1, | |
381 | .raster_order = 0, | |
382 | }; | |
383 | ||
b9e6342b MG |
384 | struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = { |
385 | .manu_name = "sharp", | |
386 | .controller_data = &lcd_cfg, | |
387 | .type = "Sharp_LCD035Q3DG01", | |
388 | }; | |
389 | ||
390 | struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = { | |
391 | .manu_name = "sharp", | |
392 | .controller_data = &lcd_cfg, | |
393 | .type = "Sharp_LK043T1DG01", | |
5cbdf276 SR |
394 | }; |
395 | ||
396 | static struct resource da8xx_lcdc_resources[] = { | |
397 | [0] = { /* registers */ | |
398 | .start = DA8XX_LCD_CNTRL_BASE, | |
399 | .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1, | |
400 | .flags = IORESOURCE_MEM, | |
401 | }, | |
402 | [1] = { /* interrupt */ | |
403 | .start = IRQ_DA8XX_LCDINT, | |
404 | .end = IRQ_DA8XX_LCDINT, | |
405 | .flags = IORESOURCE_IRQ, | |
406 | }, | |
407 | }; | |
408 | ||
b9e6342b | 409 | static struct platform_device da8xx_lcdc_device = { |
5cbdf276 SR |
410 | .name = "da8xx_lcdc", |
411 | .id = 0, | |
412 | .num_resources = ARRAY_SIZE(da8xx_lcdc_resources), | |
413 | .resource = da8xx_lcdc_resources, | |
5cbdf276 SR |
414 | }; |
415 | ||
b9e6342b | 416 | int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata) |
5cbdf276 | 417 | { |
b9e6342b MG |
418 | da8xx_lcdc_device.dev.platform_data = pdata; |
419 | return platform_device_register(&da8xx_lcdc_device); | |
5cbdf276 | 420 | } |
700691f2 SR |
421 | |
422 | static struct resource da8xx_mmcsd0_resources[] = { | |
423 | { /* registers */ | |
424 | .start = DA8XX_MMCSD0_BASE, | |
425 | .end = DA8XX_MMCSD0_BASE + SZ_4K - 1, | |
426 | .flags = IORESOURCE_MEM, | |
427 | }, | |
428 | { /* interrupt */ | |
429 | .start = IRQ_DA8XX_MMCSDINT0, | |
430 | .end = IRQ_DA8XX_MMCSDINT0, | |
431 | .flags = IORESOURCE_IRQ, | |
432 | }, | |
433 | { /* DMA RX */ | |
434 | .start = EDMA_CTLR_CHAN(0, 16), | |
435 | .end = EDMA_CTLR_CHAN(0, 16), | |
436 | .flags = IORESOURCE_DMA, | |
437 | }, | |
438 | { /* DMA TX */ | |
439 | .start = EDMA_CTLR_CHAN(0, 17), | |
440 | .end = EDMA_CTLR_CHAN(0, 17), | |
441 | .flags = IORESOURCE_DMA, | |
442 | }, | |
443 | }; | |
444 | ||
445 | static struct platform_device da8xx_mmcsd0_device = { | |
446 | .name = "davinci_mmc", | |
447 | .id = 0, | |
448 | .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources), | |
449 | .resource = da8xx_mmcsd0_resources, | |
450 | }; | |
451 | ||
452 | int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config) | |
453 | { | |
454 | da8xx_mmcsd0_device.dev.platform_data = config; | |
455 | return platform_device_register(&da8xx_mmcsd0_device); | |
456 | } | |
c51df70b MG |
457 | |
458 | static struct resource da8xx_rtc_resources[] = { | |
459 | { | |
460 | .start = DA8XX_RTC_BASE, | |
461 | .end = DA8XX_RTC_BASE + SZ_4K - 1, | |
462 | .flags = IORESOURCE_MEM, | |
463 | }, | |
464 | { /* timer irq */ | |
465 | .start = IRQ_DA8XX_RTC, | |
466 | .end = IRQ_DA8XX_RTC, | |
467 | .flags = IORESOURCE_IRQ, | |
468 | }, | |
469 | { /* alarm irq */ | |
470 | .start = IRQ_DA8XX_RTC, | |
471 | .end = IRQ_DA8XX_RTC, | |
472 | .flags = IORESOURCE_IRQ, | |
473 | }, | |
474 | }; | |
475 | ||
476 | static struct platform_device da8xx_rtc_device = { | |
477 | .name = "omap_rtc", | |
478 | .id = -1, | |
479 | .num_resources = ARRAY_SIZE(da8xx_rtc_resources), | |
480 | .resource = da8xx_rtc_resources, | |
481 | }; | |
482 | ||
483 | int da8xx_register_rtc(void) | |
484 | { | |
75c99bb0 SN |
485 | int ret; |
486 | ||
c51df70b MG |
487 | /* Unlock the rtc's registers */ |
488 | __raw_writel(0x83e70b13, IO_ADDRESS(DA8XX_RTC_BASE + 0x6c)); | |
489 | __raw_writel(0x95a4f1e0, IO_ADDRESS(DA8XX_RTC_BASE + 0x70)); | |
490 | ||
75c99bb0 SN |
491 | ret = platform_device_register(&da8xx_rtc_device); |
492 | if (!ret) | |
493 | /* Atleast on DA850, RTC is a wakeup source */ | |
494 | device_init_wakeup(&da8xx_rtc_device.dev, true); | |
495 | ||
496 | return ret; | |
c51df70b | 497 | } |
1960e693 SN |
498 | |
499 | static struct resource da8xx_cpuidle_resources[] = { | |
500 | { | |
501 | .start = DA8XX_DDR2_CTL_BASE, | |
502 | .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1, | |
503 | .flags = IORESOURCE_MEM, | |
504 | }, | |
505 | }; | |
506 | ||
507 | /* DA8XX devices support DDR2 power down */ | |
508 | static struct davinci_cpuidle_config da8xx_cpuidle_pdata = { | |
509 | .ddr2_pdown = 1, | |
510 | }; | |
511 | ||
512 | ||
513 | static struct platform_device da8xx_cpuidle_device = { | |
514 | .name = "cpuidle-davinci", | |
515 | .num_resources = ARRAY_SIZE(da8xx_cpuidle_resources), | |
516 | .resource = da8xx_cpuidle_resources, | |
517 | .dev = { | |
518 | .platform_data = &da8xx_cpuidle_pdata, | |
519 | }, | |
520 | }; | |
521 | ||
522 | int __init da8xx_register_cpuidle(void) | |
523 | { | |
524 | return platform_device_register(&da8xx_cpuidle_device); | |
525 | } | |
526 |