[deliverable/linux.git] / arch / arm / mach-davinci / devices.c

/*
 * mach-davinci/devices.c
 *
 * DaVinci platform device setup/initialization
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/io.h>

#include <mach/hardware.h>
#include <mach/i2c.h>
#include <mach/irqs.h>
#include <mach/cputype.h>
#include <mach/mux.h>
#include <mach/edma.h>
#include <mach/mmc.h>
#include <mach/time.h>

#include "clock.h"

#define DAVINCI_I2C_BASE	     0x01C21000
#define DAVINCI_ATA_BASE	     0x01C66000
#define DAVINCI_MMCSD0_BASE	     0x01E10000
#define DM355_MMCSD0_BASE	     0x01E11000
#define DM355_MMCSD1_BASE	     0x01E00000
#define DM365_MMCSD0_BASE	     0x01D11000
#define DM365_MMCSD1_BASE	     0x01D00000

static struct resource i2c_resources[] = {
	{
		.start		= DAVINCI_I2C_BASE,
		.end		= DAVINCI_I2C_BASE + 0x40,
		.flags		= IORESOURCE_MEM,
	},
	{
		.start		= IRQ_I2C,
		.flags		= IORESOURCE_IRQ,
	},
};

static struct platform_device davinci_i2c_device = {
	.name           = "i2c_davinci",
	.id             = 1,
	.num_resources	= ARRAY_SIZE(i2c_resources),
	.resource	= i2c_resources,
};

void __init davinci_init_i2c(struct davinci_i2c_platform_data *pdata)
{
	if (cpu_is_davinci_dm644x())
		davinci_cfg_reg(DM644X_I2C);

	davinci_i2c_device.dev.platform_data = pdata;
	(void) platform_device_register(&davinci_i2c_device);
}

static struct resource ide_resources[] = {
	{
		.start		= DAVINCI_ATA_BASE,
		.end		= DAVINCI_ATA_BASE + 0x7ff,
		.flags		= IORESOURCE_MEM,
	},
	{
		.start		= IRQ_IDE,
		.end		= IRQ_IDE,
		.flags		= IORESOURCE_IRQ,
	},
};

static u64 ide_dma_mask = DMA_BIT_MASK(32);

static struct platform_device ide_device = {
	.name           = "palm_bk3710",
	.id             = -1,
	.resource       = ide_resources,
	.num_resources  = ARRAY_SIZE(ide_resources),
	.dev = {
		.dma_mask		= &ide_dma_mask,
		.coherent_dma_mask      = DMA_BIT_MASK(32),
	},
};

void __init davinci_init_ide(void)
{
	if (cpu_is_davinci_dm644x()) {
		davinci_cfg_reg(DM644X_HPIEN_DISABLE);
		davinci_cfg_reg(DM644X_ATAEN);
		davinci_cfg_reg(DM644X_HDIREN);
	} else if (cpu_is_davinci_dm646x()) {
		/* IRQ_DM646X_IDE is the same as IRQ_IDE */
		davinci_cfg_reg(DM646X_ATAEN);
	} else {
		WARN_ON(1);
		return;
	}

	platform_device_register(&ide_device);
}

#if	defined(CONFIG_MMC_DAVINCI) || defined(CONFIG_MMC_DAVINCI_MODULE)

static u64 mmcsd0_dma_mask = DMA_BIT_MASK(32);

static struct resource mmcsd0_resources[] = {
	{
		/* different on dm355 */
		.start = DAVINCI_MMCSD0_BASE,
		.end   = DAVINCI_MMCSD0_BASE + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
	/* IRQs:  MMC/SD, then SDIO */
	{
		.start = IRQ_MMCINT,
		.flags = IORESOURCE_IRQ,
	}, {
		/* different on dm355 */
		.start = IRQ_SDIOINT,
		.flags = IORESOURCE_IRQ,
	},
	/* DMA channels: RX, then TX */
	{
		.start = EDMA_CTLR_CHAN(0, DAVINCI_DMA_MMCRXEVT),
		.flags = IORESOURCE_DMA,
	}, {
		.start = EDMA_CTLR_CHAN(0, DAVINCI_DMA_MMCTXEVT),
		.flags = IORESOURCE_DMA,
	},
};

static struct platform_device davinci_mmcsd0_device = {
	.name = "davinci_mmc",
	.id = 0,
	.dev = {
		.dma_mask = &mmcsd0_dma_mask,
		.coherent_dma_mask = DMA_BIT_MASK(32),
	},
	.num_resources = ARRAY_SIZE(mmcsd0_resources),
	.resource = mmcsd0_resources,
};

static u64 mmcsd1_dma_mask = DMA_BIT_MASK(32);

static struct resource mmcsd1_resources[] = {
	{
		.start = DM355_MMCSD1_BASE,
		.end   = DM355_MMCSD1_BASE + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
	/* IRQs:  MMC/SD, then SDIO */
	{
		.start = IRQ_DM355_MMCINT1,
		.flags = IORESOURCE_IRQ,
	}, {
		.start = IRQ_DM355_SDIOINT1,
		.flags = IORESOURCE_IRQ,
	},
	/* DMA channels: RX, then TX */
	{
		.start = EDMA_CTLR_CHAN(0, 30),	/* rx */
		.flags = IORESOURCE_DMA,
	}, {
		.start = EDMA_CTLR_CHAN(0, 31),	/* tx */
		.flags = IORESOURCE_DMA,
	},
};

static struct platform_device davinci_mmcsd1_device = {
	.name = "davinci_mmc",
	.id = 1,
	.dev = {
		.dma_mask = &mmcsd1_dma_mask,
		.coherent_dma_mask = DMA_BIT_MASK(32),
	},
	.num_resources = ARRAY_SIZE(mmcsd1_resources),
	.resource = mmcsd1_resources,
};


void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
{
	struct platform_device	*pdev = NULL;

	if (WARN_ON(cpu_is_davinci_dm646x()))
		return;

	/* REVISIT: update PINMUX, ARM_IRQMUX, and EDMA_EVTMUX here too;
	 * for example if MMCSD1 is used for SDIO, maybe DAT2 is unused.
	 *
	 * FIXME dm6441 (no MMC/SD), dm357 (one), and dm335 (two) are
	 * not handled right here ...
	 */
	switch (module) {
	case 1:
		if (cpu_is_davinci_dm355()) {
			/* REVISIT we may not need all these pins if e.g. this
			 * is a hard-wired SDIO device...
			 */
			davinci_cfg_reg(DM355_SD1_CMD);
			davinci_cfg_reg(DM355_SD1_CLK);
			davinci_cfg_reg(DM355_SD1_DATA0);
			davinci_cfg_reg(DM355_SD1_DATA1);
			davinci_cfg_reg(DM355_SD1_DATA2);
			davinci_cfg_reg(DM355_SD1_DATA3);
		} else if (cpu_is_davinci_dm365()) {
			void __iomem *pupdctl1 =
				IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE + 0x7c);

			/* Configure pull down control */
			__raw_writel((__raw_readl(pupdctl1) & ~0x400),
					pupdctl1);

			mmcsd1_resources[0].start = DM365_MMCSD1_BASE;
			mmcsd1_resources[0].end = DM365_MMCSD1_BASE +
							SZ_4K - 1;
			mmcsd1_resources[2].start = IRQ_DM365_SDIOINT1;
		} else
			break;

		pdev = &davinci_mmcsd1_device;
		break;
	case 0:
		if (cpu_is_davinci_dm355()) {
			mmcsd0_resources[0].start = DM355_MMCSD0_BASE;
			mmcsd0_resources[0].end = DM355_MMCSD0_BASE + SZ_4K - 1;
			mmcsd0_resources[2].start = IRQ_DM355_SDIOINT0;

			/* expose all 6 MMC0 signals:  CLK, CMD, DATA[0..3] */
			davinci_cfg_reg(DM355_MMCSD0);

			/* enable RX EDMA */
			davinci_cfg_reg(DM355_EVT26_MMC0_RX);
		} else if (cpu_is_davinci_dm365()) {
			mmcsd0_resources[0].start = DM365_MMCSD0_BASE;
			mmcsd0_resources[0].end = DM365_MMCSD0_BASE +
							SZ_4K - 1;
			mmcsd0_resources[2].start = IRQ_DM365_SDIOINT0;
		} else if (cpu_is_davinci_dm644x()) {
			/* REVISIT: should this be in board-init code? */
			void __iomem *base =
				IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);

			/* Power-on 3.3V IO cells */
			__raw_writel(0, base + DM64XX_VDD3P3V_PWDN);
			/*Set up the pull regiter for MMC */
			davinci_cfg_reg(DM644X_MSTK);
		}

		pdev = &davinci_mmcsd0_device;
		break;
	}

	if (WARN_ON(!pdev))
		return;

	pdev->dev.platform_data = config;
	platform_device_register(pdev);
}

#else

void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
{
}

#endif

/*-------------------------------------------------------------------------*/

static struct resource wdt_resources[] = {
	{
		.start	= DAVINCI_WDOG_BASE,
		.end	= DAVINCI_WDOG_BASE + SZ_1K - 1,
		.flags	= IORESOURCE_MEM,
	},
};

struct platform_device davinci_wdt_device = {
	.name		= "watchdog",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(wdt_resources),
	.resource	= wdt_resources,
};

static void davinci_init_wdt(void)
{
	platform_device_register(&davinci_wdt_device);
}

/*-------------------------------------------------------------------------*/

struct davinci_timer_instance davinci_timer_instance[2] = {
	{
		.base		= DAVINCI_TIMER0_BASE,
		.bottom_irq	= IRQ_TINT0_TINT12,
		.top_irq	= IRQ_TINT0_TINT34,
	},
	{
		.base		= DAVINCI_TIMER1_BASE,
		.bottom_irq	= IRQ_TINT1_TINT12,
		.top_irq	= IRQ_TINT1_TINT34,
	},
};

/*-------------------------------------------------------------------------*/

static int __init davinci_init_devices(void)
{
	/* please keep these calls, and their implementations above,
	 * in alphabetical order so they're easier to sort through.
	 */
	davinci_init_wdt();

	return 0;
}
arch_initcall(davinci_init_devices);
Commit	Line	Data
d395e6ad KS	1	/*
	2	* mach-davinci/devices.c
	3	*
	4	* DaVinci platform device setup/initialization
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*/
	11
d395e6ad KS	12	#include <linux/init.h>
	13	#include <linux/platform_device.h>
	14	#include <linux/dma-mapping.h>
	15	#include <linux/io.h>
	16
d395e6ad KS	17	#include <mach/hardware.h>
d395e6ad KS	18	#include <mach/i2c.h>
80b02c17	19	#include <mach/irqs.h>
5526b3f7 KH	20	#include <mach/cputype.h>
5526b3f7 KH	21	#include <mach/mux.h>
2dbf56ae KH	22	#include <mach/edma.h>
2dbf56ae KH	23	#include <mach/mmc.h>
f64691b3	24	#include <mach/time.h>
d395e6ad	25
28552c2e KH	26	#include "clock.h"
28552c2e KH	27
f5c122da	28	#define DAVINCI_I2C_BASE 0x01C21000
7a9978a1	29	#define DAVINCI_ATA_BASE 0x01C66000
2dbf56ae KH	30	#define DAVINCI_MMCSD0_BASE 0x01E10000
	31	#define DM355_MMCSD0_BASE 0x01E11000
	32	#define DM355_MMCSD1_BASE 0x01E00000
19ff3bf2 SP	33	#define DM365_MMCSD0_BASE 0x01D11000
19ff3bf2 SP	34	#define DM365_MMCSD1_BASE 0x01D00000
f5c122da	35
d395e6ad KS	36	static struct resource i2c_resources[] = {
	37	{
	38	.start = DAVINCI_I2C_BASE,
	39	.end = DAVINCI_I2C_BASE + 0x40,
	40	.flags = IORESOURCE_MEM,
	41	},
	42	{
	43	.start = IRQ_I2C,
	44	.flags = IORESOURCE_IRQ,
	45	},
	46	};
	47
	48	static struct platform_device davinci_i2c_device = {
	49	.name = "i2c_davinci",
	50	.id = 1,
	51	.num_resources = ARRAY_SIZE(i2c_resources),
	52	.resource = i2c_resources,
	53	};
	54
	55	void __init davinci_init_i2c(struct davinci_i2c_platform_data *pdata)
	56	{
5526b3f7 KH	57	if (cpu_is_davinci_dm644x())
	58	davinci_cfg_reg(DM644X_I2C);
	59
d395e6ad KS	60	davinci_i2c_device.dev.platform_data = pdata;
	61	(void) platform_device_register(&davinci_i2c_device);
	62	}
	63
7a9978a1 SS	64	static struct resource ide_resources[] = {
	65	{
	66	.start = DAVINCI_ATA_BASE,
	67	.end = DAVINCI_ATA_BASE + 0x7ff,
	68	.flags = IORESOURCE_MEM,
	69	},
	70	{
	71	.start = IRQ_IDE,
	72	.end = IRQ_IDE,
	73	.flags = IORESOURCE_IRQ,
	74	},
	75	};
	76
	77	static u64 ide_dma_mask = DMA_BIT_MASK(32);
	78
	79	static struct platform_device ide_device = {
	80	.name = "palm_bk3710",
	81	.id = -1,
	82	.resource = ide_resources,
	83	.num_resources = ARRAY_SIZE(ide_resources),
	84	.dev = {
	85	.dma_mask = &ide_dma_mask,
	86	.coherent_dma_mask = DMA_BIT_MASK(32),
	87	},
	88	};
	89
	90	void __init davinci_init_ide(void)
	91	{
	92	if (cpu_is_davinci_dm644x()) {
	93	davinci_cfg_reg(DM644X_HPIEN_DISABLE);
	94	davinci_cfg_reg(DM644X_ATAEN);
	95	davinci_cfg_reg(DM644X_HDIREN);
	96	} else if (cpu_is_davinci_dm646x()) {
	97	/* IRQ_DM646X_IDE is the same as IRQ_IDE */
	98	davinci_cfg_reg(DM646X_ATAEN);
	99	} else {
	100	WARN_ON(1);
	101	return;
	102	}
	103
	104	platform_device_register(&ide_device);
	105	}
	106
2dbf56ae KH	107	#if defined(CONFIG_MMC_DAVINCI) \|\| defined(CONFIG_MMC_DAVINCI_MODULE)
2dbf56ae KH	108
b0958aed	109	static u64 mmcsd0_dma_mask = DMA_BIT_MASK(32);
2dbf56ae KH	110
	111	static struct resource mmcsd0_resources[] = {
	112	{
	113	/* different on dm355 */
	114	.start = DAVINCI_MMCSD0_BASE,
	115	.end = DAVINCI_MMCSD0_BASE + SZ_4K - 1,
	116	.flags = IORESOURCE_MEM,
	117	},
	118	/* IRQs: MMC/SD, then SDIO */
	119	{
	120	.start = IRQ_MMCINT,
	121	.flags = IORESOURCE_IRQ,
	122	}, {
	123	/* different on dm355 */
	124	.start = IRQ_SDIOINT,
	125	.flags = IORESOURCE_IRQ,
	126	},
	127	/* DMA channels: RX, then TX */
	128	{
60902a2c	129	.start = EDMA_CTLR_CHAN(0, DAVINCI_DMA_MMCRXEVT),
2dbf56ae KH	130	.flags = IORESOURCE_DMA,
2dbf56ae KH	131	}, {
60902a2c	132	.start = EDMA_CTLR_CHAN(0, DAVINCI_DMA_MMCTXEVT),
2dbf56ae KH	133	.flags = IORESOURCE_DMA,
	134	},
	135	};
	136
	137	static struct platform_device davinci_mmcsd0_device = {
	138	.name = "davinci_mmc",
	139	.id = 0,
	140	.dev = {
	141	.dma_mask = &mmcsd0_dma_mask,
b0958aed	142	.coherent_dma_mask = DMA_BIT_MASK(32),
2dbf56ae KH	143	},
	144	.num_resources = ARRAY_SIZE(mmcsd0_resources),
	145	.resource = mmcsd0_resources,
	146	};
	147
b0958aed	148	static u64 mmcsd1_dma_mask = DMA_BIT_MASK(32);
2dbf56ae KH	149
	150	static struct resource mmcsd1_resources[] = {
	151	{
	152	.start = DM355_MMCSD1_BASE,
	153	.end = DM355_MMCSD1_BASE + SZ_4K - 1,
	154	.flags = IORESOURCE_MEM,
	155	},
	156	/* IRQs: MMC/SD, then SDIO */
	157	{
	158	.start = IRQ_DM355_MMCINT1,
	159	.flags = IORESOURCE_IRQ,
	160	}, {
	161	.start = IRQ_DM355_SDIOINT1,
	162	.flags = IORESOURCE_IRQ,
	163	},
	164	/* DMA channels: RX, then TX */
	165	{
60902a2c	166	.start = EDMA_CTLR_CHAN(0, 30), /* rx */
2dbf56ae KH	167	.flags = IORESOURCE_DMA,
2dbf56ae KH	168	}, {
60902a2c	169	.start = EDMA_CTLR_CHAN(0, 31), /* tx */
2dbf56ae KH	170	.flags = IORESOURCE_DMA,
	171	},
	172	};
	173
	174	static struct platform_device davinci_mmcsd1_device = {
	175	.name = "davinci_mmc",
	176	.id = 1,
	177	.dev = {
	178	.dma_mask = &mmcsd1_dma_mask,
b0958aed	179	.coherent_dma_mask = DMA_BIT_MASK(32),
2dbf56ae KH	180	},
	181	.num_resources = ARRAY_SIZE(mmcsd1_resources),
	182	.resource = mmcsd1_resources,
	183	};
	184
	185
	186	void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
	187	{
	188	struct platform_device *pdev = NULL;
	189
	190	if (WARN_ON(cpu_is_davinci_dm646x()))
	191	return;
	192
	193	/* REVISIT: update PINMUX, ARM_IRQMUX, and EDMA_EVTMUX here too;
	194	* for example if MMCSD1 is used for SDIO, maybe DAT2 is unused.
	195	*
	196	* FIXME dm6441 (no MMC/SD), dm357 (one), and dm335 (two) are
	197	* not handled right here ...
	198	*/
	199	switch (module) {
	200	case 1:
19ff3bf2 SP	201	if (cpu_is_davinci_dm355()) {
	202	/* REVISIT we may not need all these pins if e.g. this
	203	* is a hard-wired SDIO device...
	204	*/
	205	davinci_cfg_reg(DM355_SD1_CMD);
	206	davinci_cfg_reg(DM355_SD1_CLK);
	207	davinci_cfg_reg(DM355_SD1_DATA0);
	208	davinci_cfg_reg(DM355_SD1_DATA1);
	209	davinci_cfg_reg(DM355_SD1_DATA2);
	210	davinci_cfg_reg(DM355_SD1_DATA3);
	211	} else if (cpu_is_davinci_dm365()) {
	212	void __iomem *pupdctl1 =
	213	IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE + 0x7c);
	214
	215	/* Configure pull down control */
	216	__raw_writel((__raw_readl(pupdctl1) & ~0x400),
	217	pupdctl1);
	218
	219	mmcsd1_resources[0].start = DM365_MMCSD1_BASE;
	220	mmcsd1_resources[0].end = DM365_MMCSD1_BASE +
	221	SZ_4K - 1;
eb5ba378	222	mmcsd1_resources[2].start = IRQ_DM365_SDIOINT1;
19ff3bf2	223	} else
2dbf56ae KH	224	break;
2dbf56ae KH	225
2dbf56ae KH	226	pdev = &davinci_mmcsd1_device;
	227	break;
	228	case 0:
	229	if (cpu_is_davinci_dm355()) {
	230	mmcsd0_resources[0].start = DM355_MMCSD0_BASE;
	231	mmcsd0_resources[0].end = DM355_MMCSD0_BASE + SZ_4K - 1;
	232	mmcsd0_resources[2].start = IRQ_DM355_SDIOINT0;
	233
	234	/* expose all 6 MMC0 signals: CLK, CMD, DATA[0..3] */
	235	davinci_cfg_reg(DM355_MMCSD0);
	236
	237	/* enable RX EDMA */
	238	davinci_cfg_reg(DM355_EVT26_MMC0_RX);
19ff3bf2 SP	239	} else if (cpu_is_davinci_dm365()) {
	240	mmcsd0_resources[0].start = DM365_MMCSD0_BASE;
	241	mmcsd0_resources[0].end = DM365_MMCSD0_BASE +
	242	SZ_4K - 1;
	243	mmcsd0_resources[2].start = IRQ_DM365_SDIOINT0;
	244	} else if (cpu_is_davinci_dm644x()) {
2dbf56ae KH	245	/* REVISIT: should this be in board-init code? */
	246	void __iomem *base =
	247	IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
	248
	249	/* Power-on 3.3V IO cells */
	250	__raw_writel(0, base + DM64XX_VDD3P3V_PWDN);
	251	/Set up the pull regiter for MMC /
	252	davinci_cfg_reg(DM644X_MSTK);
	253	}
	254
	255	pdev = &davinci_mmcsd0_device;
	256	break;
	257	}
	258
	259	if (WARN_ON(!pdev))
	260	return;
	261
	262	pdev->dev.platform_data = config;
	263	platform_device_register(pdev);
	264	}
	265
	266	#else
	267
	268	void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
	269	{
	270	}
	271
	272	#endif
	273
fb631387 KH	274	/-------------------------------------------------------------------------/
	275
	276	static struct resource wdt_resources[] = {
	277	{
5fcd294d KH	278	.start = DAVINCI_WDOG_BASE,
5fcd294d KH	279	.end = DAVINCI_WDOG_BASE + SZ_1K - 1,
fb631387 KH	280	.flags = IORESOURCE_MEM,
	281	},
	282	};
	283
	284	struct platform_device davinci_wdt_device = {
	285	.name = "watchdog",
	286	.id = -1,
	287	.num_resources = ARRAY_SIZE(wdt_resources),
	288	.resource = wdt_resources,
	289	};
	290
	291	static void davinci_init_wdt(void)
	292	{
	293	platform_device_register(&davinci_wdt_device);
	294	}
	295
	296	/-------------------------------------------------------------------------/
	297
f64691b3 MG	298	struct davinci_timer_instance davinci_timer_instance[2] = {
f64691b3 MG	299	{
1bcd38ad	300	.base = DAVINCI_TIMER0_BASE,
f64691b3 MG	301	.bottom_irq = IRQ_TINT0_TINT12,
	302	.top_irq = IRQ_TINT0_TINT34,
	303	},
	304	{
1bcd38ad	305	.base = DAVINCI_TIMER1_BASE,
f64691b3 MG	306	.bottom_irq = IRQ_TINT1_TINT12,
	307	.top_irq = IRQ_TINT1_TINT34,
	308	},
	309	};
	310
	311	/-------------------------------------------------------------------------/
	312
fb631387 KH	313	static int __init davinci_init_devices(void)
	314	{
	315	/* please keep these calls, and their implementations above,
	316	* in alphabetical order so they're easier to sort through.
	317	*/
	318	davinci_init_wdt();
	319
	320	return 0;
	321	}
	322	arch_initcall(davinci_init_devices);
	323