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Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
[deliverable/linux.git] / arch / arm / mach-davinci / dm355.c
CommitLineData
95a3477f
KH		 1/*
2 * TI DaVinci DM355 chip specific setup
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
95a3477f
KH		 11#include <linux/init.h>
12#include <linux/clk.h>
65e866a9 13#include <linux/serial_8250.h>
95a3477f
KH		 14#include <linux/platform_device.h>
15#include <linux/dma-mapping.h>
16
17#include <linux/spi/spi.h>
18
79c3c0b7
MG		 19#include <asm/mach/map.h>
20
95a3477f
KH		 21#include <mach/cputype.h>
22#include <mach/edma.h>
23#include <mach/psc.h>
24#include <mach/mux.h>
25#include <mach/irqs.h>
f64691b3 26#include <mach/time.h>
65e866a9 27#include <mach/serial.h>
79c3c0b7 28#include <mach/common.h>
ec2a0833 29#include <linux/platform_data/spi-davinci.h>
5f3fcf96 30#include <mach/gpio-davinci.h>
95a3477f 31
39c6d2d1 32#include "davinci.h"
95a3477f
KH		 33#include "clock.h"
34#include "mux.h"
896f66b7 35#include "asp.h"
95a3477f 36
96ed299f 37#define DM355_UART2_BASE (IO_PHYS + 0x206000)
62a2d6cd
LP		 38#define DM355_OSD_BASE (IO_PHYS + 0x70200)
39#define DM355_VENC_BASE (IO_PHYS + 0x70400)
96ed299f 40
95a3477f
KH		 41/*
42 * Device specific clocks
43 */
44#define DM355_REF_FREQ 24000000 /* 24 or 36 MHz */
45
46static struct pll_data pll1_data = {
47 .num = 1,
48 .phys_base = DAVINCI_PLL1_BASE,
49 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
50};
51
52static struct pll_data pll2_data = {
53 .num = 2,
54 .phys_base = DAVINCI_PLL2_BASE,
55 .flags = PLL_HAS_PREDIV,
56};
57
58static struct clk ref_clk = {
59 .name = "ref_clk",
60 /* FIXME -- crystal rate is board-specific */
61 .rate = DM355_REF_FREQ,
62};
63
64static struct clk pll1_clk = {
65 .name = "pll1",
66 .parent = &ref_clk,
67 .flags = CLK_PLL,
68 .pll_data = &pll1_data,
69};
70
71static struct clk pll1_aux_clk = {
72 .name = "pll1_aux_clk",
73 .parent = &pll1_clk,
74 .flags = CLK_PLL | PRE_PLL,
75};
76
77static struct clk pll1_sysclk1 = {
78 .name = "pll1_sysclk1",
79 .parent = &pll1_clk,
80 .flags = CLK_PLL,
81 .div_reg = PLLDIV1,
82};
83
84static struct clk pll1_sysclk2 = {
85 .name = "pll1_sysclk2",
86 .parent = &pll1_clk,
87 .flags = CLK_PLL,
88 .div_reg = PLLDIV2,
89};
90
91static struct clk pll1_sysclk3 = {
92 .name = "pll1_sysclk3",
93 .parent = &pll1_clk,
94 .flags = CLK_PLL,
95 .div_reg = PLLDIV3,
96};
97
98static struct clk pll1_sysclk4 = {
99 .name = "pll1_sysclk4",
100 .parent = &pll1_clk,
101 .flags = CLK_PLL,
102 .div_reg = PLLDIV4,
103};
104
105static struct clk pll1_sysclkbp = {
106 .name = "pll1_sysclkbp",
107 .parent = &pll1_clk,
108 .flags = CLK_PLL | PRE_PLL,
109 .div_reg = BPDIV
110};
111
112static struct clk vpss_dac_clk = {
113 .name = "vpss_dac",
114 .parent = &pll1_sysclk3,
115 .lpsc = DM355_LPSC_VPSS_DAC,
116};
117
118static struct clk vpss_master_clk = {
119 .name = "vpss_master",
120 .parent = &pll1_sysclk4,
121 .lpsc = DAVINCI_LPSC_VPSSMSTR,
122 .flags = CLK_PSC,
123};
124
125static struct clk vpss_slave_clk = {
126 .name = "vpss_slave",
127 .parent = &pll1_sysclk4,
128 .lpsc = DAVINCI_LPSC_VPSSSLV,
129};
130
95a3477f
KH		 131static struct clk clkout1_clk = {
132 .name = "clkout1",
133 .parent = &pll1_aux_clk,
134 /* NOTE: clkout1 can be externally gated by muxing GPIO-18 */
135};
136
137static struct clk clkout2_clk = {
138 .name = "clkout2",
139 .parent = &pll1_sysclkbp,
140};
141
142static struct clk pll2_clk = {
143 .name = "pll2",
144 .parent = &ref_clk,
145 .flags = CLK_PLL,
146 .pll_data = &pll2_data,
147};
148
149static struct clk pll2_sysclk1 = {
150 .name = "pll2_sysclk1",
151 .parent = &pll2_clk,
152 .flags = CLK_PLL,
153 .div_reg = PLLDIV1,
154};
155
156static struct clk pll2_sysclkbp = {
157 .name = "pll2_sysclkbp",
158 .parent = &pll2_clk,
159 .flags = CLK_PLL | PRE_PLL,
160 .div_reg = BPDIV
161};
162
163static struct clk clkout3_clk = {
164 .name = "clkout3",
165 .parent = &pll2_sysclkbp,
166 /* NOTE: clkout3 can be externally gated by muxing GPIO-16 */
167};
168
169static struct clk arm_clk = {
170 .name = "arm_clk",
171 .parent = &pll1_sysclk1,
172 .lpsc = DAVINCI_LPSC_ARM,
173 .flags = ALWAYS_ENABLED,
174};
175
176/*
177 * NOT LISTED below, and not touched by Linux
178 * - in SyncReset state by default
179 * .lpsc = DAVINCI_LPSC_TPCC,
180 * .lpsc = DAVINCI_LPSC_TPTC0,
181 * .lpsc = DAVINCI_LPSC_TPTC1,
182 * .lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk,
183 * .lpsc = DAVINCI_LPSC_MEMSTICK,
184 * - in Enabled state by default
185 * .lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS,
186 * .lpsc = DAVINCI_LPSC_SCR2, // "bus"
187 * .lpsc = DAVINCI_LPSC_SCR3, // "bus"
188 * .lpsc = DAVINCI_LPSC_SCR4, // "bus"
189 * .lpsc = DAVINCI_LPSC_CROSSBAR, // "emulation"
190 * .lpsc = DAVINCI_LPSC_CFG27, // "test"
191 * .lpsc = DAVINCI_LPSC_CFG3, // "test"
192 * .lpsc = DAVINCI_LPSC_CFG5, // "test"
193 */
194
195static struct clk mjcp_clk = {
196 .name = "mjcp",
197 .parent = &pll1_sysclk1,
198 .lpsc = DAVINCI_LPSC_IMCOP,
199};
200
201static struct clk uart0_clk = {
202 .name = "uart0",
203 .parent = &pll1_aux_clk,
204 .lpsc = DAVINCI_LPSC_UART0,
205};
206
207static struct clk uart1_clk = {
208 .name = "uart1",
209 .parent = &pll1_aux_clk,
210 .lpsc = DAVINCI_LPSC_UART1,
211};
212
213static struct clk uart2_clk = {
214 .name = "uart2",
215 .parent = &pll1_sysclk2,
216 .lpsc = DAVINCI_LPSC_UART2,
217};
218
219static struct clk i2c_clk = {
220 .name = "i2c",
221 .parent = &pll1_aux_clk,
222 .lpsc = DAVINCI_LPSC_I2C,
223};
224
225static struct clk asp0_clk = {
226 .name = "asp0",
227 .parent = &pll1_sysclk2,
228 .lpsc = DAVINCI_LPSC_McBSP,
229};
230
231static struct clk asp1_clk = {
232 .name = "asp1",
233 .parent = &pll1_sysclk2,
234 .lpsc = DM355_LPSC_McBSP1,
235};
236
237static struct clk mmcsd0_clk = {
238 .name = "mmcsd0",
239 .parent = &pll1_sysclk2,
240 .lpsc = DAVINCI_LPSC_MMC_SD,
241};
242
243static struct clk mmcsd1_clk = {
244 .name = "mmcsd1",
245 .parent = &pll1_sysclk2,
246 .lpsc = DM355_LPSC_MMC_SD1,
247};
248
249static struct clk spi0_clk = {
250 .name = "spi0",
251 .parent = &pll1_sysclk2,
252 .lpsc = DAVINCI_LPSC_SPI,
253};
254
255static struct clk spi1_clk = {
256 .name = "spi1",
257 .parent = &pll1_sysclk2,
258 .lpsc = DM355_LPSC_SPI1,
259};
260
261static struct clk spi2_clk = {
262 .name = "spi2",
263 .parent = &pll1_sysclk2,
264 .lpsc = DM355_LPSC_SPI2,
265};
266
267static struct clk gpio_clk = {
268 .name = "gpio",
269 .parent = &pll1_sysclk2,
270 .lpsc = DAVINCI_LPSC_GPIO,
271};
272
273static struct clk aemif_clk = {
274 .name = "aemif",
275 .parent = &pll1_sysclk2,
276 .lpsc = DAVINCI_LPSC_AEMIF,
277};
278
279static struct clk pwm0_clk = {
280 .name = "pwm0",
281 .parent = &pll1_aux_clk,
282 .lpsc = DAVINCI_LPSC_PWM0,
283};
284
285static struct clk pwm1_clk = {
286 .name = "pwm1",
287 .parent = &pll1_aux_clk,
288 .lpsc = DAVINCI_LPSC_PWM1,
289};
290
291static struct clk pwm2_clk = {
292 .name = "pwm2",
293 .parent = &pll1_aux_clk,
294 .lpsc = DAVINCI_LPSC_PWM2,
295};
296
297static struct clk pwm3_clk = {
298 .name = "pwm3",
299 .parent = &pll1_aux_clk,
300 .lpsc = DM355_LPSC_PWM3,
301};
302
303static struct clk timer0_clk = {
304 .name = "timer0",
305 .parent = &pll1_aux_clk,
306 .lpsc = DAVINCI_LPSC_TIMER0,
307};
308
309static struct clk timer1_clk = {
310 .name = "timer1",
311 .parent = &pll1_aux_clk,
312 .lpsc = DAVINCI_LPSC_TIMER1,
313};
314
315static struct clk timer2_clk = {
316 .name = "timer2",
317 .parent = &pll1_aux_clk,
318 .lpsc = DAVINCI_LPSC_TIMER2,
e9c54999 319 .usecount = 1, /* REVISIT: why can't this be disabled? */
95a3477f
KH		 320};
321
322static struct clk timer3_clk = {
323 .name = "timer3",
324 .parent = &pll1_aux_clk,
325 .lpsc = DM355_LPSC_TIMER3,
326};
327
328static struct clk rto_clk = {
329 .name = "rto",
330 .parent = &pll1_aux_clk,
331 .lpsc = DM355_LPSC_RTO,
332};
333
334static struct clk usb_clk = {
335 .name = "usb",
336 .parent = &pll1_sysclk2,
337 .lpsc = DAVINCI_LPSC_USB,
338};
339
08aca087 340static struct clk_lookup dm355_clks[] = {
95a3477f
KH		 341 CLK(NULL, "ref", &ref_clk),
342 CLK(NULL, "pll1", &pll1_clk),
343 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
344 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
345 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
346 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
347 CLK(NULL, "pll1_aux", &pll1_aux_clk),
348 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
349 CLK(NULL, "vpss_dac", &vpss_dac_clk),
9a3e89b1
LP		 350 CLK("vpss", "master", &vpss_master_clk),
351 CLK("vpss", "slave", &vpss_slave_clk),
95a3477f
KH		 352 CLK(NULL, "clkout1", &clkout1_clk),
353 CLK(NULL, "clkout2", &clkout2_clk),
354 CLK(NULL, "pll2", &pll2_clk),
355 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
356 CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
357 CLK(NULL, "clkout3", &clkout3_clk),
358 CLK(NULL, "arm", &arm_clk),
359 CLK(NULL, "mjcp", &mjcp_clk),
360 CLK(NULL, "uart0", &uart0_clk),
361 CLK(NULL, "uart1", &uart1_clk),
362 CLK(NULL, "uart2", &uart2_clk),
363 CLK("i2c_davinci.1", NULL, &i2c_clk),
bedad0ca
CPE		 364 CLK("davinci-mcbsp.0", NULL, &asp0_clk),
365 CLK("davinci-mcbsp.1", NULL, &asp1_clk),
d7ca4c75
MP		 366 CLK("dm6441-mmc.0", NULL, &mmcsd0_clk),
367 CLK("dm6441-mmc.1", NULL, &mmcsd1_clk),
15e86585
SP		 368 CLK("spi_davinci.0", NULL, &spi0_clk),
369 CLK("spi_davinci.1", NULL, &spi1_clk),
370 CLK("spi_davinci.2", NULL, &spi2_clk),
95a3477f
KH		 371 CLK(NULL, "gpio", &gpio_clk),
372 CLK(NULL, "aemif", &aemif_clk),
373 CLK(NULL, "pwm0", &pwm0_clk),
374 CLK(NULL, "pwm1", &pwm1_clk),
375 CLK(NULL, "pwm2", &pwm2_clk),
376 CLK(NULL, "pwm3", &pwm3_clk),
377 CLK(NULL, "timer0", &timer0_clk),
378 CLK(NULL, "timer1", &timer1_clk),
379 CLK("watchdog", NULL, &timer2_clk),
380 CLK(NULL, "timer3", &timer3_clk),
381 CLK(NULL, "rto", &rto_clk),
382 CLK(NULL, "usb", &usb_clk),
383 CLK(NULL, NULL, NULL),
384};
385
386/*----------------------------------------------------------------------*/
387
388static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);
389
390static struct resource dm355_spi0_resources[] = {
391 {
392 .start = 0x01c66000,
393 .end = 0x01c667ff,
394 .flags = IORESOURCE_MEM,
395 },
396 {
15e86585 397 .start = IRQ_DM355_SPINT0_0,
95a3477f
KH		 398 .flags = IORESOURCE_IRQ,
399 },
15e86585
SP		 400 {
401 .start = 17,
402 .flags = IORESOURCE_DMA,
403 },
404 {
405 .start = 16,
406 .flags = IORESOURCE_DMA,
407 },
95a3477f
KH		 408};
409
15e86585
SP		 410static struct davinci_spi_platform_data dm355_spi0_pdata = {
411 .version = SPI_VERSION_1,
412 .num_chipselect = 2,
c29e3c60 413 .cshold_bug = true,
2e3e2a5e 414 .dma_event_q = EVENTQ_1,
15e86585 415};
95a3477f
KH		 416static struct platform_device dm355_spi0_device = {
417 .name = "spi_davinci",
418 .id = 0,
419 .dev = {
420 .dma_mask = &dm355_spi0_dma_mask,
421 .coherent_dma_mask = DMA_BIT_MASK(32),
15e86585 422 .platform_data = &dm355_spi0_pdata,
95a3477f
KH		 423 },
424 .num_resources = ARRAY_SIZE(dm355_spi0_resources),
425 .resource = dm355_spi0_resources,
426};
427
428void __init dm355_init_spi0(unsigned chipselect_mask,
d65566e5 429 const struct spi_board_info *info, unsigned len)
95a3477f
KH		 430{
431 /* for now, assume we need MISO */
432 davinci_cfg_reg(DM355_SPI0_SDI);
433
434 /* not all slaves will be wired up */
435 if (chipselect_mask & BIT(0))
436 davinci_cfg_reg(DM355_SPI0_SDENA0);
437 if (chipselect_mask & BIT(1))
438 davinci_cfg_reg(DM355_SPI0_SDENA1);
439
440 spi_register_board_info(info, len);
441
442 platform_device_register(&dm355_spi0_device);
443}
444
445/*----------------------------------------------------------------------*/
446
5570078c
MG		 447#define INTMUX 0x18
448#define EVTMUX 0x1c
449
95a3477f
KH		 450/*
451 * Device specific mux setup
452 *
453 * soc description mux mode mode mux dbg
454 * reg offset mask mode
455 */
456static const struct mux_config dm355_pins[] = {
0e585952 457#ifdef CONFIG_DAVINCI_MUX
95a3477f
KH		 458MUX_CFG(DM355, MMCSD0, 4, 2, 1, 0, false)
459
460MUX_CFG(DM355, SD1_CLK, 3, 6, 1, 1, false)
461MUX_CFG(DM355, SD1_CMD, 3, 7, 1, 1, false)
462MUX_CFG(DM355, SD1_DATA3, 3, 8, 3, 1, false)
463MUX_CFG(DM355, SD1_DATA2, 3, 10, 3, 1, false)
464MUX_CFG(DM355, SD1_DATA1, 3, 12, 3, 1, false)
465MUX_CFG(DM355, SD1_DATA0, 3, 14, 3, 1, false)
466
467MUX_CFG(DM355, I2C_SDA, 3, 19, 1, 1, false)
468MUX_CFG(DM355, I2C_SCL, 3, 20, 1, 1, false)
469
470MUX_CFG(DM355, MCBSP0_BDX, 3, 0, 1, 1, false)
471MUX_CFG(DM355, MCBSP0_X, 3, 1, 1, 1, false)
472MUX_CFG(DM355, MCBSP0_BFSX, 3, 2, 1, 1, false)
473MUX_CFG(DM355, MCBSP0_BDR, 3, 3, 1, 1, false)
474MUX_CFG(DM355, MCBSP0_R, 3, 4, 1, 1, false)
475MUX_CFG(DM355, MCBSP0_BFSR, 3, 5, 1, 1, false)
476
477MUX_CFG(DM355, SPI0_SDI, 4, 1, 1, 0, false)
478MUX_CFG(DM355, SPI0_SDENA0, 4, 0, 1, 0, false)
479MUX_CFG(DM355, SPI0_SDENA1, 3, 28, 1, 1, false)
480
481INT_CFG(DM355, INT_EDMA_CC, 2, 1, 1, false)
482INT_CFG(DM355, INT_EDMA_TC0_ERR, 3, 1, 1, false)
483INT_CFG(DM355, INT_EDMA_TC1_ERR, 4, 1, 1, false)
484
485EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false)
486EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false)
487EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false)
1aebb50e
SP		 488
489MUX_CFG(DM355, VOUT_FIELD, 1, 18, 3, 1, false)
490MUX_CFG(DM355, VOUT_FIELD_G70, 1, 18, 3, 0, false)
491MUX_CFG(DM355, VOUT_HVSYNC, 1, 16, 1, 0, false)
492MUX_CFG(DM355, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false)
493MUX_CFG(DM355, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false)
51e68e27
MK		 494
495MUX_CFG(DM355, VIN_PCLK, 0, 14, 1, 1, false)
496MUX_CFG(DM355, VIN_CAM_WEN, 0, 13, 1, 1, false)
497MUX_CFG(DM355, VIN_CAM_VD, 0, 12, 1, 1, false)
498MUX_CFG(DM355, VIN_CAM_HD, 0, 11, 1, 1, false)
499MUX_CFG(DM355, VIN_YIN_EN, 0, 10, 1, 1, false)
500MUX_CFG(DM355, VIN_CINL_EN, 0, 0, 0xff, 0x55, false)
501MUX_CFG(DM355, VIN_CINH_EN, 0, 8, 3, 3, false)
0e585952 502#endif
95a3477f
KH		 503};
504
673dd36f
MG		 505static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
506 [IRQ_DM355_CCDC_VDINT0] = 2,
507 [IRQ_DM355_CCDC_VDINT1] = 6,
508 [IRQ_DM355_CCDC_VDINT2] = 6,
509 [IRQ_DM355_IPIPE_HST] = 6,
510 [IRQ_DM355_H3AINT] = 6,
511 [IRQ_DM355_IPIPE_SDR] = 6,
512 [IRQ_DM355_IPIPEIFINT] = 6,
513 [IRQ_DM355_OSDINT] = 7,
514 [IRQ_DM355_VENCINT] = 6,
515 [IRQ_ASQINT] = 6,
516 [IRQ_IMXINT] = 6,
517 [IRQ_USBINT] = 4,
518 [IRQ_DM355_RTOINT] = 4,
519 [IRQ_DM355_UARTINT2] = 7,
520 [IRQ_DM355_TINT6] = 7,
521 [IRQ_CCINT0] = 5, /* dma */
522 [IRQ_CCERRINT] = 5, /* dma */
523 [IRQ_TCERRINT0] = 5, /* dma */
524 [IRQ_TCERRINT] = 5, /* dma */
525 [IRQ_DM355_SPINT2_1] = 7,
526 [IRQ_DM355_TINT7] = 4,
527 [IRQ_DM355_SDIOINT0] = 7,
528 [IRQ_MBXINT] = 7,
529 [IRQ_MBRINT] = 7,
530 [IRQ_MMCINT] = 7,
531 [IRQ_DM355_MMCINT1] = 7,
532 [IRQ_DM355_PWMINT3] = 7,
533 [IRQ_DDRINT] = 7,
534 [IRQ_AEMIFINT] = 7,
535 [IRQ_DM355_SDIOINT1] = 4,
536 [IRQ_TINT0_TINT12] = 2, /* clockevent */
537 [IRQ_TINT0_TINT34] = 2, /* clocksource */
538 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
539 [IRQ_TINT1_TINT34] = 7, /* system tick */
540 [IRQ_PWMINT0] = 7,
541 [IRQ_PWMINT1] = 7,
542 [IRQ_PWMINT2] = 7,
543 [IRQ_I2C] = 3,
544 [IRQ_UARTINT0] = 3,
545 [IRQ_UARTINT1] = 3,
546 [IRQ_DM355_SPINT0_0] = 3,
547 [IRQ_DM355_SPINT0_1] = 3,
548 [IRQ_DM355_GPIO0] = 3,
549 [IRQ_DM355_GPIO1] = 7,
550 [IRQ_DM355_GPIO2] = 4,
551 [IRQ_DM355_GPIO3] = 4,
552 [IRQ_DM355_GPIO4] = 7,
553 [IRQ_DM355_GPIO5] = 7,
554 [IRQ_DM355_GPIO6] = 7,
555 [IRQ_DM355_GPIO7] = 7,
556 [IRQ_DM355_GPIO8] = 7,
557 [IRQ_DM355_GPIO9] = 7,
558 [IRQ_DM355_GPIOBNK0] = 7,
559 [IRQ_DM355_GPIOBNK1] = 7,
560 [IRQ_DM355_GPIOBNK2] = 7,
561 [IRQ_DM355_GPIOBNK3] = 7,
562 [IRQ_DM355_GPIOBNK4] = 7,
563 [IRQ_DM355_GPIOBNK5] = 7,
564 [IRQ_DM355_GPIOBNK6] = 7,
565 [IRQ_COMMTX] = 7,
566 [IRQ_COMMRX] = 7,
567 [IRQ_EMUINT] = 7,
568};
569
95a3477f
KH		 570/*----------------------------------------------------------------------*/
571
60902a2c
SR		 572static const s8
573queue_tc_mapping[][2] = {
574 /* {event queue no, TC no} */
575 {0, 0},
576 {1, 1},
577 {-1, -1},
578};
579
580static const s8
581queue_priority_mapping[][2] = {
582 /* {event queue no, Priority} */
583 {0, 3},
584 {1, 7},
585 {-1, -1},
586};
587
bc3ac9f3
SN		 588static struct edma_soc_info edma_cc0_info = {
589 .n_channel = 64,
590 .n_region = 4,
591 .n_slot = 128,
592 .n_tc = 2,
593 .n_cc = 1,
594 .queue_tc_mapping = queue_tc_mapping,
595 .queue_priority_mapping = queue_priority_mapping,
f23fe857 596 .default_queue = EVENTQ_1,
bc3ac9f3
SN		 597};
598
599static struct edma_soc_info *dm355_edma_info[EDMA_MAX_CC] = {
600 &edma_cc0_info,
95a3477f
KH		 601};
602
603static struct resource edma_resources[] = {
604 {
60902a2c 605 .name = "edma_cc0",
95a3477f
KH		 606 .start = 0x01c00000,
607 .end = 0x01c00000 + SZ_64K - 1,
608 .flags = IORESOURCE_MEM,
609 },
610 {
611 .name = "edma_tc0",
612 .start = 0x01c10000,
613 .end = 0x01c10000 + SZ_1K - 1,
614 .flags = IORESOURCE_MEM,
615 },
616 {
617 .name = "edma_tc1",
618 .start = 0x01c10400,
619 .end = 0x01c10400 + SZ_1K - 1,
620 .flags = IORESOURCE_MEM,
621 },
622 {
60902a2c 623 .name = "edma0",
95a3477f
KH		 624 .start = IRQ_CCINT0,
625 .flags = IORESOURCE_IRQ,
626 },
627 {
60902a2c 628 .name = "edma0_err",
95a3477f
KH		 629 .start = IRQ_CCERRINT,
630 .flags = IORESOURCE_IRQ,
631 },
632 /* not using (or muxing) TC*_ERR */
633};
634
635static struct platform_device dm355_edma_device = {
636 .name = "edma",
60902a2c
SR		 637 .id = 0,
638 .dev.platform_data = dm355_edma_info,
95a3477f
KH		 639 .num_resources = ARRAY_SIZE(edma_resources),
640 .resource = edma_resources,
641};
642
25acf553
C		 643static struct resource dm355_asp1_resources[] = {
644 {
645 .start = DAVINCI_ASP1_BASE,
646 .end = DAVINCI_ASP1_BASE + SZ_8K - 1,
647 .flags = IORESOURCE_MEM,
648 },
649 {
650 .start = DAVINCI_DMA_ASP1_TX,
651 .end = DAVINCI_DMA_ASP1_TX,
652 .flags = IORESOURCE_DMA,
653 },
654 {
655 .start = DAVINCI_DMA_ASP1_RX,
656 .end = DAVINCI_DMA_ASP1_RX,
657 .flags = IORESOURCE_DMA,
658 },
659};
660
661static struct platform_device dm355_asp1_device = {
bedad0ca 662 .name = "davinci-mcbsp",
61aa0732 663 .id = 1,
25acf553
C		 664 .num_resources = ARRAY_SIZE(dm355_asp1_resources),
665 .resource = dm355_asp1_resources,
666};
667
77c8b5fb
MK		 668static void dm355_ccdc_setup_pinmux(void)
669{
670 davinci_cfg_reg(DM355_VIN_PCLK);
671 davinci_cfg_reg(DM355_VIN_CAM_WEN);
672 davinci_cfg_reg(DM355_VIN_CAM_VD);
673 davinci_cfg_reg(DM355_VIN_CAM_HD);
674 davinci_cfg_reg(DM355_VIN_YIN_EN);
675 davinci_cfg_reg(DM355_VIN_CINL_EN);
676 davinci_cfg_reg(DM355_VIN_CINH_EN);
677}
678
51e68e27
MK		 679static struct resource dm355_vpss_resources[] = {
680 {
681 /* VPSS BL Base address */
682 .name = "vpss",
683 .start = 0x01c70800,
684 .end = 0x01c70800 + 0xff,
685 .flags = IORESOURCE_MEM,
686 },
687 {
688 /* VPSS CLK Base address */
689 .name = "vpss",
690 .start = 0x01c70000,
691 .end = 0x01c70000 + 0xf,
692 .flags = IORESOURCE_MEM,
693 },
694};
695
696static struct platform_device dm355_vpss_device = {
697 .name = "vpss",
698 .id = -1,
699 .dev.platform_data = "dm355_vpss",
700 .num_resources = ARRAY_SIZE(dm355_vpss_resources),
701 .resource = dm355_vpss_resources,
702};
703
704static struct resource vpfe_resources[] = {
705 {
706 .start = IRQ_VDINT0,
707 .end = IRQ_VDINT0,
708 .flags = IORESOURCE_IRQ,
709 },
710 {
711 .start = IRQ_VDINT1,
712 .end = IRQ_VDINT1,
713 .flags = IORESOURCE_IRQ,
714 },
77c8b5fb
MK		 715};
716
717static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
718static struct resource dm355_ccdc_resource[] = {
51e68e27
MK		 719 /* CCDC Base address */
720 {
721 .flags = IORESOURCE_MEM,
722 .start = 0x01c70600,
723 .end = 0x01c70600 + 0x1ff,
724 },
725};
77c8b5fb
MK		 726static struct platform_device dm355_ccdc_dev = {
727 .name = "dm355_ccdc",
728 .id = -1,
729 .num_resources = ARRAY_SIZE(dm355_ccdc_resource),
730 .resource = dm355_ccdc_resource,
731 .dev = {
732 .dma_mask = &vpfe_capture_dma_mask,
733 .coherent_dma_mask = DMA_BIT_MASK(32),
734 .platform_data = dm355_ccdc_setup_pinmux,
735 },
736};
51e68e27 737
51e68e27
MK		 738static struct platform_device vpfe_capture_dev = {
739 .name = CAPTURE_DRV_NAME,
740 .id = -1,
741 .num_resources = ARRAY_SIZE(vpfe_resources),
742 .resource = vpfe_resources,
743 .dev = {
744 .dma_mask = &vpfe_capture_dma_mask,
745 .coherent_dma_mask = DMA_BIT_MASK(32),
746 },
747};
748
62a2d6cd
LP		 749static struct resource dm355_osd_resources[] = {
750 {
751 .start = DM355_OSD_BASE,
752 .end = DM355_OSD_BASE + 0x17f,
753 .flags = IORESOURCE_MEM,
754 },
755};
756
757static struct platform_device dm355_osd_dev = {
758 .name = DM355_VPBE_OSD_SUBDEV_NAME,
759 .id = -1,
760 .num_resources = ARRAY_SIZE(dm355_osd_resources),
761 .resource = dm355_osd_resources,
762 .dev = {
763 .dma_mask = &vpfe_capture_dma_mask,
764 .coherent_dma_mask = DMA_BIT_MASK(32),
765 },
766};
767
768static struct resource dm355_venc_resources[] = {
769 {
770 .start = IRQ_VENCINT,
771 .end = IRQ_VENCINT,
772 .flags = IORESOURCE_IRQ,
773 },
774 /* venc registers io space */
775 {
776 .start = DM355_VENC_BASE,
777 .end = DM355_VENC_BASE + 0x17f,
778 .flags = IORESOURCE_MEM,
779 },
780 /* VDAC config register io space */
781 {
782 .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG,
783 .end = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3,
784 .flags = IORESOURCE_MEM,
785 },
786};
787
788static struct resource dm355_v4l2_disp_resources[] = {
789 {
790 .start = IRQ_VENCINT,
791 .end = IRQ_VENCINT,
792 .flags = IORESOURCE_IRQ,
793 },
794 /* venc registers io space */
795 {
796 .start = DM355_VENC_BASE,
797 .end = DM355_VENC_BASE + 0x17f,
798 .flags = IORESOURCE_MEM,
799 },
800};
801
802static int dm355_vpbe_setup_pinmux(enum v4l2_mbus_pixelcode if_type,
803 int field)
804{
805 switch (if_type) {
806 case V4L2_MBUS_FMT_SGRBG8_1X8:
807 davinci_cfg_reg(DM355_VOUT_FIELD_G70);
808 break;
809 case V4L2_MBUS_FMT_YUYV10_1X20:
810 if (field)
811 davinci_cfg_reg(DM355_VOUT_FIELD);
812 else
813 davinci_cfg_reg(DM355_VOUT_FIELD_G70);
814 break;
815 default:
816 return -EINVAL;
817 }
818
819 davinci_cfg_reg(DM355_VOUT_COUTL_EN);
820 davinci_cfg_reg(DM355_VOUT_COUTH_EN);
821
822 return 0;
823}
824
825static int dm355_venc_setup_clock(enum vpbe_enc_timings_type type,
826 unsigned int pclock)
51e68e27 827{
62a2d6cd
LP		 828 void __iomem *vpss_clk_ctrl_reg;
829
830 vpss_clk_ctrl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL);
831
832 switch (type) {
833 case VPBE_ENC_STD:
834 writel(VPSS_DACCLKEN_ENABLE | VPSS_VENCCLKEN_ENABLE,
835 vpss_clk_ctrl_reg);
836 break;
837 case VPBE_ENC_DV_TIMINGS:
838 if (pclock > 27000000)
839 /*
840 * For HD, use external clock source since we cannot
841 * support HD mode with internal clocks.
842 */
843 writel(VPSS_MUXSEL_EXTCLK_ENABLE, vpss_clk_ctrl_reg);
844 break;
845 default:
846 return -EINVAL;
847 }
848
849 return 0;
51e68e27
MK		 850}
851
62a2d6cd
LP		 852static struct platform_device dm355_vpbe_display = {
853 .name = "vpbe-v4l2",
854 .id = -1,
855 .num_resources = ARRAY_SIZE(dm355_v4l2_disp_resources),
856 .resource = dm355_v4l2_disp_resources,
857 .dev = {
858 .dma_mask = &vpfe_capture_dma_mask,
859 .coherent_dma_mask = DMA_BIT_MASK(32),
860 },
861};
862
863struct venc_platform_data dm355_venc_pdata = {
864 .setup_pinmux = dm355_vpbe_setup_pinmux,
865 .setup_clock = dm355_venc_setup_clock,
866};
867
868static struct platform_device dm355_venc_dev = {
869 .name = DM355_VPBE_VENC_SUBDEV_NAME,
870 .id = -1,
871 .num_resources = ARRAY_SIZE(dm355_venc_resources),
872 .resource = dm355_venc_resources,
873 .dev = {
874 .dma_mask = &vpfe_capture_dma_mask,
875 .coherent_dma_mask = DMA_BIT_MASK(32),
876 .platform_data = (void *)&dm355_venc_pdata,
877 },
878};
879
880static struct platform_device dm355_vpbe_dev = {
881 .name = "vpbe_controller",
882 .id = -1,
883 .dev = {
884 .dma_mask = &vpfe_capture_dma_mask,
885 .coherent_dma_mask = DMA_BIT_MASK(32),
886 },
887};
888
95a3477f
KH		 889/*----------------------------------------------------------------------*/
890
79c3c0b7
MG		 891static struct map_desc dm355_io_desc[] = {
892 {
893 .virtual = IO_VIRT,
894 .pfn = __phys_to_pfn(IO_PHYS),
895 .length = IO_SIZE,
896 .type = MT_DEVICE
897 },
898};
899
b9ab1279
MG		 900/* Contents of JTAG ID register used to identify exact cpu type */
901static struct davinci_id dm355_ids[] = {
902 {
903 .variant = 0x0,
904 .part_no = 0xb73b,
905 .manufacturer = 0x00f,
906 .cpu_id = DAVINCI_CPU_ID_DM355,
907 .name = "dm355",
908 },
909};
910
e4c822c7 911static u32 dm355_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
d81d188c 912
f64691b3
MG		 913/*
914 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
915 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
916 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
917 * T1_TOP: Timer 1, top : <unused>
918 */
28552c2e 919static struct davinci_timer_info dm355_timer_info = {
f64691b3
MG		 920 .timers = davinci_timer_instance,
921 .clockevent_id = T0_BOT,
922 .clocksource_id = T0_TOP,
923};
924
65e866a9
MG		 925static struct plat_serial8250_port dm355_serial_platform_data[] = {
926 {
927 .mapbase = DAVINCI_UART0_BASE,
928 .irq = IRQ_UARTINT0,
929 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
930 UPF_IOREMAP,
931 .iotype = UPIO_MEM,
932 .regshift = 2,
933 },
934 {
935 .mapbase = DAVINCI_UART1_BASE,
936 .irq = IRQ_UARTINT1,
937 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
938 UPF_IOREMAP,
939 .iotype = UPIO_MEM,
940 .regshift = 2,
941 },
942 {
943 .mapbase = DM355_UART2_BASE,
944 .irq = IRQ_DM355_UARTINT2,
945 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
946 UPF_IOREMAP,
947 .iotype = UPIO_MEM,
948 .regshift = 2,
949 },
950 {
951 .flags = 0
952 },
953};
954
955static struct platform_device dm355_serial_device = {
956 .name = "serial8250",
957 .id = PLAT8250_DEV_PLATFORM,
958 .dev = {
959 .platform_data = dm355_serial_platform_data,
960 },
961};
962
79c3c0b7
MG		 963static struct davinci_soc_info davinci_soc_info_dm355 = {
964 .io_desc = dm355_io_desc,
965 .io_desc_num = ARRAY_SIZE(dm355_io_desc),
3347db83 966 .jtag_id_reg = 0x01c40028,
b9ab1279
MG		 967 .ids = dm355_ids,
968 .ids_num = ARRAY_SIZE(dm355_ids),
66e0c399 969 .cpu_clks = dm355_clks,
d81d188c
MG		 970 .psc_bases = dm355_psc_bases,
971 .psc_bases_num = ARRAY_SIZE(dm355_psc_bases),
779b0d53 972 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
0e585952
MG		 973 .pinmux_pins = dm355_pins,
974 .pinmux_pins_num = ARRAY_SIZE(dm355_pins),
bd808947 975 .intc_base = DAVINCI_ARM_INTC_BASE,
673dd36f
MG		 976 .intc_type = DAVINCI_INTC_TYPE_AINTC,
977 .intc_irq_prios = dm355_default_priorities,
978 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
f64691b3 979 .timer_info = &dm355_timer_info,
686b634a 980 .gpio_type = GPIO_TYPE_DAVINCI,
b8d44293 981 .gpio_base = DAVINCI_GPIO_BASE,
a994955c
MG		 982 .gpio_num = 104,
983 .gpio_irq = IRQ_DM355_GPIOBNK0,
65e866a9 984 .serial_dev = &dm355_serial_device,
0d04eb47
DB		 985 .sram_dma = 0x00010000,
986 .sram_len = SZ_32K,
79c3c0b7
MG		 987};
988
25acf553
C		 989void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata)
990{
991 /* we don't use ASP1 IRQs, or we'd need to mux them ... */
992 if (evt_enable & ASP1_TX_EVT_EN)
993 davinci_cfg_reg(DM355_EVT8_ASP1_TX);
994
995 if (evt_enable & ASP1_RX_EVT_EN)
996 davinci_cfg_reg(DM355_EVT9_ASP1_RX);
997
998 dm355_asp1_device.dev.platform_data = pdata;
999 platform_device_register(&dm355_asp1_device);
1000}
1001
95a3477f
KH		 1002void __init dm355_init(void)
1003{
79c3c0b7 1004 davinci_common_init(&davinci_soc_info_dm355);
5cfb19ac 1005 davinci_map_sysmod();
95a3477f
KH		 1006}
1007
62a2d6cd
LP		 1008int __init dm355_init_video(struct vpfe_config *vpfe_cfg,
1009 struct vpbe_config *vpbe_cfg)
1010{
1011 if (vpfe_cfg || vpbe_cfg)
1012 platform_device_register(&dm355_vpss_device);
1013
1014 if (vpfe_cfg) {
1015 vpfe_capture_dev.dev.platform_data = vpfe_cfg;
1016 platform_device_register(&dm355_ccdc_dev);
1017 platform_device_register(&vpfe_capture_dev);
1018 }
1019
1020 if (vpbe_cfg) {
1021 dm355_vpbe_dev.dev.platform_data = vpbe_cfg;
1022 platform_device_register(&dm355_osd_dev);
1023 platform_device_register(&dm355_venc_dev);
1024 platform_device_register(&dm355_vpbe_dev);
1025 platform_device_register(&dm355_vpbe_display);
1026 }
1027
1028 return 0;
1029}
1030
95a3477f
KH		 1031static int __init dm355_init_devices(void)
1032{
1033 if (!cpu_is_davinci_dm355())
1034 return 0;
1035
1036 davinci_cfg_reg(DM355_INT_EDMA_CC);
1037 platform_device_register(&dm355_edma_device);
51e68e27 1038
95a3477f
KH		 1039 return 0;
1040}
1041postcore_initcall(dm355_init_devices);
Linux kernel - Deliverables
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