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DaVinci: SPI: Adding header file for SPI support.
[deliverable/linux.git] / arch / arm / mach-davinci / dm355.c
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95a3477f
KH		 1/*
2 * TI DaVinci DM355 chip specific setup
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
95a3477f
KH		 11#include <linux/init.h>
12#include <linux/clk.h>
65e866a9 13#include <linux/serial_8250.h>
95a3477f
KH		 14#include <linux/platform_device.h>
15#include <linux/dma-mapping.h>
a994955c 16#include <linux/gpio.h>
95a3477f
KH		 17
18#include <linux/spi/spi.h>
19
79c3c0b7
MG		 20#include <asm/mach/map.h>
21
95a3477f 22#include <mach/dm355.h>
95a3477f
KH		 23#include <mach/cputype.h>
24#include <mach/edma.h>
25#include <mach/psc.h>
26#include <mach/mux.h>
27#include <mach/irqs.h>
f64691b3 28#include <mach/time.h>
65e866a9 29#include <mach/serial.h>
79c3c0b7 30#include <mach/common.h>
25acf553 31#include <mach/asp.h>
95a3477f
KH		 32
33#include "clock.h"
34#include "mux.h"
35
96ed299f
KH		 36#define DM355_UART2_BASE (IO_PHYS + 0x206000)
37
95a3477f
KH		 38/*
39 * Device specific clocks
40 */
41#define DM355_REF_FREQ 24000000 /* 24 or 36 MHz */
42
43static struct pll_data pll1_data = {
44 .num = 1,
45 .phys_base = DAVINCI_PLL1_BASE,
46 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
47};
48
49static struct pll_data pll2_data = {
50 .num = 2,
51 .phys_base = DAVINCI_PLL2_BASE,
52 .flags = PLL_HAS_PREDIV,
53};
54
55static struct clk ref_clk = {
56 .name = "ref_clk",
57 /* FIXME -- crystal rate is board-specific */
58 .rate = DM355_REF_FREQ,
59};
60
61static struct clk pll1_clk = {
62 .name = "pll1",
63 .parent = &ref_clk,
64 .flags = CLK_PLL,
65 .pll_data = &pll1_data,
66};
67
68static struct clk pll1_aux_clk = {
69 .name = "pll1_aux_clk",
70 .parent = &pll1_clk,
71 .flags = CLK_PLL | PRE_PLL,
72};
73
74static struct clk pll1_sysclk1 = {
75 .name = "pll1_sysclk1",
76 .parent = &pll1_clk,
77 .flags = CLK_PLL,
78 .div_reg = PLLDIV1,
79};
80
81static struct clk pll1_sysclk2 = {
82 .name = "pll1_sysclk2",
83 .parent = &pll1_clk,
84 .flags = CLK_PLL,
85 .div_reg = PLLDIV2,
86};
87
88static struct clk pll1_sysclk3 = {
89 .name = "pll1_sysclk3",
90 .parent = &pll1_clk,
91 .flags = CLK_PLL,
92 .div_reg = PLLDIV3,
93};
94
95static struct clk pll1_sysclk4 = {
96 .name = "pll1_sysclk4",
97 .parent = &pll1_clk,
98 .flags = CLK_PLL,
99 .div_reg = PLLDIV4,
100};
101
102static struct clk pll1_sysclkbp = {
103 .name = "pll1_sysclkbp",
104 .parent = &pll1_clk,
105 .flags = CLK_PLL | PRE_PLL,
106 .div_reg = BPDIV
107};
108
109static struct clk vpss_dac_clk = {
110 .name = "vpss_dac",
111 .parent = &pll1_sysclk3,
112 .lpsc = DM355_LPSC_VPSS_DAC,
113};
114
115static struct clk vpss_master_clk = {
116 .name = "vpss_master",
117 .parent = &pll1_sysclk4,
118 .lpsc = DAVINCI_LPSC_VPSSMSTR,
119 .flags = CLK_PSC,
120};
121
122static struct clk vpss_slave_clk = {
123 .name = "vpss_slave",
124 .parent = &pll1_sysclk4,
125 .lpsc = DAVINCI_LPSC_VPSSSLV,
126};
127
128
129static struct clk clkout1_clk = {
130 .name = "clkout1",
131 .parent = &pll1_aux_clk,
132 /* NOTE: clkout1 can be externally gated by muxing GPIO-18 */
133};
134
135static struct clk clkout2_clk = {
136 .name = "clkout2",
137 .parent = &pll1_sysclkbp,
138};
139
140static struct clk pll2_clk = {
141 .name = "pll2",
142 .parent = &ref_clk,
143 .flags = CLK_PLL,
144 .pll_data = &pll2_data,
145};
146
147static struct clk pll2_sysclk1 = {
148 .name = "pll2_sysclk1",
149 .parent = &pll2_clk,
150 .flags = CLK_PLL,
151 .div_reg = PLLDIV1,
152};
153
154static struct clk pll2_sysclkbp = {
155 .name = "pll2_sysclkbp",
156 .parent = &pll2_clk,
157 .flags = CLK_PLL | PRE_PLL,
158 .div_reg = BPDIV
159};
160
161static struct clk clkout3_clk = {
162 .name = "clkout3",
163 .parent = &pll2_sysclkbp,
164 /* NOTE: clkout3 can be externally gated by muxing GPIO-16 */
165};
166
167static struct clk arm_clk = {
168 .name = "arm_clk",
169 .parent = &pll1_sysclk1,
170 .lpsc = DAVINCI_LPSC_ARM,
171 .flags = ALWAYS_ENABLED,
172};
173
174/*
175 * NOT LISTED below, and not touched by Linux
176 * - in SyncReset state by default
177 * .lpsc = DAVINCI_LPSC_TPCC,
178 * .lpsc = DAVINCI_LPSC_TPTC0,
179 * .lpsc = DAVINCI_LPSC_TPTC1,
180 * .lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk,
181 * .lpsc = DAVINCI_LPSC_MEMSTICK,
182 * - in Enabled state by default
183 * .lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS,
184 * .lpsc = DAVINCI_LPSC_SCR2, // "bus"
185 * .lpsc = DAVINCI_LPSC_SCR3, // "bus"
186 * .lpsc = DAVINCI_LPSC_SCR4, // "bus"
187 * .lpsc = DAVINCI_LPSC_CROSSBAR, // "emulation"
188 * .lpsc = DAVINCI_LPSC_CFG27, // "test"
189 * .lpsc = DAVINCI_LPSC_CFG3, // "test"
190 * .lpsc = DAVINCI_LPSC_CFG5, // "test"
191 */
192
193static struct clk mjcp_clk = {
194 .name = "mjcp",
195 .parent = &pll1_sysclk1,
196 .lpsc = DAVINCI_LPSC_IMCOP,
197};
198
199static struct clk uart0_clk = {
200 .name = "uart0",
201 .parent = &pll1_aux_clk,
202 .lpsc = DAVINCI_LPSC_UART0,
203};
204
205static struct clk uart1_clk = {
206 .name = "uart1",
207 .parent = &pll1_aux_clk,
208 .lpsc = DAVINCI_LPSC_UART1,
209};
210
211static struct clk uart2_clk = {
212 .name = "uart2",
213 .parent = &pll1_sysclk2,
214 .lpsc = DAVINCI_LPSC_UART2,
215};
216
217static struct clk i2c_clk = {
218 .name = "i2c",
219 .parent = &pll1_aux_clk,
220 .lpsc = DAVINCI_LPSC_I2C,
221};
222
223static struct clk asp0_clk = {
224 .name = "asp0",
225 .parent = &pll1_sysclk2,
226 .lpsc = DAVINCI_LPSC_McBSP,
227};
228
229static struct clk asp1_clk = {
230 .name = "asp1",
231 .parent = &pll1_sysclk2,
232 .lpsc = DM355_LPSC_McBSP1,
233};
234
235static struct clk mmcsd0_clk = {
236 .name = "mmcsd0",
237 .parent = &pll1_sysclk2,
238 .lpsc = DAVINCI_LPSC_MMC_SD,
239};
240
241static struct clk mmcsd1_clk = {
242 .name = "mmcsd1",
243 .parent = &pll1_sysclk2,
244 .lpsc = DM355_LPSC_MMC_SD1,
245};
246
247static struct clk spi0_clk = {
248 .name = "spi0",
249 .parent = &pll1_sysclk2,
250 .lpsc = DAVINCI_LPSC_SPI,
251};
252
253static struct clk spi1_clk = {
254 .name = "spi1",
255 .parent = &pll1_sysclk2,
256 .lpsc = DM355_LPSC_SPI1,
257};
258
259static struct clk spi2_clk = {
260 .name = "spi2",
261 .parent = &pll1_sysclk2,
262 .lpsc = DM355_LPSC_SPI2,
263};
264
265static struct clk gpio_clk = {
266 .name = "gpio",
267 .parent = &pll1_sysclk2,
268 .lpsc = DAVINCI_LPSC_GPIO,
269};
270
271static struct clk aemif_clk = {
272 .name = "aemif",
273 .parent = &pll1_sysclk2,
274 .lpsc = DAVINCI_LPSC_AEMIF,
275};
276
277static struct clk pwm0_clk = {
278 .name = "pwm0",
279 .parent = &pll1_aux_clk,
280 .lpsc = DAVINCI_LPSC_PWM0,
281};
282
283static struct clk pwm1_clk = {
284 .name = "pwm1",
285 .parent = &pll1_aux_clk,
286 .lpsc = DAVINCI_LPSC_PWM1,
287};
288
289static struct clk pwm2_clk = {
290 .name = "pwm2",
291 .parent = &pll1_aux_clk,
292 .lpsc = DAVINCI_LPSC_PWM2,
293};
294
295static struct clk pwm3_clk = {
296 .name = "pwm3",
297 .parent = &pll1_aux_clk,
298 .lpsc = DM355_LPSC_PWM3,
299};
300
301static struct clk timer0_clk = {
302 .name = "timer0",
303 .parent = &pll1_aux_clk,
304 .lpsc = DAVINCI_LPSC_TIMER0,
305};
306
307static struct clk timer1_clk = {
308 .name = "timer1",
309 .parent = &pll1_aux_clk,
310 .lpsc = DAVINCI_LPSC_TIMER1,
311};
312
313static struct clk timer2_clk = {
314 .name = "timer2",
315 .parent = &pll1_aux_clk,
316 .lpsc = DAVINCI_LPSC_TIMER2,
317 .usecount = 1, /* REVISIT: why cant' this be disabled? */
318};
319
320static struct clk timer3_clk = {
321 .name = "timer3",
322 .parent = &pll1_aux_clk,
323 .lpsc = DM355_LPSC_TIMER3,
324};
325
326static struct clk rto_clk = {
327 .name = "rto",
328 .parent = &pll1_aux_clk,
329 .lpsc = DM355_LPSC_RTO,
330};
331
332static struct clk usb_clk = {
333 .name = "usb",
334 .parent = &pll1_sysclk2,
335 .lpsc = DAVINCI_LPSC_USB,
336};
337
08aca087 338static struct clk_lookup dm355_clks[] = {
95a3477f
KH		 339 CLK(NULL, "ref", &ref_clk),
340 CLK(NULL, "pll1", &pll1_clk),
341 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
342 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
343 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
344 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
345 CLK(NULL, "pll1_aux", &pll1_aux_clk),
346 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
347 CLK(NULL, "vpss_dac", &vpss_dac_clk),
348 CLK(NULL, "vpss_master", &vpss_master_clk),
349 CLK(NULL, "vpss_slave", &vpss_slave_clk),
350 CLK(NULL, "clkout1", &clkout1_clk),
351 CLK(NULL, "clkout2", &clkout2_clk),
352 CLK(NULL, "pll2", &pll2_clk),
353 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
354 CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
355 CLK(NULL, "clkout3", &clkout3_clk),
356 CLK(NULL, "arm", &arm_clk),
357 CLK(NULL, "mjcp", &mjcp_clk),
358 CLK(NULL, "uart0", &uart0_clk),
359 CLK(NULL, "uart1", &uart1_clk),
360 CLK(NULL, "uart2", &uart2_clk),
361 CLK("i2c_davinci.1", NULL, &i2c_clk),
61aa0732
KH		 362 CLK("davinci-asp.0", NULL, &asp0_clk),
363 CLK("davinci-asp.1", NULL, &asp1_clk),
95a3477f
KH		 364 CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
365 CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
366 CLK(NULL, "spi0", &spi0_clk),
367 CLK(NULL, "spi1", &spi1_clk),
368 CLK(NULL, "spi2", &spi2_clk),
369 CLK(NULL, "gpio", &gpio_clk),
370 CLK(NULL, "aemif", &aemif_clk),
371 CLK(NULL, "pwm0", &pwm0_clk),
372 CLK(NULL, "pwm1", &pwm1_clk),
373 CLK(NULL, "pwm2", &pwm2_clk),
374 CLK(NULL, "pwm3", &pwm3_clk),
375 CLK(NULL, "timer0", &timer0_clk),
376 CLK(NULL, "timer1", &timer1_clk),
377 CLK("watchdog", NULL, &timer2_clk),
378 CLK(NULL, "timer3", &timer3_clk),
379 CLK(NULL, "rto", &rto_clk),
380 CLK(NULL, "usb", &usb_clk),
381 CLK(NULL, NULL, NULL),
382};
383
384/*----------------------------------------------------------------------*/
385
386static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);
387
388static struct resource dm355_spi0_resources[] = {
389 {
390 .start = 0x01c66000,
391 .end = 0x01c667ff,
392 .flags = IORESOURCE_MEM,
393 },
394 {
395 .start = IRQ_DM355_SPINT0_1,
396 .flags = IORESOURCE_IRQ,
397 },
398 /* Not yet used, so not included:
399 * IORESOURCE_IRQ:
400 * - IRQ_DM355_SPINT0_0
401 * IORESOURCE_DMA:
402 * - DAVINCI_DMA_SPI_SPIX
403 * - DAVINCI_DMA_SPI_SPIR
404 */
405};
406
407static struct platform_device dm355_spi0_device = {
408 .name = "spi_davinci",
409 .id = 0,
410 .dev = {
411 .dma_mask = &dm355_spi0_dma_mask,
412 .coherent_dma_mask = DMA_BIT_MASK(32),
413 },
414 .num_resources = ARRAY_SIZE(dm355_spi0_resources),
415 .resource = dm355_spi0_resources,
416};
417
418void __init dm355_init_spi0(unsigned chipselect_mask,
419 struct spi_board_info *info, unsigned len)
420{
421 /* for now, assume we need MISO */
422 davinci_cfg_reg(DM355_SPI0_SDI);
423
424 /* not all slaves will be wired up */
425 if (chipselect_mask & BIT(0))
426 davinci_cfg_reg(DM355_SPI0_SDENA0);
427 if (chipselect_mask & BIT(1))
428 davinci_cfg_reg(DM355_SPI0_SDENA1);
429
430 spi_register_board_info(info, len);
431
432 platform_device_register(&dm355_spi0_device);
433}
434
435/*----------------------------------------------------------------------*/
436
5570078c
MG		 437#define PINMUX0 0x00
438#define PINMUX1 0x04
439#define PINMUX2 0x08
440#define PINMUX3 0x0c
441#define PINMUX4 0x10
442#define INTMUX 0x18
443#define EVTMUX 0x1c
444
95a3477f
KH		 445/*
446 * Device specific mux setup
447 *
448 * soc description mux mode mode mux dbg
449 * reg offset mask mode
450 */
451static const struct mux_config dm355_pins[] = {
0e585952 452#ifdef CONFIG_DAVINCI_MUX
95a3477f
KH		 453MUX_CFG(DM355, MMCSD0, 4, 2, 1, 0, false)
454
455MUX_CFG(DM355, SD1_CLK, 3, 6, 1, 1, false)
456MUX_CFG(DM355, SD1_CMD, 3, 7, 1, 1, false)
457MUX_CFG(DM355, SD1_DATA3, 3, 8, 3, 1, false)
458MUX_CFG(DM355, SD1_DATA2, 3, 10, 3, 1, false)
459MUX_CFG(DM355, SD1_DATA1, 3, 12, 3, 1, false)
460MUX_CFG(DM355, SD1_DATA0, 3, 14, 3, 1, false)
461
462MUX_CFG(DM355, I2C_SDA, 3, 19, 1, 1, false)
463MUX_CFG(DM355, I2C_SCL, 3, 20, 1, 1, false)
464
465MUX_CFG(DM355, MCBSP0_BDX, 3, 0, 1, 1, false)
466MUX_CFG(DM355, MCBSP0_X, 3, 1, 1, 1, false)
467MUX_CFG(DM355, MCBSP0_BFSX, 3, 2, 1, 1, false)
468MUX_CFG(DM355, MCBSP0_BDR, 3, 3, 1, 1, false)
469MUX_CFG(DM355, MCBSP0_R, 3, 4, 1, 1, false)
470MUX_CFG(DM355, MCBSP0_BFSR, 3, 5, 1, 1, false)
471
472MUX_CFG(DM355, SPI0_SDI, 4, 1, 1, 0, false)
473MUX_CFG(DM355, SPI0_SDENA0, 4, 0, 1, 0, false)
474MUX_CFG(DM355, SPI0_SDENA1, 3, 28, 1, 1, false)
475
476INT_CFG(DM355, INT_EDMA_CC, 2, 1, 1, false)
477INT_CFG(DM355, INT_EDMA_TC0_ERR, 3, 1, 1, false)
478INT_CFG(DM355, INT_EDMA_TC1_ERR, 4, 1, 1, false)
479
480EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false)
481EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false)
482EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false)
1aebb50e
SP		 483
484MUX_CFG(DM355, VOUT_FIELD, 1, 18, 3, 1, false)
485MUX_CFG(DM355, VOUT_FIELD_G70, 1, 18, 3, 0, false)
486MUX_CFG(DM355, VOUT_HVSYNC, 1, 16, 1, 0, false)
487MUX_CFG(DM355, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false)
488MUX_CFG(DM355, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false)
51e68e27
MK		 489
490MUX_CFG(DM355, VIN_PCLK, 0, 14, 1, 1, false)
491MUX_CFG(DM355, VIN_CAM_WEN, 0, 13, 1, 1, false)
492MUX_CFG(DM355, VIN_CAM_VD, 0, 12, 1, 1, false)
493MUX_CFG(DM355, VIN_CAM_HD, 0, 11, 1, 1, false)
494MUX_CFG(DM355, VIN_YIN_EN, 0, 10, 1, 1, false)
495MUX_CFG(DM355, VIN_CINL_EN, 0, 0, 0xff, 0x55, false)
496MUX_CFG(DM355, VIN_CINH_EN, 0, 8, 3, 3, false)
0e585952 497#endif
95a3477f
KH		 498};
499
673dd36f
MG		 500static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
501 [IRQ_DM355_CCDC_VDINT0] = 2,
502 [IRQ_DM355_CCDC_VDINT1] = 6,
503 [IRQ_DM355_CCDC_VDINT2] = 6,
504 [IRQ_DM355_IPIPE_HST] = 6,
505 [IRQ_DM355_H3AINT] = 6,
506 [IRQ_DM355_IPIPE_SDR] = 6,
507 [IRQ_DM355_IPIPEIFINT] = 6,
508 [IRQ_DM355_OSDINT] = 7,
509 [IRQ_DM355_VENCINT] = 6,
510 [IRQ_ASQINT] = 6,
511 [IRQ_IMXINT] = 6,
512 [IRQ_USBINT] = 4,
513 [IRQ_DM355_RTOINT] = 4,
514 [IRQ_DM355_UARTINT2] = 7,
515 [IRQ_DM355_TINT6] = 7,
516 [IRQ_CCINT0] = 5, /* dma */
517 [IRQ_CCERRINT] = 5, /* dma */
518 [IRQ_TCERRINT0] = 5, /* dma */
519 [IRQ_TCERRINT] = 5, /* dma */
520 [IRQ_DM355_SPINT2_1] = 7,
521 [IRQ_DM355_TINT7] = 4,
522 [IRQ_DM355_SDIOINT0] = 7,
523 [IRQ_MBXINT] = 7,
524 [IRQ_MBRINT] = 7,
525 [IRQ_MMCINT] = 7,
526 [IRQ_DM355_MMCINT1] = 7,
527 [IRQ_DM355_PWMINT3] = 7,
528 [IRQ_DDRINT] = 7,
529 [IRQ_AEMIFINT] = 7,
530 [IRQ_DM355_SDIOINT1] = 4,
531 [IRQ_TINT0_TINT12] = 2, /* clockevent */
532 [IRQ_TINT0_TINT34] = 2, /* clocksource */
533 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
534 [IRQ_TINT1_TINT34] = 7, /* system tick */
535 [IRQ_PWMINT0] = 7,
536 [IRQ_PWMINT1] = 7,
537 [IRQ_PWMINT2] = 7,
538 [IRQ_I2C] = 3,
539 [IRQ_UARTINT0] = 3,
540 [IRQ_UARTINT1] = 3,
541 [IRQ_DM355_SPINT0_0] = 3,
542 [IRQ_DM355_SPINT0_1] = 3,
543 [IRQ_DM355_GPIO0] = 3,
544 [IRQ_DM355_GPIO1] = 7,
545 [IRQ_DM355_GPIO2] = 4,
546 [IRQ_DM355_GPIO3] = 4,
547 [IRQ_DM355_GPIO4] = 7,
548 [IRQ_DM355_GPIO5] = 7,
549 [IRQ_DM355_GPIO6] = 7,
550 [IRQ_DM355_GPIO7] = 7,
551 [IRQ_DM355_GPIO8] = 7,
552 [IRQ_DM355_GPIO9] = 7,
553 [IRQ_DM355_GPIOBNK0] = 7,
554 [IRQ_DM355_GPIOBNK1] = 7,
555 [IRQ_DM355_GPIOBNK2] = 7,
556 [IRQ_DM355_GPIOBNK3] = 7,
557 [IRQ_DM355_GPIOBNK4] = 7,
558 [IRQ_DM355_GPIOBNK5] = 7,
559 [IRQ_DM355_GPIOBNK6] = 7,
560 [IRQ_COMMTX] = 7,
561 [IRQ_COMMRX] = 7,
562 [IRQ_EMUINT] = 7,
563};
564
95a3477f
KH		 565/*----------------------------------------------------------------------*/
566
60902a2c
SR		 567static const s8
568queue_tc_mapping[][2] = {
569 /* {event queue no, TC no} */
570 {0, 0},
571 {1, 1},
572 {-1, -1},
573};
574
575static const s8
576queue_priority_mapping[][2] = {
577 /* {event queue no, Priority} */
578 {0, 3},
579 {1, 7},
580 {-1, -1},
581};
582
583static struct edma_soc_info dm355_edma_info[] = {
584 {
585 .n_channel = 64,
586 .n_region = 4,
587 .n_slot = 128,
588 .n_tc = 2,
589 .n_cc = 1,
60902a2c
SR		 590 .queue_tc_mapping = queue_tc_mapping,
591 .queue_priority_mapping = queue_priority_mapping,
592 },
95a3477f
KH		 593};
594
595static struct resource edma_resources[] = {
596 {
60902a2c 597 .name = "edma_cc0",
95a3477f
KH		 598 .start = 0x01c00000,
599 .end = 0x01c00000 + SZ_64K - 1,
600 .flags = IORESOURCE_MEM,
601 },
602 {
603 .name = "edma_tc0",
604 .start = 0x01c10000,
605 .end = 0x01c10000 + SZ_1K - 1,
606 .flags = IORESOURCE_MEM,
607 },
608 {
609 .name = "edma_tc1",
610 .start = 0x01c10400,
611 .end = 0x01c10400 + SZ_1K - 1,
612 .flags = IORESOURCE_MEM,
613 },
614 {
60902a2c 615 .name = "edma0",
95a3477f
KH		 616 .start = IRQ_CCINT0,
617 .flags = IORESOURCE_IRQ,
618 },
619 {
60902a2c 620 .name = "edma0_err",
95a3477f
KH		 621 .start = IRQ_CCERRINT,
622 .flags = IORESOURCE_IRQ,
623 },
624 /* not using (or muxing) TC*_ERR */
625};
626
627static struct platform_device dm355_edma_device = {
628 .name = "edma",
60902a2c
SR		 629 .id = 0,
630 .dev.platform_data = dm355_edma_info,
95a3477f
KH		 631 .num_resources = ARRAY_SIZE(edma_resources),
632 .resource = edma_resources,
633};
634
25acf553
C		 635static struct resource dm355_asp1_resources[] = {
636 {
637 .start = DAVINCI_ASP1_BASE,
638 .end = DAVINCI_ASP1_BASE + SZ_8K - 1,
639 .flags = IORESOURCE_MEM,
640 },
641 {
642 .start = DAVINCI_DMA_ASP1_TX,
643 .end = DAVINCI_DMA_ASP1_TX,
644 .flags = IORESOURCE_DMA,
645 },
646 {
647 .start = DAVINCI_DMA_ASP1_RX,
648 .end = DAVINCI_DMA_ASP1_RX,
649 .flags = IORESOURCE_DMA,
650 },
651};
652
653static struct platform_device dm355_asp1_device = {
654 .name = "davinci-asp",
61aa0732 655 .id = 1,
25acf553
C		 656 .num_resources = ARRAY_SIZE(dm355_asp1_resources),
657 .resource = dm355_asp1_resources,
658};
659
51e68e27
MK		 660static struct resource dm355_vpss_resources[] = {
661 {
662 /* VPSS BL Base address */
663 .name = "vpss",
664 .start = 0x01c70800,
665 .end = 0x01c70800 + 0xff,
666 .flags = IORESOURCE_MEM,
667 },
668 {
669 /* VPSS CLK Base address */
670 .name = "vpss",
671 .start = 0x01c70000,
672 .end = 0x01c70000 + 0xf,
673 .flags = IORESOURCE_MEM,
674 },
675};
676
677static struct platform_device dm355_vpss_device = {
678 .name = "vpss",
679 .id = -1,
680 .dev.platform_data = "dm355_vpss",
681 .num_resources = ARRAY_SIZE(dm355_vpss_resources),
682 .resource = dm355_vpss_resources,
683};
684
685static struct resource vpfe_resources[] = {
686 {
687 .start = IRQ_VDINT0,
688 .end = IRQ_VDINT0,
689 .flags = IORESOURCE_IRQ,
690 },
691 {
692 .start = IRQ_VDINT1,
693 .end = IRQ_VDINT1,
694 .flags = IORESOURCE_IRQ,
695 },
696 /* CCDC Base address */
697 {
698 .flags = IORESOURCE_MEM,
699 .start = 0x01c70600,
700 .end = 0x01c70600 + 0x1ff,
701 },
702};
703
704static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
705static struct platform_device vpfe_capture_dev = {
706 .name = CAPTURE_DRV_NAME,
707 .id = -1,
708 .num_resources = ARRAY_SIZE(vpfe_resources),
709 .resource = vpfe_resources,
710 .dev = {
711 .dma_mask = &vpfe_capture_dma_mask,
712 .coherent_dma_mask = DMA_BIT_MASK(32),
713 },
714};
715
716void dm355_set_vpfe_config(struct vpfe_config *cfg)
717{
718 vpfe_capture_dev.dev.platform_data = cfg;
719}
720
95a3477f
KH		 721/*----------------------------------------------------------------------*/
722
79c3c0b7
MG		 723static struct map_desc dm355_io_desc[] = {
724 {
725 .virtual = IO_VIRT,
726 .pfn = __phys_to_pfn(IO_PHYS),
727 .length = IO_SIZE,
728 .type = MT_DEVICE
729 },
0d04eb47
DB		 730 {
731 .virtual = SRAM_VIRT,
732 .pfn = __phys_to_pfn(0x00010000),
733 .length = SZ_32K,
734 /* MT_MEMORY_NONCACHED requires supersection alignment */
735 .type = MT_DEVICE,
736 },
79c3c0b7
MG		 737};
738
b9ab1279
MG		 739/* Contents of JTAG ID register used to identify exact cpu type */
740static struct davinci_id dm355_ids[] = {
741 {
742 .variant = 0x0,
743 .part_no = 0xb73b,
744 .manufacturer = 0x00f,
745 .cpu_id = DAVINCI_CPU_ID_DM355,
746 .name = "dm355",
747 },
748};
749
d81d188c
MG		 750static void __iomem *dm355_psc_bases[] = {
751 IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
752};
753
f64691b3
MG		 754/*
755 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
756 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
757 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
758 * T1_TOP: Timer 1, top : <unused>
759 */
760struct davinci_timer_info dm355_timer_info = {
761 .timers = davinci_timer_instance,
762 .clockevent_id = T0_BOT,
763 .clocksource_id = T0_TOP,
764};
765
65e866a9
MG		 766static struct plat_serial8250_port dm355_serial_platform_data[] = {
767 {
768 .mapbase = DAVINCI_UART0_BASE,
769 .irq = IRQ_UARTINT0,
770 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
771 UPF_IOREMAP,
772 .iotype = UPIO_MEM,
773 .regshift = 2,
774 },
775 {
776 .mapbase = DAVINCI_UART1_BASE,
777 .irq = IRQ_UARTINT1,
778 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
779 UPF_IOREMAP,
780 .iotype = UPIO_MEM,
781 .regshift = 2,
782 },
783 {
784 .mapbase = DM355_UART2_BASE,
785 .irq = IRQ_DM355_UARTINT2,
786 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
787 UPF_IOREMAP,
788 .iotype = UPIO_MEM,
789 .regshift = 2,
790 },
791 {
792 .flags = 0
793 },
794};
795
796static struct platform_device dm355_serial_device = {
797 .name = "serial8250",
798 .id = PLAT8250_DEV_PLATFORM,
799 .dev = {
800 .platform_data = dm355_serial_platform_data,
801 },
802};
803
79c3c0b7
MG		 804static struct davinci_soc_info davinci_soc_info_dm355 = {
805 .io_desc = dm355_io_desc,
806 .io_desc_num = ARRAY_SIZE(dm355_io_desc),
b9ab1279
MG		 807 .jtag_id_base = IO_ADDRESS(0x01c40028),
808 .ids = dm355_ids,
809 .ids_num = ARRAY_SIZE(dm355_ids),
66e0c399 810 .cpu_clks = dm355_clks,
d81d188c
MG		 811 .psc_bases = dm355_psc_bases,
812 .psc_bases_num = ARRAY_SIZE(dm355_psc_bases),
0e585952
MG		 813 .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
814 .pinmux_pins = dm355_pins,
815 .pinmux_pins_num = ARRAY_SIZE(dm355_pins),
673dd36f
MG		 816 .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
817 .intc_type = DAVINCI_INTC_TYPE_AINTC,
818 .intc_irq_prios = dm355_default_priorities,
819 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
f64691b3 820 .timer_info = &dm355_timer_info,
a994955c
MG		 821 .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE),
822 .gpio_num = 104,
823 .gpio_irq = IRQ_DM355_GPIOBNK0,
65e866a9 824 .serial_dev = &dm355_serial_device,
0d04eb47
DB		 825 .sram_dma = 0x00010000,
826 .sram_len = SZ_32K,
79c3c0b7
MG		 827};
828
25acf553
C		 829void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata)
830{
831 /* we don't use ASP1 IRQs, or we'd need to mux them ... */
832 if (evt_enable & ASP1_TX_EVT_EN)
833 davinci_cfg_reg(DM355_EVT8_ASP1_TX);
834
835 if (evt_enable & ASP1_RX_EVT_EN)
836 davinci_cfg_reg(DM355_EVT9_ASP1_RX);
837
838 dm355_asp1_device.dev.platform_data = pdata;
839 platform_device_register(&dm355_asp1_device);
840}
841
95a3477f
KH		 842void __init dm355_init(void)
843{
79c3c0b7 844 davinci_common_init(&davinci_soc_info_dm355);
95a3477f
KH		 845}
846
847static int __init dm355_init_devices(void)
848{
849 if (!cpu_is_davinci_dm355())
850 return 0;
851
852 davinci_cfg_reg(DM355_INT_EDMA_CC);
853 platform_device_register(&dm355_edma_device);
51e68e27
MK		 854 platform_device_register(&dm355_vpss_device);
855 /*
856 * setup Mux configuration for vpfe input and register
857 * vpfe capture platform device
858 */
859 davinci_cfg_reg(DM355_VIN_PCLK);
860 davinci_cfg_reg(DM355_VIN_CAM_WEN);
861 davinci_cfg_reg(DM355_VIN_CAM_VD);
862 davinci_cfg_reg(DM355_VIN_CAM_HD);
863 davinci_cfg_reg(DM355_VIN_YIN_EN);
864 davinci_cfg_reg(DM355_VIN_CINL_EN);
865 davinci_cfg_reg(DM355_VIN_CINH_EN);
866 platform_device_register(&vpfe_capture_dev);
867
95a3477f
KH		 868 return 0;
869}
870postcore_initcall(dm355_init_devices);
Linux kernel - Deliverables
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