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Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
[deliverable/linux.git] / arch / arm / mach-davinci / dm365.c
CommitLineData
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SP		 1/*
2 * TI DaVinci DM365 chip specific setup
3 *
4 * Copyright (C) 2009 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
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SP		 15#include <linux/init.h>
16#include <linux/clk.h>
17#include <linux/serial_8250.h>
18#include <linux/platform_device.h>
19#include <linux/dma-mapping.h>
a3e13e89 20#include <linux/spi/spi.h>
3ad7a42d 21#include <linux/platform_data/edma.h>
9cc1515c
PA		 22#include <linux/platform_data/gpio-davinci.h>
23#include <linux/platform_data/keyscan-davinci.h>
24#include <linux/platform_data/spi-davinci.h>
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SP		 25
26#include <asm/mach/map.h>
27
fb8fcb89 28#include <mach/cputype.h>
3acf731c 29#include "psc.h"
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SP		 30#include <mach/mux.h>
31#include <mach/irqs.h>
32#include <mach/time.h>
33#include <mach/serial.h>
34#include <mach/common.h>
35
39c6d2d1 36#include "davinci.h"
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SP		 37#include "clock.h"
38#include "mux.h"
896f66b7 39#include "asp.h"
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SP		 40
41#define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */
719f56f2 42#define DM365_RTC_BASE 0x01c69000
120c6604
LP		 43#define DM365_KEYSCAN_BASE 0x01c69400
44#define DM365_OSD_BASE 0x01c71c00
45#define DM365_VENC_BASE 0x01c71e00
719f56f2
MH		 46#define DAVINCI_DM365_VC_BASE 0x01d0c000
47#define DAVINCI_DMA_VC_TX 2
48#define DAVINCI_DMA_VC_RX 3
719f56f2
MH		 49#define DM365_EMAC_BASE 0x01d07000
50#define DM365_EMAC_MDIO_BASE (DM365_EMAC_BASE + 0x4000)
51#define DM365_EMAC_CNTRL_OFFSET 0x0000
52#define DM365_EMAC_CNTRL_MOD_OFFSET 0x3000
53#define DM365_EMAC_CNTRL_RAM_OFFSET 0x1000
54#define DM365_EMAC_CNTRL_RAM_SIZE 0x2000
55
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SP		 56static struct pll_data pll1_data = {
57 .num = 1,
58 .phys_base = DAVINCI_PLL1_BASE,
59 .flags = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
60};
61
62static struct pll_data pll2_data = {
63 .num = 2,
64 .phys_base = DAVINCI_PLL2_BASE,
65 .flags = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
66};
67
68static struct clk ref_clk = {
69 .name = "ref_clk",
70 .rate = DM365_REF_FREQ,
71};
72
73static struct clk pll1_clk = {
74 .name = "pll1",
75 .parent = &ref_clk,
76 .flags = CLK_PLL,
77 .pll_data = &pll1_data,
78};
79
80static struct clk pll1_aux_clk = {
81 .name = "pll1_aux_clk",
82 .parent = &pll1_clk,
83 .flags = CLK_PLL | PRE_PLL,
84};
85
86static struct clk pll1_sysclkbp = {
87 .name = "pll1_sysclkbp",
88 .parent = &pll1_clk,
89 .flags = CLK_PLL | PRE_PLL,
90 .div_reg = BPDIV
91};
92
93static struct clk clkout0_clk = {
94 .name = "clkout0",
95 .parent = &pll1_clk,
96 .flags = CLK_PLL | PRE_PLL,
97};
98
99static struct clk pll1_sysclk1 = {
100 .name = "pll1_sysclk1",
101 .parent = &pll1_clk,
102 .flags = CLK_PLL,
103 .div_reg = PLLDIV1,
104};
105
106static struct clk pll1_sysclk2 = {
107 .name = "pll1_sysclk2",
108 .parent = &pll1_clk,
109 .flags = CLK_PLL,
110 .div_reg = PLLDIV2,
111};
112
113static struct clk pll1_sysclk3 = {
114 .name = "pll1_sysclk3",
115 .parent = &pll1_clk,
116 .flags = CLK_PLL,
117 .div_reg = PLLDIV3,
118};
119
120static struct clk pll1_sysclk4 = {
121 .name = "pll1_sysclk4",
122 .parent = &pll1_clk,
123 .flags = CLK_PLL,
124 .div_reg = PLLDIV4,
125};
126
127static struct clk pll1_sysclk5 = {
128 .name = "pll1_sysclk5",
129 .parent = &pll1_clk,
130 .flags = CLK_PLL,
131 .div_reg = PLLDIV5,
132};
133
134static struct clk pll1_sysclk6 = {
135 .name = "pll1_sysclk6",
136 .parent = &pll1_clk,
137 .flags = CLK_PLL,
138 .div_reg = PLLDIV6,
139};
140
141static struct clk pll1_sysclk7 = {
142 .name = "pll1_sysclk7",
143 .parent = &pll1_clk,
144 .flags = CLK_PLL,
145 .div_reg = PLLDIV7,
146};
147
148static struct clk pll1_sysclk8 = {
149 .name = "pll1_sysclk8",
150 .parent = &pll1_clk,
151 .flags = CLK_PLL,
152 .div_reg = PLLDIV8,
153};
154
155static struct clk pll1_sysclk9 = {
156 .name = "pll1_sysclk9",
157 .parent = &pll1_clk,
158 .flags = CLK_PLL,
159 .div_reg = PLLDIV9,
160};
161
162static struct clk pll2_clk = {
163 .name = "pll2",
164 .parent = &ref_clk,
165 .flags = CLK_PLL,
166 .pll_data = &pll2_data,
167};
168
169static struct clk pll2_aux_clk = {
170 .name = "pll2_aux_clk",
171 .parent = &pll2_clk,
172 .flags = CLK_PLL | PRE_PLL,
173};
174
175static struct clk clkout1_clk = {
176 .name = "clkout1",
177 .parent = &pll2_clk,
178 .flags = CLK_PLL | PRE_PLL,
179};
180
181static struct clk pll2_sysclk1 = {
182 .name = "pll2_sysclk1",
183 .parent = &pll2_clk,
184 .flags = CLK_PLL,
185 .div_reg = PLLDIV1,
186};
187
188static struct clk pll2_sysclk2 = {
189 .name = "pll2_sysclk2",
190 .parent = &pll2_clk,
191 .flags = CLK_PLL,
192 .div_reg = PLLDIV2,
193};
194
195static struct clk pll2_sysclk3 = {
196 .name = "pll2_sysclk3",
197 .parent = &pll2_clk,
198 .flags = CLK_PLL,
199 .div_reg = PLLDIV3,
200};
201
202static struct clk pll2_sysclk4 = {
203 .name = "pll2_sysclk4",
204 .parent = &pll2_clk,
205 .flags = CLK_PLL,
206 .div_reg = PLLDIV4,
207};
208
209static struct clk pll2_sysclk5 = {
210 .name = "pll2_sysclk5",
211 .parent = &pll2_clk,
212 .flags = CLK_PLL,
213 .div_reg = PLLDIV5,
214};
215
216static struct clk pll2_sysclk6 = {
217 .name = "pll2_sysclk6",
218 .parent = &pll2_clk,
219 .flags = CLK_PLL,
220 .div_reg = PLLDIV6,
221};
222
223static struct clk pll2_sysclk7 = {
224 .name = "pll2_sysclk7",
225 .parent = &pll2_clk,
226 .flags = CLK_PLL,
227 .div_reg = PLLDIV7,
228};
229
230static struct clk pll2_sysclk8 = {
231 .name = "pll2_sysclk8",
232 .parent = &pll2_clk,
233 .flags = CLK_PLL,
234 .div_reg = PLLDIV8,
235};
236
237static struct clk pll2_sysclk9 = {
238 .name = "pll2_sysclk9",
239 .parent = &pll2_clk,
240 .flags = CLK_PLL,
241 .div_reg = PLLDIV9,
242};
243
244static struct clk vpss_dac_clk = {
245 .name = "vpss_dac",
246 .parent = &pll1_sysclk3,
247 .lpsc = DM365_LPSC_DAC_CLK,
248};
249
250static struct clk vpss_master_clk = {
251 .name = "vpss_master",
252 .parent = &pll1_sysclk5,
253 .lpsc = DM365_LPSC_VPSSMSTR,
254 .flags = CLK_PSC,
255};
256
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LP		 257static struct clk vpss_slave_clk = {
258 .name = "vpss_slave",
259 .parent = &pll1_sysclk5,
260 .lpsc = DAVINCI_LPSC_VPSSSLV,
261};
262
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SP		 263static struct clk arm_clk = {
264 .name = "arm_clk",
265 .parent = &pll2_sysclk2,
266 .lpsc = DAVINCI_LPSC_ARM,
267 .flags = ALWAYS_ENABLED,
268};
269
270static struct clk uart0_clk = {
271 .name = "uart0",
272 .parent = &pll1_aux_clk,
273 .lpsc = DAVINCI_LPSC_UART0,
274};
275
276static struct clk uart1_clk = {
277 .name = "uart1",
278 .parent = &pll1_sysclk4,
279 .lpsc = DAVINCI_LPSC_UART1,
280};
281
282static struct clk i2c_clk = {
283 .name = "i2c",
284 .parent = &pll1_aux_clk,
285 .lpsc = DAVINCI_LPSC_I2C,
286};
287
288static struct clk mmcsd0_clk = {
289 .name = "mmcsd0",
290 .parent = &pll1_sysclk8,
291 .lpsc = DAVINCI_LPSC_MMC_SD,
292};
293
294static struct clk mmcsd1_clk = {
295 .name = "mmcsd1",
296 .parent = &pll1_sysclk4,
297 .lpsc = DM365_LPSC_MMC_SD1,
298};
299
300static struct clk spi0_clk = {
301 .name = "spi0",
302 .parent = &pll1_sysclk4,
303 .lpsc = DAVINCI_LPSC_SPI,
304};
305
306static struct clk spi1_clk = {
307 .name = "spi1",
308 .parent = &pll1_sysclk4,
309 .lpsc = DM365_LPSC_SPI1,
310};
311
312static struct clk spi2_clk = {
313 .name = "spi2",
314 .parent = &pll1_sysclk4,
315 .lpsc = DM365_LPSC_SPI2,
316};
317
318static struct clk spi3_clk = {
319 .name = "spi3",
320 .parent = &pll1_sysclk4,
321 .lpsc = DM365_LPSC_SPI3,
322};
323
324static struct clk spi4_clk = {
325 .name = "spi4",
326 .parent = &pll1_aux_clk,
327 .lpsc = DM365_LPSC_SPI4,
328};
329
330static struct clk gpio_clk = {
331 .name = "gpio",
332 .parent = &pll1_sysclk4,
333 .lpsc = DAVINCI_LPSC_GPIO,
334};
335
336static struct clk aemif_clk = {
337 .name = "aemif",
338 .parent = &pll1_sysclk4,
339 .lpsc = DAVINCI_LPSC_AEMIF,
340};
341
342static struct clk pwm0_clk = {
343 .name = "pwm0",
344 .parent = &pll1_aux_clk,
345 .lpsc = DAVINCI_LPSC_PWM0,
346};
347
348static struct clk pwm1_clk = {
349 .name = "pwm1",
350 .parent = &pll1_aux_clk,
351 .lpsc = DAVINCI_LPSC_PWM1,
352};
353
354static struct clk pwm2_clk = {
355 .name = "pwm2",
356 .parent = &pll1_aux_clk,
357 .lpsc = DAVINCI_LPSC_PWM2,
358};
359
360static struct clk pwm3_clk = {
361 .name = "pwm3",
362 .parent = &ref_clk,
363 .lpsc = DM365_LPSC_PWM3,
364};
365
366static struct clk timer0_clk = {
367 .name = "timer0",
368 .parent = &pll1_aux_clk,
369 .lpsc = DAVINCI_LPSC_TIMER0,
370};
371
372static struct clk timer1_clk = {
373 .name = "timer1",
374 .parent = &pll1_aux_clk,
375 .lpsc = DAVINCI_LPSC_TIMER1,
376};
377
378static struct clk timer2_clk = {
379 .name = "timer2",
380 .parent = &pll1_aux_clk,
381 .lpsc = DAVINCI_LPSC_TIMER2,
382 .usecount = 1,
383};
384
385static struct clk timer3_clk = {
386 .name = "timer3",
387 .parent = &pll1_aux_clk,
388 .lpsc = DM365_LPSC_TIMER3,
389};
390
391static struct clk usb_clk = {
392 .name = "usb",
ed160672 393 .parent = &pll1_aux_clk,
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SP		 394 .lpsc = DAVINCI_LPSC_USB,
395};
396
397static struct clk emac_clk = {
398 .name = "emac",
399 .parent = &pll1_sysclk4,
400 .lpsc = DM365_LPSC_EMAC,
401};
402
403static struct clk voicecodec_clk = {
404 .name = "voice_codec",
405 .parent = &pll2_sysclk4,
406 .lpsc = DM365_LPSC_VOICE_CODEC,
407};
408
409static struct clk asp0_clk = {
410 .name = "asp0",
411 .parent = &pll1_sysclk4,
412 .lpsc = DM365_LPSC_McBSP1,
413};
414
415static struct clk rto_clk = {
416 .name = "rto",
417 .parent = &pll1_sysclk4,
418 .lpsc = DM365_LPSC_RTO,
419};
420
421static struct clk mjcp_clk = {
422 .name = "mjcp",
423 .parent = &pll1_sysclk3,
424 .lpsc = DM365_LPSC_MJCP,
425};
426
08aca087 427static struct clk_lookup dm365_clks[] = {
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SP		 428 CLK(NULL, "ref", &ref_clk),
429 CLK(NULL, "pll1", &pll1_clk),
430 CLK(NULL, "pll1_aux", &pll1_aux_clk),
431 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
432 CLK(NULL, "clkout0", &clkout0_clk),
433 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
434 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
435 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
436 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
437 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
438 CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
439 CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
440 CLK(NULL, "pll1_sysclk8", &pll1_sysclk8),
441 CLK(NULL, "pll1_sysclk9", &pll1_sysclk9),
442 CLK(NULL, "pll2", &pll2_clk),
443 CLK(NULL, "pll2_aux", &pll2_aux_clk),
444 CLK(NULL, "clkout1", &clkout1_clk),
445 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
446 CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
447 CLK(NULL, "pll2_sysclk3", &pll2_sysclk3),
448 CLK(NULL, "pll2_sysclk4", &pll2_sysclk4),
449 CLK(NULL, "pll2_sysclk5", &pll2_sysclk5),
450 CLK(NULL, "pll2_sysclk6", &pll2_sysclk6),
451 CLK(NULL, "pll2_sysclk7", &pll2_sysclk7),
452 CLK(NULL, "pll2_sysclk8", &pll2_sysclk8),
453 CLK(NULL, "pll2_sysclk9", &pll2_sysclk9),
454 CLK(NULL, "vpss_dac", &vpss_dac_clk),
9a3e89b1
LP		 455 CLK("vpss", "master", &vpss_master_clk),
456 CLK("vpss", "slave", &vpss_slave_clk),
fb8fcb89 457 CLK(NULL, "arm", &arm_clk),
19955c3d
MP		 458 CLK("serial8250.0", NULL, &uart0_clk),
459 CLK("serial8250.1", NULL, &uart1_clk),
fb8fcb89 460 CLK("i2c_davinci.1", NULL, &i2c_clk),
d7ca4c75
MP		 461 CLK("da830-mmc.0", NULL, &mmcsd0_clk),
462 CLK("da830-mmc.1", NULL, &mmcsd1_clk),
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SP		 463 CLK("spi_davinci.0", NULL, &spi0_clk),
464 CLK("spi_davinci.1", NULL, &spi1_clk),
465 CLK("spi_davinci.2", NULL, &spi2_clk),
466 CLK("spi_davinci.3", NULL, &spi3_clk),
467 CLK("spi_davinci.4", NULL, &spi4_clk),
468 CLK(NULL, "gpio", &gpio_clk),
469 CLK(NULL, "aemif", &aemif_clk),
470 CLK(NULL, "pwm0", &pwm0_clk),
471 CLK(NULL, "pwm1", &pwm1_clk),
472 CLK(NULL, "pwm2", &pwm2_clk),
473 CLK(NULL, "pwm3", &pwm3_clk),
474 CLK(NULL, "timer0", &timer0_clk),
475 CLK(NULL, "timer1", &timer1_clk),
84374812 476 CLK("davinci-wdt", NULL, &timer2_clk),
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SP		 477 CLK(NULL, "timer3", &timer3_clk),
478 CLK(NULL, "usb", &usb_clk),
479 CLK("davinci_emac.1", NULL, &emac_clk),
46c18334 480 CLK("davinci_mdio.0", "fck", &emac_clk),
e89861e9 481 CLK("davinci_voicecodec", NULL, &voicecodec_clk),
bedad0ca 482 CLK("davinci-mcbsp", NULL, &asp0_clk),
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SP		 483 CLK(NULL, "rto", &rto_clk),
484 CLK(NULL, "mjcp", &mjcp_clk),
485 CLK(NULL, NULL, NULL),
486};
487
488/*----------------------------------------------------------------------*/
489
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SP		 490#define INTMUX 0x18
491#define EVTMUX 0x1c
492
493
494static const struct mux_config dm365_pins[] = {
495#ifdef CONFIG_DAVINCI_MUX
496MUX_CFG(DM365, MMCSD0, 0, 24, 1, 0, false)
497
498MUX_CFG(DM365, SD1_CLK, 0, 16, 3, 1, false)
499MUX_CFG(DM365, SD1_CMD, 4, 30, 3, 1, false)
500MUX_CFG(DM365, SD1_DATA3, 4, 28, 3, 1, false)
501MUX_CFG(DM365, SD1_DATA2, 4, 26, 3, 1, false)
502MUX_CFG(DM365, SD1_DATA1, 4, 24, 3, 1, false)
503MUX_CFG(DM365, SD1_DATA0, 4, 22, 3, 1, false)
504
505MUX_CFG(DM365, I2C_SDA, 3, 23, 3, 2, false)
506MUX_CFG(DM365, I2C_SCL, 3, 21, 3, 2, false)
507
7735227e
TK		 508MUX_CFG(DM365, AEMIF_AR_A14, 2, 0, 3, 1, false)
509MUX_CFG(DM365, AEMIF_AR_BA0, 2, 0, 3, 2, false)
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SP		 510MUX_CFG(DM365, AEMIF_A3, 2, 2, 3, 1, false)
511MUX_CFG(DM365, AEMIF_A7, 2, 4, 3, 1, false)
512MUX_CFG(DM365, AEMIF_D15_8, 2, 6, 1, 1, false)
513MUX_CFG(DM365, AEMIF_CE0, 2, 7, 1, 0, false)
7735227e
TK		 514MUX_CFG(DM365, AEMIF_CE1, 2, 8, 1, 0, false)
515MUX_CFG(DM365, AEMIF_WE_OE, 2, 9, 1, 0, false)
fb8fcb89
SP		 516
517MUX_CFG(DM365, MCBSP0_BDX, 0, 23, 1, 1, false)
518MUX_CFG(DM365, MCBSP0_X, 0, 22, 1, 1, false)
519MUX_CFG(DM365, MCBSP0_BFSX, 0, 21, 1, 1, false)
520MUX_CFG(DM365, MCBSP0_BDR, 0, 20, 1, 1, false)
521MUX_CFG(DM365, MCBSP0_R, 0, 19, 1, 1, false)
522MUX_CFG(DM365, MCBSP0_BFSR, 0, 18, 1, 1, false)
523
524MUX_CFG(DM365, SPI0_SCLK, 3, 28, 1, 1, false)
525MUX_CFG(DM365, SPI0_SDI, 3, 26, 3, 1, false)
526MUX_CFG(DM365, SPI0_SDO, 3, 25, 1, 1, false)
527MUX_CFG(DM365, SPI0_SDENA0, 3, 29, 3, 1, false)
528MUX_CFG(DM365, SPI0_SDENA1, 3, 26, 3, 2, false)
529
530MUX_CFG(DM365, UART0_RXD, 3, 20, 1, 1, false)
531MUX_CFG(DM365, UART0_TXD, 3, 19, 1, 1, false)
532MUX_CFG(DM365, UART1_RXD, 3, 17, 3, 2, false)
533MUX_CFG(DM365, UART1_TXD, 3, 15, 3, 2, false)
534MUX_CFG(DM365, UART1_RTS, 3, 23, 3, 1, false)
535MUX_CFG(DM365, UART1_CTS, 3, 21, 3, 1, false)
536
537MUX_CFG(DM365, EMAC_TX_EN, 3, 17, 3, 1, false)
538MUX_CFG(DM365, EMAC_TX_CLK, 3, 15, 3, 1, false)
539MUX_CFG(DM365, EMAC_COL, 3, 14, 1, 1, false)
540MUX_CFG(DM365, EMAC_TXD3, 3, 13, 1, 1, false)
541MUX_CFG(DM365, EMAC_TXD2, 3, 12, 1, 1, false)
542MUX_CFG(DM365, EMAC_TXD1, 3, 11, 1, 1, false)
543MUX_CFG(DM365, EMAC_TXD0, 3, 10, 1, 1, false)
544MUX_CFG(DM365, EMAC_RXD3, 3, 9, 1, 1, false)
545MUX_CFG(DM365, EMAC_RXD2, 3, 8, 1, 1, false)
546MUX_CFG(DM365, EMAC_RXD1, 3, 7, 1, 1, false)
547MUX_CFG(DM365, EMAC_RXD0, 3, 6, 1, 1, false)
548MUX_CFG(DM365, EMAC_RX_CLK, 3, 5, 1, 1, false)
549MUX_CFG(DM365, EMAC_RX_DV, 3, 4, 1, 1, false)
550MUX_CFG(DM365, EMAC_RX_ER, 3, 3, 1, 1, false)
551MUX_CFG(DM365, EMAC_CRS, 3, 2, 1, 1, false)
552MUX_CFG(DM365, EMAC_MDIO, 3, 1, 1, 1, false)
553MUX_CFG(DM365, EMAC_MDCLK, 3, 0, 1, 1, false)
9f513153 554
990c09d5 555MUX_CFG(DM365, KEYSCAN, 2, 0, 0x3f, 0x3f, false)
9f513153 556
af5dbaef
SP		 557MUX_CFG(DM365, PWM0, 1, 0, 3, 2, false)
558MUX_CFG(DM365, PWM0_G23, 3, 26, 3, 3, false)
559MUX_CFG(DM365, PWM1, 1, 2, 3, 2, false)
560MUX_CFG(DM365, PWM1_G25, 3, 29, 3, 2, false)
561MUX_CFG(DM365, PWM2_G87, 1, 10, 3, 2, false)
562MUX_CFG(DM365, PWM2_G88, 1, 8, 3, 2, false)
563MUX_CFG(DM365, PWM2_G89, 1, 6, 3, 2, false)
564MUX_CFG(DM365, PWM2_G90, 1, 4, 3, 2, false)
565MUX_CFG(DM365, PWM3_G80, 1, 20, 3, 3, false)
566MUX_CFG(DM365, PWM3_G81, 1, 18, 3, 3, false)
567MUX_CFG(DM365, PWM3_G85, 1, 14, 3, 2, false)
568MUX_CFG(DM365, PWM3_G86, 1, 12, 3, 2, false)
569
570MUX_CFG(DM365, SPI1_SCLK, 4, 2, 3, 1, false)
571MUX_CFG(DM365, SPI1_SDI, 3, 31, 1, 1, false)
572MUX_CFG(DM365, SPI1_SDO, 4, 0, 3, 1, false)
573MUX_CFG(DM365, SPI1_SDENA0, 4, 4, 3, 1, false)
574MUX_CFG(DM365, SPI1_SDENA1, 4, 0, 3, 2, false)
575
576MUX_CFG(DM365, SPI2_SCLK, 4, 10, 3, 1, false)
577MUX_CFG(DM365, SPI2_SDI, 4, 6, 3, 1, false)
578MUX_CFG(DM365, SPI2_SDO, 4, 8, 3, 1, false)
579MUX_CFG(DM365, SPI2_SDENA0, 4, 12, 3, 1, false)
580MUX_CFG(DM365, SPI2_SDENA1, 4, 8, 3, 2, false)
581
582MUX_CFG(DM365, SPI3_SCLK, 0, 0, 3, 2, false)
583MUX_CFG(DM365, SPI3_SDI, 0, 2, 3, 2, false)
584MUX_CFG(DM365, SPI3_SDO, 0, 6, 3, 2, false)
585MUX_CFG(DM365, SPI3_SDENA0, 0, 4, 3, 2, false)
586MUX_CFG(DM365, SPI3_SDENA1, 0, 6, 3, 3, false)
587
588MUX_CFG(DM365, SPI4_SCLK, 4, 18, 3, 1, false)
589MUX_CFG(DM365, SPI4_SDI, 4, 14, 3, 1, false)
590MUX_CFG(DM365, SPI4_SDO, 4, 16, 3, 1, false)
591MUX_CFG(DM365, SPI4_SDENA0, 4, 20, 3, 1, false)
592MUX_CFG(DM365, SPI4_SDENA1, 4, 16, 3, 2, false)
593
0efe2b74
TK		 594MUX_CFG(DM365, CLKOUT0, 4, 20, 3, 3, false)
595MUX_CFG(DM365, CLKOUT1, 4, 16, 3, 3, false)
596MUX_CFG(DM365, CLKOUT2, 4, 8, 3, 3, false)
597
af5dbaef 598MUX_CFG(DM365, GPIO20, 3, 21, 3, 0, false)
2168e76d
TK		 599MUX_CFG(DM365, GPIO30, 4, 6, 3, 0, false)
600MUX_CFG(DM365, GPIO31, 4, 8, 3, 0, false)
601MUX_CFG(DM365, GPIO32, 4, 10, 3, 0, false)
af5dbaef
SP		 602MUX_CFG(DM365, GPIO33, 4, 12, 3, 0, false)
603MUX_CFG(DM365, GPIO40, 4, 26, 3, 0, false)
ce100669 604MUX_CFG(DM365, GPIO64_57, 2, 6, 1, 0, false)
af5dbaef
SP		 605
606MUX_CFG(DM365, VOUT_FIELD, 1, 18, 3, 1, false)
607MUX_CFG(DM365, VOUT_FIELD_G81, 1, 18, 3, 0, false)
608MUX_CFG(DM365, VOUT_HVSYNC, 1, 16, 1, 0, false)
609MUX_CFG(DM365, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false)
610MUX_CFG(DM365, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false)
611MUX_CFG(DM365, VIN_CAM_WEN, 0, 14, 3, 0, false)
612MUX_CFG(DM365, VIN_CAM_VD, 0, 13, 1, 0, false)
613MUX_CFG(DM365, VIN_CAM_HD, 0, 12, 1, 0, false)
866d2869
SP		 614MUX_CFG(DM365, VIN_YIN4_7_EN, 0, 0, 0xff, 0, false)
615MUX_CFG(DM365, VIN_YIN0_3_EN, 0, 8, 0xf, 0, false)
af5dbaef 616
9f513153
SP		 617INT_CFG(DM365, INT_EDMA_CC, 2, 1, 1, false)
618INT_CFG(DM365, INT_EDMA_TC0_ERR, 3, 1, 1, false)
619INT_CFG(DM365, INT_EDMA_TC1_ERR, 4, 1, 1, false)
620INT_CFG(DM365, INT_EDMA_TC2_ERR, 22, 1, 1, false)
621INT_CFG(DM365, INT_EDMA_TC3_ERR, 23, 1, 1, false)
622INT_CFG(DM365, INT_PRTCSS, 10, 1, 1, false)
623INT_CFG(DM365, INT_EMAC_RXTHRESH, 14, 1, 1, false)
624INT_CFG(DM365, INT_EMAC_RXPULSE, 15, 1, 1, false)
625INT_CFG(DM365, INT_EMAC_TXPULSE, 16, 1, 1, false)
626INT_CFG(DM365, INT_EMAC_MISCPULSE, 17, 1, 1, false)
0c30e0d3
SP		 627INT_CFG(DM365, INT_IMX0_ENABLE, 0, 1, 0, false)
628INT_CFG(DM365, INT_IMX0_DISABLE, 0, 1, 1, false)
629INT_CFG(DM365, INT_HDVICP_ENABLE, 0, 1, 1, false)
630INT_CFG(DM365, INT_HDVICP_DISABLE, 0, 1, 0, false)
631INT_CFG(DM365, INT_IMX1_ENABLE, 24, 1, 1, false)
632INT_CFG(DM365, INT_IMX1_DISABLE, 24, 1, 0, false)
633INT_CFG(DM365, INT_NSF_ENABLE, 25, 1, 1, false)
634INT_CFG(DM365, INT_NSF_DISABLE, 25, 1, 0, false)
e9ab3214
MA		 635
636EVT_CFG(DM365, EVT2_ASP_TX, 0, 1, 0, false)
637EVT_CFG(DM365, EVT3_ASP_RX, 1, 1, 0, false)
e89861e9
MA		 638EVT_CFG(DM365, EVT2_VC_TX, 0, 1, 1, false)
639EVT_CFG(DM365, EVT3_VC_RX, 1, 1, 1, false)
fb8fcb89
SP		 640#endif
641};
642
a3e13e89
SP		 643static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
644
645static struct davinci_spi_platform_data dm365_spi0_pdata = {
646 .version = SPI_VERSION_1,
647 .num_chipselect = 2,
2e3e2a5e 648 .dma_event_q = EVENTQ_3,
1b0838b5 649 .prescaler_limit = 1,
a3e13e89
SP		 650};
651
652static struct resource dm365_spi0_resources[] = {
653 {
654 .start = 0x01c66000,
655 .end = 0x01c667ff,
656 .flags = IORESOURCE_MEM,
657 },
658 {
659 .start = IRQ_DM365_SPIINT0_0,
660 .flags = IORESOURCE_IRQ,
661 },
662 {
663 .start = 17,
664 .flags = IORESOURCE_DMA,
665 },
666 {
667 .start = 16,
668 .flags = IORESOURCE_DMA,
669 },
a3e13e89
SP		 670};
671
672static struct platform_device dm365_spi0_device = {
673 .name = "spi_davinci",
674 .id = 0,
675 .dev = {
676 .dma_mask = &dm365_spi0_dma_mask,
677 .coherent_dma_mask = DMA_BIT_MASK(32),
678 .platform_data = &dm365_spi0_pdata,
679 },
680 .num_resources = ARRAY_SIZE(dm365_spi0_resources),
681 .resource = dm365_spi0_resources,
682};
683
684void __init dm365_init_spi0(unsigned chipselect_mask,
d65566e5 685 const struct spi_board_info *info, unsigned len)
a3e13e89
SP		 686{
687 davinci_cfg_reg(DM365_SPI0_SCLK);
688 davinci_cfg_reg(DM365_SPI0_SDI);
689 davinci_cfg_reg(DM365_SPI0_SDO);
690
691 /* not all slaves will be wired up */
692 if (chipselect_mask & BIT(0))
693 davinci_cfg_reg(DM365_SPI0_SDENA0);
694 if (chipselect_mask & BIT(1))
695 davinci_cfg_reg(DM365_SPI0_SDENA1);
696
697 spi_register_board_info(info, len);
698
699 platform_device_register(&dm365_spi0_device);
700}
701
9cc1515c
PA		 702static struct resource dm365_gpio_resources[] = {
703 { /* registers */
704 .start = DAVINCI_GPIO_BASE,
705 .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
706 .flags = IORESOURCE_MEM,
707 },
708 { /* interrupt */
709 .start = IRQ_DM365_GPIO0,
710 .end = IRQ_DM365_GPIO7,
711 .flags = IORESOURCE_IRQ,
712 },
713};
714
715static struct davinci_gpio_platform_data dm365_gpio_platform_data = {
716 .ngpio = 104,
9cc1515c
PA		 717 .gpio_unbanked = 8,
718};
719
720int __init dm365_gpio_register(void)
721{
722 return davinci_gpio_register(dm365_gpio_resources,
e462f1f5 723 ARRAY_SIZE(dm365_gpio_resources),
9cc1515c
PA		 724 &dm365_gpio_platform_data);
725}
726
8ed0a9d4
SP		 727static struct emac_platform_data dm365_emac_pdata = {
728 .ctrl_reg_offset = DM365_EMAC_CNTRL_OFFSET,
729 .ctrl_mod_reg_offset = DM365_EMAC_CNTRL_MOD_OFFSET,
730 .ctrl_ram_offset = DM365_EMAC_CNTRL_RAM_OFFSET,
8ed0a9d4
SP		 731 .ctrl_ram_size = DM365_EMAC_CNTRL_RAM_SIZE,
732 .version = EMAC_VERSION_2,
733};
734
735static struct resource dm365_emac_resources[] = {
736 {
737 .start = DM365_EMAC_BASE,
d22960c8 738 .end = DM365_EMAC_BASE + SZ_16K - 1,
8ed0a9d4
SP		 739 .flags = IORESOURCE_MEM,
740 },
741 {
742 .start = IRQ_DM365_EMAC_RXTHRESH,
743 .end = IRQ_DM365_EMAC_RXTHRESH,
744 .flags = IORESOURCE_IRQ,
745 },
746 {
747 .start = IRQ_DM365_EMAC_RXPULSE,
748 .end = IRQ_DM365_EMAC_RXPULSE,
749 .flags = IORESOURCE_IRQ,
750 },
751 {
752 .start = IRQ_DM365_EMAC_TXPULSE,
753 .end = IRQ_DM365_EMAC_TXPULSE,
754 .flags = IORESOURCE_IRQ,
755 },
756 {
757 .start = IRQ_DM365_EMAC_MISCPULSE,
758 .end = IRQ_DM365_EMAC_MISCPULSE,
759 .flags = IORESOURCE_IRQ,
760 },
761};
762
763static struct platform_device dm365_emac_device = {
764 .name = "davinci_emac",
765 .id = 1,
766 .dev = {
767 .platform_data = &dm365_emac_pdata,
768 },
769 .num_resources = ARRAY_SIZE(dm365_emac_resources),
770 .resource = dm365_emac_resources,
771};
fb8fcb89 772
d22960c8
CC		 773static struct resource dm365_mdio_resources[] = {
774 {
775 .start = DM365_EMAC_MDIO_BASE,
776 .end = DM365_EMAC_MDIO_BASE + SZ_4K - 1,
777 .flags = IORESOURCE_MEM,
778 },
779};
780
781static struct platform_device dm365_mdio_device = {
782 .name = "davinci_mdio",
783 .id = 0,
784 .num_resources = ARRAY_SIZE(dm365_mdio_resources),
785 .resource = dm365_mdio_resources,
786};
787
fb8fcb89
SP		 788static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
789 [IRQ_VDINT0] = 2,
790 [IRQ_VDINT1] = 6,
791 [IRQ_VDINT2] = 6,
792 [IRQ_HISTINT] = 6,
793 [IRQ_H3AINT] = 6,
794 [IRQ_PRVUINT] = 6,
795 [IRQ_RSZINT] = 6,
796 [IRQ_DM365_INSFINT] = 7,
797 [IRQ_VENCINT] = 6,
798 [IRQ_ASQINT] = 6,
799 [IRQ_IMXINT] = 6,
800 [IRQ_DM365_IMCOPINT] = 4,
801 [IRQ_USBINT] = 4,
802 [IRQ_DM365_RTOINT] = 7,
803 [IRQ_DM365_TINT5] = 7,
804 [IRQ_DM365_TINT6] = 5,
805 [IRQ_CCINT0] = 5,
806 [IRQ_CCERRINT] = 5,
807 [IRQ_TCERRINT0] = 5,
808 [IRQ_TCERRINT] = 7,
809 [IRQ_PSCIN] = 4,
810 [IRQ_DM365_SPINT2_1] = 7,
811 [IRQ_DM365_TINT7] = 7,
812 [IRQ_DM365_SDIOINT0] = 7,
813 [IRQ_MBXINT] = 7,
814 [IRQ_MBRINT] = 7,
815 [IRQ_MMCINT] = 7,
816 [IRQ_DM365_MMCINT1] = 7,
817 [IRQ_DM365_PWMINT3] = 7,
fb8fcb89
SP		 818 [IRQ_AEMIFINT] = 2,
819 [IRQ_DM365_SDIOINT1] = 2,
820 [IRQ_TINT0_TINT12] = 7,
821 [IRQ_TINT0_TINT34] = 7,
822 [IRQ_TINT1_TINT12] = 7,
823 [IRQ_TINT1_TINT34] = 7,
824 [IRQ_PWMINT0] = 7,
825 [IRQ_PWMINT1] = 3,
826 [IRQ_PWMINT2] = 3,
827 [IRQ_I2C] = 3,
828 [IRQ_UARTINT0] = 3,
829 [IRQ_UARTINT1] = 3,
99381b4f 830 [IRQ_DM365_RTCINT] = 3,
fb8fcb89
SP		 831 [IRQ_DM365_SPIINT0_0] = 3,
832 [IRQ_DM365_SPIINT3_0] = 3,
833 [IRQ_DM365_GPIO0] = 3,
834 [IRQ_DM365_GPIO1] = 7,
835 [IRQ_DM365_GPIO2] = 4,
836 [IRQ_DM365_GPIO3] = 4,
837 [IRQ_DM365_GPIO4] = 7,
838 [IRQ_DM365_GPIO5] = 7,
839 [IRQ_DM365_GPIO6] = 7,
840 [IRQ_DM365_GPIO7] = 7,
841 [IRQ_DM365_EMAC_RXTHRESH] = 7,
842 [IRQ_DM365_EMAC_RXPULSE] = 7,
843 [IRQ_DM365_EMAC_TXPULSE] = 7,
844 [IRQ_DM365_EMAC_MISCPULSE] = 7,
845 [IRQ_DM365_GPIO12] = 7,
846 [IRQ_DM365_GPIO13] = 7,
847 [IRQ_DM365_GPIO14] = 7,
848 [IRQ_DM365_GPIO15] = 7,
849 [IRQ_DM365_KEYINT] = 7,
850 [IRQ_DM365_TCERRINT2] = 7,
851 [IRQ_DM365_TCERRINT3] = 7,
852 [IRQ_DM365_EMUINT] = 7,
853};
854
15061b5d 855/* Four Transfer Controllers on DM365 */
d4cb7f40 856static s8 dm365_queue_priority_mapping[][2] = {
15061b5d
SP		 857 /* {event queue no, Priority} */
858 {0, 7},
859 {1, 7},
860 {2, 7},
861 {3, 0},
862 {-1, -1},
863};
864
d4cb7f40 865static struct edma_soc_info dm365_edma_pdata = {
bc3ac9f3
SN		 866 .queue_priority_mapping = dm365_queue_priority_mapping,
867 .default_queue = EVENTQ_3,
868};
869
15061b5d
SP		 870static struct resource edma_resources[] = {
871 {
d4cb7f40 872 .name = "edma3_cc",
15061b5d
SP		 873 .start = 0x01c00000,
874 .end = 0x01c00000 + SZ_64K - 1,
875 .flags = IORESOURCE_MEM,
876 },
877 {
d4cb7f40 878 .name = "edma3_tc0",
15061b5d
SP		 879 .start = 0x01c10000,
880 .end = 0x01c10000 + SZ_1K - 1,
881 .flags = IORESOURCE_MEM,
882 },
883 {
d4cb7f40 884 .name = "edma3_tc1",
15061b5d
SP		 885 .start = 0x01c10400,
886 .end = 0x01c10400 + SZ_1K - 1,
887 .flags = IORESOURCE_MEM,
888 },
889 {
d4cb7f40 890 .name = "edma3_tc2",
15061b5d
SP		 891 .start = 0x01c10800,
892 .end = 0x01c10800 + SZ_1K - 1,
893 .flags = IORESOURCE_MEM,
894 },
895 {
d4cb7f40 896 .name = "edma3_tc3",
15061b5d
SP		 897 .start = 0x01c10c00,
898 .end = 0x01c10c00 + SZ_1K - 1,
899 .flags = IORESOURCE_MEM,
900 },
901 {
d4cb7f40 902 .name = "edma3_ccint",
15061b5d
SP		 903 .start = IRQ_CCINT0,
904 .flags = IORESOURCE_IRQ,
905 },
906 {
d4cb7f40 907 .name = "edma3_ccerrint",
15061b5d
SP		 908 .start = IRQ_CCERRINT,
909 .flags = IORESOURCE_IRQ,
910 },
911 /* not using TC*_ERR */
912};
913
914static struct platform_device dm365_edma_device = {
915 .name = "edma",
916 .id = 0,
d4cb7f40 917 .dev.platform_data = &dm365_edma_pdata,
15061b5d
SP		 918 .num_resources = ARRAY_SIZE(edma_resources),
919 .resource = edma_resources,
920};
921
e9ab3214
MA		 922static struct resource dm365_asp_resources[] = {
923 {
ee880dbd 924 .name = "mpu",
e9ab3214
MA		 925 .start = DAVINCI_DM365_ASP0_BASE,
926 .end = DAVINCI_DM365_ASP0_BASE + SZ_8K - 1,
927 .flags = IORESOURCE_MEM,
928 },
929 {
930 .start = DAVINCI_DMA_ASP0_TX,
931 .end = DAVINCI_DMA_ASP0_TX,
932 .flags = IORESOURCE_DMA,
933 },
934 {
935 .start = DAVINCI_DMA_ASP0_RX,
936 .end = DAVINCI_DMA_ASP0_RX,
937 .flags = IORESOURCE_DMA,
938 },
939};
940
941static struct platform_device dm365_asp_device = {
bedad0ca
CPE		 942 .name = "davinci-mcbsp",
943 .id = -1,
e9ab3214
MA		 944 .num_resources = ARRAY_SIZE(dm365_asp_resources),
945 .resource = dm365_asp_resources,
946};
947
e89861e9
MA		 948static struct resource dm365_vc_resources[] = {
949 {
950 .start = DAVINCI_DM365_VC_BASE,
951 .end = DAVINCI_DM365_VC_BASE + SZ_1K - 1,
952 .flags = IORESOURCE_MEM,
953 },
954 {
955 .start = DAVINCI_DMA_VC_TX,
956 .end = DAVINCI_DMA_VC_TX,
957 .flags = IORESOURCE_DMA,
958 },
959 {
960 .start = DAVINCI_DMA_VC_RX,
961 .end = DAVINCI_DMA_VC_RX,
962 .flags = IORESOURCE_DMA,
963 },
964};
965
966static struct platform_device dm365_vc_device = {
967 .name = "davinci_voicecodec",
968 .id = -1,
969 .num_resources = ARRAY_SIZE(dm365_vc_resources),
970 .resource = dm365_vc_resources,
971};
972
99381b4f
MA		 973static struct resource dm365_rtc_resources[] = {
974 {
975 .start = DM365_RTC_BASE,
976 .end = DM365_RTC_BASE + SZ_1K - 1,
977 .flags = IORESOURCE_MEM,
978 },
979 {
980 .start = IRQ_DM365_RTCINT,
981 .flags = IORESOURCE_IRQ,
982 },
983};
984
985static struct platform_device dm365_rtc_device = {
986 .name = "rtc_davinci",
987 .id = 0,
988 .num_resources = ARRAY_SIZE(dm365_rtc_resources),
989 .resource = dm365_rtc_resources,
990};
991
fb8fcb89
SP		 992static struct map_desc dm365_io_desc[] = {
993 {
994 .virtual = IO_VIRT,
995 .pfn = __phys_to_pfn(IO_PHYS),
996 .length = IO_SIZE,
997 .type = MT_DEVICE
998 },
fb8fcb89
SP		 999};
1000
990c09d5
MA		 1001static struct resource dm365_ks_resources[] = {
1002 {
1003 /* registers */
1004 .start = DM365_KEYSCAN_BASE,
1005 .end = DM365_KEYSCAN_BASE + SZ_1K - 1,
1006 .flags = IORESOURCE_MEM,
1007 },
1008 {
1009 /* interrupt */
1010 .start = IRQ_DM365_KEYINT,
1011 .end = IRQ_DM365_KEYINT,
1012 .flags = IORESOURCE_IRQ,
1013 },
1014};
1015
1016static struct platform_device dm365_ks_device = {
1017 .name = "davinci_keyscan",
1018 .id = 0,
1019 .num_resources = ARRAY_SIZE(dm365_ks_resources),
1020 .resource = dm365_ks_resources,
1021};
1022
fb8fcb89
SP		 1023/* Contents of JTAG ID register used to identify exact cpu type */
1024static struct davinci_id dm365_ids[] = {
1025 {
1026 .variant = 0x0,
1027 .part_no = 0xb83e,
1028 .manufacturer = 0x017,
1029 .cpu_id = DAVINCI_CPU_ID_DM365,
cc36e97b
SP		 1030 .name = "dm365_rev1.1",
1031 },
1032 {
1033 .variant = 0x8,
1034 .part_no = 0xb83e,
1035 .manufacturer = 0x017,
1036 .cpu_id = DAVINCI_CPU_ID_DM365,
1037 .name = "dm365_rev1.2",
fb8fcb89
SP		 1038 },
1039};
1040
e4c822c7 1041static u32 dm365_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
fb8fcb89 1042
28552c2e 1043static struct davinci_timer_info dm365_timer_info = {
fb8fcb89
SP		 1044 .timers = davinci_timer_instance,
1045 .clockevent_id = T0_BOT,
1046 .clocksource_id = T0_TOP,
1047};
1048
a2767b41
TK		 1049#define DM365_UART1_BASE (IO_PHYS + 0x106000)
1050
19955c3d 1051static struct plat_serial8250_port dm365_serial0_platform_data[] = {
fb8fcb89
SP		 1052 {
1053 .mapbase = DAVINCI_UART0_BASE,
1054 .irq = IRQ_UARTINT0,
1055 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
1056 UPF_IOREMAP,
1057 .iotype = UPIO_MEM,
1058 .regshift = 2,
1059 },
19955c3d
MP		 1060 {
1061 .flags = 0,
1062 }
1063};
1064static struct plat_serial8250_port dm365_serial1_platform_data[] = {
fb8fcb89 1065 {
a2767b41 1066 .mapbase = DM365_UART1_BASE,
fb8fcb89
SP		 1067 .irq = IRQ_UARTINT1,
1068 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
1069 UPF_IOREMAP,
1070 .iotype = UPIO_MEM,
1071 .regshift = 2,
1072 },
1073 {
19955c3d
MP		 1074 .flags = 0,
1075 }
fb8fcb89
SP		 1076};
1077
fcf7157b 1078struct platform_device dm365_serial_device[] = {
19955c3d
MP		 1079 {
1080 .name = "serial8250",
1081 .id = PLAT8250_DEV_PLATFORM,
1082 .dev = {
1083 .platform_data = dm365_serial0_platform_data,
1084 }
fb8fcb89 1085 },
19955c3d
MP		 1086 {
1087 .name = "serial8250",
1088 .id = PLAT8250_DEV_PLATFORM1,
1089 .dev = {
1090 .platform_data = dm365_serial1_platform_data,
1091 }
fb8fcb89 1092 },
19955c3d
MP		 1093 {
1094 }
fb8fcb89
SP		 1095};
1096
1097static struct davinci_soc_info davinci_soc_info_dm365 = {
1098 .io_desc = dm365_io_desc,
1099 .io_desc_num = ARRAY_SIZE(dm365_io_desc),
3347db83 1100 .jtag_id_reg = 0x01c40028,
fb8fcb89
SP		 1101 .ids = dm365_ids,
1102 .ids_num = ARRAY_SIZE(dm365_ids),
1103 .cpu_clks = dm365_clks,
1104 .psc_bases = dm365_psc_bases,
1105 .psc_bases_num = ARRAY_SIZE(dm365_psc_bases),
779b0d53 1106 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
fb8fcb89
SP		 1107 .pinmux_pins = dm365_pins,
1108 .pinmux_pins_num = ARRAY_SIZE(dm365_pins),
bd808947 1109 .intc_base = DAVINCI_ARM_INTC_BASE,
fb8fcb89
SP		 1110 .intc_type = DAVINCI_INTC_TYPE_AINTC,
1111 .intc_irq_prios = dm365_default_priorities,
1112 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
1113 .timer_info = &dm365_timer_info,
8ed0a9d4 1114 .emac_pdata = &dm365_emac_pdata,
fb8fcb89
SP		 1115 .sram_dma = 0x00010000,
1116 .sram_len = SZ_32K,
1117};
1118
e9ab3214
MA		 1119void __init dm365_init_asp(struct snd_platform_data *pdata)
1120{
1121 davinci_cfg_reg(DM365_MCBSP0_BDX);
1122 davinci_cfg_reg(DM365_MCBSP0_X);
1123 davinci_cfg_reg(DM365_MCBSP0_BFSX);
1124 davinci_cfg_reg(DM365_MCBSP0_BDR);
1125 davinci_cfg_reg(DM365_MCBSP0_R);
1126 davinci_cfg_reg(DM365_MCBSP0_BFSR);
1127 davinci_cfg_reg(DM365_EVT2_ASP_TX);
1128 davinci_cfg_reg(DM365_EVT3_ASP_RX);
1129 dm365_asp_device.dev.platform_data = pdata;
1130 platform_device_register(&dm365_asp_device);
1131}
1132
e89861e9
MA		 1133void __init dm365_init_vc(struct snd_platform_data *pdata)
1134{
1135 davinci_cfg_reg(DM365_EVT2_VC_TX);
1136 davinci_cfg_reg(DM365_EVT3_VC_RX);
1137 dm365_vc_device.dev.platform_data = pdata;
1138 platform_device_register(&dm365_vc_device);
1139}
1140
990c09d5
MA		 1141void __init dm365_init_ks(struct davinci_ks_platform_data *pdata)
1142{
990c09d5
MA		 1143 dm365_ks_device.dev.platform_data = pdata;
1144 platform_device_register(&dm365_ks_device);
1145}
1146
99381b4f
MA		 1147void __init dm365_init_rtc(void)
1148{
1149 davinci_cfg_reg(DM365_INT_PRTCSS);
1150 platform_device_register(&dm365_rtc_device);
1151}
1152
fb8fcb89
SP		 1153void __init dm365_init(void)
1154{
1155 davinci_common_init(&davinci_soc_info_dm365);
5cfb19ac 1156 davinci_map_sysmod();
fb8fcb89 1157}
8ed0a9d4 1158
f2a4c59d
MK		 1159static struct resource dm365_vpss_resources[] = {
1160 {
1161 /* VPSS ISP5 Base address */
1162 .name = "isp5",
1163 .start = 0x01c70000,
1164 .end = 0x01c70000 + 0xff,
1165 .flags = IORESOURCE_MEM,
1166 },
1167 {
1168 /* VPSS CLK Base address */
1169 .name = "vpss",
1170 .start = 0x01c70200,
1171 .end = 0x01c70200 + 0xff,
1172 .flags = IORESOURCE_MEM,
1173 },
1174};
1175
1176static struct platform_device dm365_vpss_device = {
1177 .name = "vpss",
1178 .id = -1,
1179 .dev.platform_data = "dm365_vpss",
1180 .num_resources = ARRAY_SIZE(dm365_vpss_resources),
1181 .resource = dm365_vpss_resources,
1182};
1183
1184static struct resource vpfe_resources[] = {
1185 {
1186 .start = IRQ_VDINT0,
1187 .end = IRQ_VDINT0,
1188 .flags = IORESOURCE_IRQ,
1189 },
1190 {
1191 .start = IRQ_VDINT1,
1192 .end = IRQ_VDINT1,
1193 .flags = IORESOURCE_IRQ,
1194 },
1195};
1196
1197static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
1198static struct platform_device vpfe_capture_dev = {
1199 .name = CAPTURE_DRV_NAME,
1200 .id = -1,
1201 .num_resources = ARRAY_SIZE(vpfe_resources),
1202 .resource = vpfe_resources,
1203 .dev = {
1204 .dma_mask = &vpfe_capture_dma_mask,
1205 .coherent_dma_mask = DMA_BIT_MASK(32),
1206 },
1207};
1208
1209static void dm365_isif_setup_pinmux(void)
1210{
1211 davinci_cfg_reg(DM365_VIN_CAM_WEN);
1212 davinci_cfg_reg(DM365_VIN_CAM_VD);
1213 davinci_cfg_reg(DM365_VIN_CAM_HD);
1214 davinci_cfg_reg(DM365_VIN_YIN4_7_EN);
1215 davinci_cfg_reg(DM365_VIN_YIN0_3_EN);
1216}
1217
1218static struct resource isif_resource[] = {
1219 /* ISIF Base address */
1220 {
1221 .start = 0x01c71000,
1222 .end = 0x01c71000 + 0x1ff,
1223 .flags = IORESOURCE_MEM,
1224 },
1225 /* ISIF Linearization table 0 */
1226 {
1227 .start = 0x1C7C000,
1228 .end = 0x1C7C000 + 0x2ff,
1229 .flags = IORESOURCE_MEM,
1230 },
1231 /* ISIF Linearization table 1 */
1232 {
1233 .start = 0x1C7C400,
1234 .end = 0x1C7C400 + 0x2ff,
1235 .flags = IORESOURCE_MEM,
1236 },
1237};
1238static struct platform_device dm365_isif_dev = {
1239 .name = "isif",
1240 .id = -1,
1241 .num_resources = ARRAY_SIZE(isif_resource),
1242 .resource = isif_resource,
1243 .dev = {
1244 .dma_mask = &vpfe_capture_dma_mask,
1245 .coherent_dma_mask = DMA_BIT_MASK(32),
1246 .platform_data = dm365_isif_setup_pinmux,
1247 },
1248};
1249
120c6604
LP		 1250static struct resource dm365_osd_resources[] = {
1251 {
1252 .start = DM365_OSD_BASE,
1253 .end = DM365_OSD_BASE + 0xff,
1254 .flags = IORESOURCE_MEM,
1255 },
1256};
1257
1258static u64 dm365_video_dma_mask = DMA_BIT_MASK(32);
1259
1260static struct platform_device dm365_osd_dev = {
1261 .name = DM365_VPBE_OSD_SUBDEV_NAME,
1262 .id = -1,
1263 .num_resources = ARRAY_SIZE(dm365_osd_resources),
1264 .resource = dm365_osd_resources,
1265 .dev = {
1266 .dma_mask = &dm365_video_dma_mask,
1267 .coherent_dma_mask = DMA_BIT_MASK(32),
1268 },
1269};
1270
1271static struct resource dm365_venc_resources[] = {
1272 {
1273 .start = IRQ_VENCINT,
1274 .end = IRQ_VENCINT,
1275 .flags = IORESOURCE_IRQ,
1276 },
1277 /* venc registers io space */
1278 {
1279 .start = DM365_VENC_BASE,
1280 .end = DM365_VENC_BASE + 0x177,
1281 .flags = IORESOURCE_MEM,
1282 },
1283 /* vdaccfg registers io space */
1284 {
1285 .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG,
1286 .end = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3,
1287 .flags = IORESOURCE_MEM,
1288 },
1289};
1290
1291static struct resource dm365_v4l2_disp_resources[] = {
1292 {
1293 .start = IRQ_VENCINT,
1294 .end = IRQ_VENCINT,
1295 .flags = IORESOURCE_IRQ,
1296 },
1297 /* venc registers io space */
1298 {
1299 .start = DM365_VENC_BASE,
1300 .end = DM365_VENC_BASE + 0x177,
1301 .flags = IORESOURCE_MEM,
1302 },
1303};
1304
27ffaeb0 1305static int dm365_vpbe_setup_pinmux(u32 if_type, int field)
120c6604
LP		 1306{
1307 switch (if_type) {
27ffaeb0 1308 case MEDIA_BUS_FMT_SGRBG8_1X8:
120c6604
LP		 1309 davinci_cfg_reg(DM365_VOUT_FIELD_G81);
1310 davinci_cfg_reg(DM365_VOUT_COUTL_EN);
1311 davinci_cfg_reg(DM365_VOUT_COUTH_EN);
1312 break;
27ffaeb0 1313 case MEDIA_BUS_FMT_YUYV10_1X20:
120c6604
LP		 1314 if (field)
1315 davinci_cfg_reg(DM365_VOUT_FIELD);
1316 else
1317 davinci_cfg_reg(DM365_VOUT_FIELD_G81);
1318 davinci_cfg_reg(DM365_VOUT_COUTL_EN);
1319 davinci_cfg_reg(DM365_VOUT_COUTH_EN);
1320 break;
1321 default:
1322 return -EINVAL;
1323 }
1324
1325 return 0;
1326}
1327
1328static int dm365_venc_setup_clock(enum vpbe_enc_timings_type type,
1329 unsigned int pclock)
1330{
1331 void __iomem *vpss_clkctl_reg;
1332 u32 val;
1333
1334 vpss_clkctl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL);
1335
1336 switch (type) {
1337 case VPBE_ENC_STD:
1338 val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
1339 break;
1340 case VPBE_ENC_DV_TIMINGS:
1341 if (pclock <= 27000000) {
1342 val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
1343 } else {
1344 /* set sysclk4 to output 74.25 MHz from pll1 */
1345 val = VPSS_PLLC2SYSCLK5_ENABLE | VPSS_DACCLKEN_ENABLE |
1346 VPSS_VENCCLKEN_ENABLE;
1347 }
1348 break;
1349 default:
1350 return -EINVAL;
1351 }
1352 writel(val, vpss_clkctl_reg);
1353
1354 return 0;
1355}
1356
1357static struct platform_device dm365_vpbe_display = {
1358 .name = "vpbe-v4l2",
1359 .id = -1,
1360 .num_resources = ARRAY_SIZE(dm365_v4l2_disp_resources),
1361 .resource = dm365_v4l2_disp_resources,
1362 .dev = {
1363 .dma_mask = &dm365_video_dma_mask,
1364 .coherent_dma_mask = DMA_BIT_MASK(32),
1365 },
1366};
1367
9c559708 1368static struct venc_platform_data dm365_venc_pdata = {
120c6604
LP		 1369 .setup_pinmux = dm365_vpbe_setup_pinmux,
1370 .setup_clock = dm365_venc_setup_clock,
1371};
1372
1373static struct platform_device dm365_venc_dev = {
1374 .name = DM365_VPBE_VENC_SUBDEV_NAME,
1375 .id = -1,
1376 .num_resources = ARRAY_SIZE(dm365_venc_resources),
1377 .resource = dm365_venc_resources,
1378 .dev = {
1379 .dma_mask = &dm365_video_dma_mask,
1380 .coherent_dma_mask = DMA_BIT_MASK(32),
1381 .platform_data = (void *)&dm365_venc_pdata,
1382 },
1383};
1384
1385static struct platform_device dm365_vpbe_dev = {
1386 .name = "vpbe_controller",
1387 .id = -1,
1388 .dev = {
1389 .dma_mask = &dm365_video_dma_mask,
1390 .coherent_dma_mask = DMA_BIT_MASK(32),
1391 },
1392};
1393
1394int __init dm365_init_video(struct vpfe_config *vpfe_cfg,
1395 struct vpbe_config *vpbe_cfg)
1396{
1397 if (vpfe_cfg || vpbe_cfg)
1398 platform_device_register(&dm365_vpss_device);
1399
1400 if (vpfe_cfg) {
1401 vpfe_capture_dev.dev.platform_data = vpfe_cfg;
1402 platform_device_register(&dm365_isif_dev);
1403 platform_device_register(&vpfe_capture_dev);
1404 }
1405 if (vpbe_cfg) {
1406 dm365_vpbe_dev.dev.platform_data = vpbe_cfg;
1407 platform_device_register(&dm365_osd_dev);
1408 platform_device_register(&dm365_venc_dev);
1409 platform_device_register(&dm365_vpbe_dev);
1410 platform_device_register(&dm365_vpbe_display);
1411 }
1412
1413 return 0;
1414}
1415
8ed0a9d4
SP		 1416static int __init dm365_init_devices(void)
1417{
1233090c
SN		 1418 int ret = 0;
1419
8ed0a9d4
SP		 1420 if (!cpu_is_davinci_dm365())
1421 return 0;
1422
15061b5d
SP		 1423 davinci_cfg_reg(DM365_INT_EDMA_CC);
1424 platform_device_register(&dm365_edma_device);
d22960c8
CC		 1425
1426 platform_device_register(&dm365_mdio_device);
8ed0a9d4 1427 platform_device_register(&dm365_emac_device);
d22960c8 1428
1233090c
SN		 1429 ret = davinci_init_wdt();
1430 if (ret)
1431 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
1432
1433 return ret;
8ed0a9d4
SP		 1434}
1435postcore_initcall(dm365_init_devices);
Linux kernel - Deliverables
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