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[deliverable/linux.git] / arch / arm / mach-davinci / dm365.c
CommitLineData
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SP		 1/*
2 * TI DaVinci DM365 chip specific setup
3 *
4 * Copyright (C) 2009 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
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SP		 15#include <linux/init.h>
16#include <linux/clk.h>
17#include <linux/serial_8250.h>
18#include <linux/platform_device.h>
19#include <linux/dma-mapping.h>
0c750e1f 20#include <linux/dmaengine.h>
a3e13e89 21#include <linux/spi/spi.h>
3ad7a42d 22#include <linux/platform_data/edma.h>
9cc1515c
PA		 23#include <linux/platform_data/gpio-davinci.h>
24#include <linux/platform_data/keyscan-davinci.h>
25#include <linux/platform_data/spi-davinci.h>
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SP		 26
27#include <asm/mach/map.h>
28
fb8fcb89 29#include <mach/cputype.h>
3acf731c 30#include "psc.h"
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SP		 31#include <mach/mux.h>
32#include <mach/irqs.h>
33#include <mach/time.h>
34#include <mach/serial.h>
35#include <mach/common.h>
36
39c6d2d1 37#include "davinci.h"
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SP		 38#include "clock.h"
39#include "mux.h"
896f66b7 40#include "asp.h"
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SP		 41
42#define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */
719f56f2 43#define DM365_RTC_BASE 0x01c69000
120c6604
LP		 44#define DM365_KEYSCAN_BASE 0x01c69400
45#define DM365_OSD_BASE 0x01c71c00
46#define DM365_VENC_BASE 0x01c71e00
719f56f2
MH		 47#define DAVINCI_DM365_VC_BASE 0x01d0c000
48#define DAVINCI_DMA_VC_TX 2
49#define DAVINCI_DMA_VC_RX 3
719f56f2
MH		 50#define DM365_EMAC_BASE 0x01d07000
51#define DM365_EMAC_MDIO_BASE (DM365_EMAC_BASE + 0x4000)
52#define DM365_EMAC_CNTRL_OFFSET 0x0000
53#define DM365_EMAC_CNTRL_MOD_OFFSET 0x3000
54#define DM365_EMAC_CNTRL_RAM_OFFSET 0x1000
55#define DM365_EMAC_CNTRL_RAM_SIZE 0x2000
56
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SP		 57static struct pll_data pll1_data = {
58 .num = 1,
59 .phys_base = DAVINCI_PLL1_BASE,
60 .flags = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
61};
62
63static struct pll_data pll2_data = {
64 .num = 2,
65 .phys_base = DAVINCI_PLL2_BASE,
66 .flags = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
67};
68
69static struct clk ref_clk = {
70 .name = "ref_clk",
71 .rate = DM365_REF_FREQ,
72};
73
74static struct clk pll1_clk = {
75 .name = "pll1",
76 .parent = &ref_clk,
77 .flags = CLK_PLL,
78 .pll_data = &pll1_data,
79};
80
81static struct clk pll1_aux_clk = {
82 .name = "pll1_aux_clk",
83 .parent = &pll1_clk,
84 .flags = CLK_PLL | PRE_PLL,
85};
86
87static struct clk pll1_sysclkbp = {
88 .name = "pll1_sysclkbp",
89 .parent = &pll1_clk,
90 .flags = CLK_PLL | PRE_PLL,
91 .div_reg = BPDIV
92};
93
94static struct clk clkout0_clk = {
95 .name = "clkout0",
96 .parent = &pll1_clk,
97 .flags = CLK_PLL | PRE_PLL,
98};
99
100static struct clk pll1_sysclk1 = {
101 .name = "pll1_sysclk1",
102 .parent = &pll1_clk,
103 .flags = CLK_PLL,
104 .div_reg = PLLDIV1,
105};
106
107static struct clk pll1_sysclk2 = {
108 .name = "pll1_sysclk2",
109 .parent = &pll1_clk,
110 .flags = CLK_PLL,
111 .div_reg = PLLDIV2,
112};
113
114static struct clk pll1_sysclk3 = {
115 .name = "pll1_sysclk3",
116 .parent = &pll1_clk,
117 .flags = CLK_PLL,
118 .div_reg = PLLDIV3,
119};
120
121static struct clk pll1_sysclk4 = {
122 .name = "pll1_sysclk4",
123 .parent = &pll1_clk,
124 .flags = CLK_PLL,
125 .div_reg = PLLDIV4,
126};
127
128static struct clk pll1_sysclk5 = {
129 .name = "pll1_sysclk5",
130 .parent = &pll1_clk,
131 .flags = CLK_PLL,
132 .div_reg = PLLDIV5,
133};
134
135static struct clk pll1_sysclk6 = {
136 .name = "pll1_sysclk6",
137 .parent = &pll1_clk,
138 .flags = CLK_PLL,
139 .div_reg = PLLDIV6,
140};
141
142static struct clk pll1_sysclk7 = {
143 .name = "pll1_sysclk7",
144 .parent = &pll1_clk,
145 .flags = CLK_PLL,
146 .div_reg = PLLDIV7,
147};
148
149static struct clk pll1_sysclk8 = {
150 .name = "pll1_sysclk8",
151 .parent = &pll1_clk,
152 .flags = CLK_PLL,
153 .div_reg = PLLDIV8,
154};
155
156static struct clk pll1_sysclk9 = {
157 .name = "pll1_sysclk9",
158 .parent = &pll1_clk,
159 .flags = CLK_PLL,
160 .div_reg = PLLDIV9,
161};
162
163static struct clk pll2_clk = {
164 .name = "pll2",
165 .parent = &ref_clk,
166 .flags = CLK_PLL,
167 .pll_data = &pll2_data,
168};
169
170static struct clk pll2_aux_clk = {
171 .name = "pll2_aux_clk",
172 .parent = &pll2_clk,
173 .flags = CLK_PLL | PRE_PLL,
174};
175
176static struct clk clkout1_clk = {
177 .name = "clkout1",
178 .parent = &pll2_clk,
179 .flags = CLK_PLL | PRE_PLL,
180};
181
182static struct clk pll2_sysclk1 = {
183 .name = "pll2_sysclk1",
184 .parent = &pll2_clk,
185 .flags = CLK_PLL,
186 .div_reg = PLLDIV1,
187};
188
189static struct clk pll2_sysclk2 = {
190 .name = "pll2_sysclk2",
191 .parent = &pll2_clk,
192 .flags = CLK_PLL,
193 .div_reg = PLLDIV2,
194};
195
196static struct clk pll2_sysclk3 = {
197 .name = "pll2_sysclk3",
198 .parent = &pll2_clk,
199 .flags = CLK_PLL,
200 .div_reg = PLLDIV3,
201};
202
203static struct clk pll2_sysclk4 = {
204 .name = "pll2_sysclk4",
205 .parent = &pll2_clk,
206 .flags = CLK_PLL,
207 .div_reg = PLLDIV4,
208};
209
210static struct clk pll2_sysclk5 = {
211 .name = "pll2_sysclk5",
212 .parent = &pll2_clk,
213 .flags = CLK_PLL,
214 .div_reg = PLLDIV5,
215};
216
217static struct clk pll2_sysclk6 = {
218 .name = "pll2_sysclk6",
219 .parent = &pll2_clk,
220 .flags = CLK_PLL,
221 .div_reg = PLLDIV6,
222};
223
224static struct clk pll2_sysclk7 = {
225 .name = "pll2_sysclk7",
226 .parent = &pll2_clk,
227 .flags = CLK_PLL,
228 .div_reg = PLLDIV7,
229};
230
231static struct clk pll2_sysclk8 = {
232 .name = "pll2_sysclk8",
233 .parent = &pll2_clk,
234 .flags = CLK_PLL,
235 .div_reg = PLLDIV8,
236};
237
238static struct clk pll2_sysclk9 = {
239 .name = "pll2_sysclk9",
240 .parent = &pll2_clk,
241 .flags = CLK_PLL,
242 .div_reg = PLLDIV9,
243};
244
245static struct clk vpss_dac_clk = {
246 .name = "vpss_dac",
247 .parent = &pll1_sysclk3,
248 .lpsc = DM365_LPSC_DAC_CLK,
249};
250
251static struct clk vpss_master_clk = {
252 .name = "vpss_master",
253 .parent = &pll1_sysclk5,
254 .lpsc = DM365_LPSC_VPSSMSTR,
255 .flags = CLK_PSC,
256};
257
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LP		 258static struct clk vpss_slave_clk = {
259 .name = "vpss_slave",
260 .parent = &pll1_sysclk5,
261 .lpsc = DAVINCI_LPSC_VPSSSLV,
262};
263
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SP		 264static struct clk arm_clk = {
265 .name = "arm_clk",
266 .parent = &pll2_sysclk2,
267 .lpsc = DAVINCI_LPSC_ARM,
268 .flags = ALWAYS_ENABLED,
269};
270
271static struct clk uart0_clk = {
272 .name = "uart0",
273 .parent = &pll1_aux_clk,
274 .lpsc = DAVINCI_LPSC_UART0,
275};
276
277static struct clk uart1_clk = {
278 .name = "uart1",
279 .parent = &pll1_sysclk4,
280 .lpsc = DAVINCI_LPSC_UART1,
281};
282
283static struct clk i2c_clk = {
284 .name = "i2c",
285 .parent = &pll1_aux_clk,
286 .lpsc = DAVINCI_LPSC_I2C,
287};
288
289static struct clk mmcsd0_clk = {
290 .name = "mmcsd0",
291 .parent = &pll1_sysclk8,
292 .lpsc = DAVINCI_LPSC_MMC_SD,
293};
294
295static struct clk mmcsd1_clk = {
296 .name = "mmcsd1",
297 .parent = &pll1_sysclk4,
298 .lpsc = DM365_LPSC_MMC_SD1,
299};
300
301static struct clk spi0_clk = {
302 .name = "spi0",
303 .parent = &pll1_sysclk4,
304 .lpsc = DAVINCI_LPSC_SPI,
305};
306
307static struct clk spi1_clk = {
308 .name = "spi1",
309 .parent = &pll1_sysclk4,
310 .lpsc = DM365_LPSC_SPI1,
311};
312
313static struct clk spi2_clk = {
314 .name = "spi2",
315 .parent = &pll1_sysclk4,
316 .lpsc = DM365_LPSC_SPI2,
317};
318
319static struct clk spi3_clk = {
320 .name = "spi3",
321 .parent = &pll1_sysclk4,
322 .lpsc = DM365_LPSC_SPI3,
323};
324
325static struct clk spi4_clk = {
326 .name = "spi4",
327 .parent = &pll1_aux_clk,
328 .lpsc = DM365_LPSC_SPI4,
329};
330
331static struct clk gpio_clk = {
332 .name = "gpio",
333 .parent = &pll1_sysclk4,
334 .lpsc = DAVINCI_LPSC_GPIO,
335};
336
337static struct clk aemif_clk = {
338 .name = "aemif",
339 .parent = &pll1_sysclk4,
340 .lpsc = DAVINCI_LPSC_AEMIF,
341};
342
343static struct clk pwm0_clk = {
344 .name = "pwm0",
345 .parent = &pll1_aux_clk,
346 .lpsc = DAVINCI_LPSC_PWM0,
347};
348
349static struct clk pwm1_clk = {
350 .name = "pwm1",
351 .parent = &pll1_aux_clk,
352 .lpsc = DAVINCI_LPSC_PWM1,
353};
354
355static struct clk pwm2_clk = {
356 .name = "pwm2",
357 .parent = &pll1_aux_clk,
358 .lpsc = DAVINCI_LPSC_PWM2,
359};
360
361static struct clk pwm3_clk = {
362 .name = "pwm3",
363 .parent = &ref_clk,
364 .lpsc = DM365_LPSC_PWM3,
365};
366
367static struct clk timer0_clk = {
368 .name = "timer0",
369 .parent = &pll1_aux_clk,
370 .lpsc = DAVINCI_LPSC_TIMER0,
371};
372
373static struct clk timer1_clk = {
374 .name = "timer1",
375 .parent = &pll1_aux_clk,
376 .lpsc = DAVINCI_LPSC_TIMER1,
377};
378
379static struct clk timer2_clk = {
380 .name = "timer2",
381 .parent = &pll1_aux_clk,
382 .lpsc = DAVINCI_LPSC_TIMER2,
383 .usecount = 1,
384};
385
386static struct clk timer3_clk = {
387 .name = "timer3",
388 .parent = &pll1_aux_clk,
389 .lpsc = DM365_LPSC_TIMER3,
390};
391
392static struct clk usb_clk = {
393 .name = "usb",
ed160672 394 .parent = &pll1_aux_clk,
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SP		 395 .lpsc = DAVINCI_LPSC_USB,
396};
397
398static struct clk emac_clk = {
399 .name = "emac",
400 .parent = &pll1_sysclk4,
401 .lpsc = DM365_LPSC_EMAC,
402};
403
404static struct clk voicecodec_clk = {
405 .name = "voice_codec",
406 .parent = &pll2_sysclk4,
407 .lpsc = DM365_LPSC_VOICE_CODEC,
408};
409
410static struct clk asp0_clk = {
411 .name = "asp0",
412 .parent = &pll1_sysclk4,
413 .lpsc = DM365_LPSC_McBSP1,
414};
415
416static struct clk rto_clk = {
417 .name = "rto",
418 .parent = &pll1_sysclk4,
419 .lpsc = DM365_LPSC_RTO,
420};
421
422static struct clk mjcp_clk = {
423 .name = "mjcp",
424 .parent = &pll1_sysclk3,
425 .lpsc = DM365_LPSC_MJCP,
426};
427
08aca087 428static struct clk_lookup dm365_clks[] = {
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SP		 429 CLK(NULL, "ref", &ref_clk),
430 CLK(NULL, "pll1", &pll1_clk),
431 CLK(NULL, "pll1_aux", &pll1_aux_clk),
432 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
433 CLK(NULL, "clkout0", &clkout0_clk),
434 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
435 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
436 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
437 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
438 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
439 CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
440 CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
441 CLK(NULL, "pll1_sysclk8", &pll1_sysclk8),
442 CLK(NULL, "pll1_sysclk9", &pll1_sysclk9),
443 CLK(NULL, "pll2", &pll2_clk),
444 CLK(NULL, "pll2_aux", &pll2_aux_clk),
445 CLK(NULL, "clkout1", &clkout1_clk),
446 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
447 CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
448 CLK(NULL, "pll2_sysclk3", &pll2_sysclk3),
449 CLK(NULL, "pll2_sysclk4", &pll2_sysclk4),
450 CLK(NULL, "pll2_sysclk5", &pll2_sysclk5),
451 CLK(NULL, "pll2_sysclk6", &pll2_sysclk6),
452 CLK(NULL, "pll2_sysclk7", &pll2_sysclk7),
453 CLK(NULL, "pll2_sysclk8", &pll2_sysclk8),
454 CLK(NULL, "pll2_sysclk9", &pll2_sysclk9),
455 CLK(NULL, "vpss_dac", &vpss_dac_clk),
9a3e89b1
LP		 456 CLK("vpss", "master", &vpss_master_clk),
457 CLK("vpss", "slave", &vpss_slave_clk),
fb8fcb89 458 CLK(NULL, "arm", &arm_clk),
19955c3d
MP		 459 CLK("serial8250.0", NULL, &uart0_clk),
460 CLK("serial8250.1", NULL, &uart1_clk),
fb8fcb89 461 CLK("i2c_davinci.1", NULL, &i2c_clk),
d7ca4c75
MP		 462 CLK("da830-mmc.0", NULL, &mmcsd0_clk),
463 CLK("da830-mmc.1", NULL, &mmcsd1_clk),
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SP		 464 CLK("spi_davinci.0", NULL, &spi0_clk),
465 CLK("spi_davinci.1", NULL, &spi1_clk),
466 CLK("spi_davinci.2", NULL, &spi2_clk),
467 CLK("spi_davinci.3", NULL, &spi3_clk),
468 CLK("spi_davinci.4", NULL, &spi4_clk),
469 CLK(NULL, "gpio", &gpio_clk),
470 CLK(NULL, "aemif", &aemif_clk),
471 CLK(NULL, "pwm0", &pwm0_clk),
472 CLK(NULL, "pwm1", &pwm1_clk),
473 CLK(NULL, "pwm2", &pwm2_clk),
474 CLK(NULL, "pwm3", &pwm3_clk),
475 CLK(NULL, "timer0", &timer0_clk),
476 CLK(NULL, "timer1", &timer1_clk),
84374812 477 CLK("davinci-wdt", NULL, &timer2_clk),
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SP		 478 CLK(NULL, "timer3", &timer3_clk),
479 CLK(NULL, "usb", &usb_clk),
480 CLK("davinci_emac.1", NULL, &emac_clk),
46c18334 481 CLK("davinci_mdio.0", "fck", &emac_clk),
e89861e9 482 CLK("davinci_voicecodec", NULL, &voicecodec_clk),
bedad0ca 483 CLK("davinci-mcbsp", NULL, &asp0_clk),
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SP		 484 CLK(NULL, "rto", &rto_clk),
485 CLK(NULL, "mjcp", &mjcp_clk),
486 CLK(NULL, NULL, NULL),
487};
488
489/*----------------------------------------------------------------------*/
490
fb8fcb89
SP		 491#define INTMUX 0x18
492#define EVTMUX 0x1c
493
494
495static const struct mux_config dm365_pins[] = {
496#ifdef CONFIG_DAVINCI_MUX
497MUX_CFG(DM365, MMCSD0, 0, 24, 1, 0, false)
498
499MUX_CFG(DM365, SD1_CLK, 0, 16, 3, 1, false)
500MUX_CFG(DM365, SD1_CMD, 4, 30, 3, 1, false)
501MUX_CFG(DM365, SD1_DATA3, 4, 28, 3, 1, false)
502MUX_CFG(DM365, SD1_DATA2, 4, 26, 3, 1, false)
503MUX_CFG(DM365, SD1_DATA1, 4, 24, 3, 1, false)
504MUX_CFG(DM365, SD1_DATA0, 4, 22, 3, 1, false)
505
506MUX_CFG(DM365, I2C_SDA, 3, 23, 3, 2, false)
507MUX_CFG(DM365, I2C_SCL, 3, 21, 3, 2, false)
508
7735227e
TK		 509MUX_CFG(DM365, AEMIF_AR_A14, 2, 0, 3, 1, false)
510MUX_CFG(DM365, AEMIF_AR_BA0, 2, 0, 3, 2, false)
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SP		 511MUX_CFG(DM365, AEMIF_A3, 2, 2, 3, 1, false)
512MUX_CFG(DM365, AEMIF_A7, 2, 4, 3, 1, false)
513MUX_CFG(DM365, AEMIF_D15_8, 2, 6, 1, 1, false)
514MUX_CFG(DM365, AEMIF_CE0, 2, 7, 1, 0, false)
7735227e
TK		 515MUX_CFG(DM365, AEMIF_CE1, 2, 8, 1, 0, false)
516MUX_CFG(DM365, AEMIF_WE_OE, 2, 9, 1, 0, false)
fb8fcb89
SP		 517
518MUX_CFG(DM365, MCBSP0_BDX, 0, 23, 1, 1, false)
519MUX_CFG(DM365, MCBSP0_X, 0, 22, 1, 1, false)
520MUX_CFG(DM365, MCBSP0_BFSX, 0, 21, 1, 1, false)
521MUX_CFG(DM365, MCBSP0_BDR, 0, 20, 1, 1, false)
522MUX_CFG(DM365, MCBSP0_R, 0, 19, 1, 1, false)
523MUX_CFG(DM365, MCBSP0_BFSR, 0, 18, 1, 1, false)
524
525MUX_CFG(DM365, SPI0_SCLK, 3, 28, 1, 1, false)
526MUX_CFG(DM365, SPI0_SDI, 3, 26, 3, 1, false)
527MUX_CFG(DM365, SPI0_SDO, 3, 25, 1, 1, false)
528MUX_CFG(DM365, SPI0_SDENA0, 3, 29, 3, 1, false)
529MUX_CFG(DM365, SPI0_SDENA1, 3, 26, 3, 2, false)
530
531MUX_CFG(DM365, UART0_RXD, 3, 20, 1, 1, false)
532MUX_CFG(DM365, UART0_TXD, 3, 19, 1, 1, false)
533MUX_CFG(DM365, UART1_RXD, 3, 17, 3, 2, false)
534MUX_CFG(DM365, UART1_TXD, 3, 15, 3, 2, false)
535MUX_CFG(DM365, UART1_RTS, 3, 23, 3, 1, false)
536MUX_CFG(DM365, UART1_CTS, 3, 21, 3, 1, false)
537
538MUX_CFG(DM365, EMAC_TX_EN, 3, 17, 3, 1, false)
539MUX_CFG(DM365, EMAC_TX_CLK, 3, 15, 3, 1, false)
540MUX_CFG(DM365, EMAC_COL, 3, 14, 1, 1, false)
541MUX_CFG(DM365, EMAC_TXD3, 3, 13, 1, 1, false)
542MUX_CFG(DM365, EMAC_TXD2, 3, 12, 1, 1, false)
543MUX_CFG(DM365, EMAC_TXD1, 3, 11, 1, 1, false)
544MUX_CFG(DM365, EMAC_TXD0, 3, 10, 1, 1, false)
545MUX_CFG(DM365, EMAC_RXD3, 3, 9, 1, 1, false)
546MUX_CFG(DM365, EMAC_RXD2, 3, 8, 1, 1, false)
547MUX_CFG(DM365, EMAC_RXD1, 3, 7, 1, 1, false)
548MUX_CFG(DM365, EMAC_RXD0, 3, 6, 1, 1, false)
549MUX_CFG(DM365, EMAC_RX_CLK, 3, 5, 1, 1, false)
550MUX_CFG(DM365, EMAC_RX_DV, 3, 4, 1, 1, false)
551MUX_CFG(DM365, EMAC_RX_ER, 3, 3, 1, 1, false)
552MUX_CFG(DM365, EMAC_CRS, 3, 2, 1, 1, false)
553MUX_CFG(DM365, EMAC_MDIO, 3, 1, 1, 1, false)
554MUX_CFG(DM365, EMAC_MDCLK, 3, 0, 1, 1, false)
9f513153 555
990c09d5 556MUX_CFG(DM365, KEYSCAN, 2, 0, 0x3f, 0x3f, false)
9f513153 557
af5dbaef
SP		 558MUX_CFG(DM365, PWM0, 1, 0, 3, 2, false)
559MUX_CFG(DM365, PWM0_G23, 3, 26, 3, 3, false)
560MUX_CFG(DM365, PWM1, 1, 2, 3, 2, false)
561MUX_CFG(DM365, PWM1_G25, 3, 29, 3, 2, false)
562MUX_CFG(DM365, PWM2_G87, 1, 10, 3, 2, false)
563MUX_CFG(DM365, PWM2_G88, 1, 8, 3, 2, false)
564MUX_CFG(DM365, PWM2_G89, 1, 6, 3, 2, false)
565MUX_CFG(DM365, PWM2_G90, 1, 4, 3, 2, false)
566MUX_CFG(DM365, PWM3_G80, 1, 20, 3, 3, false)
567MUX_CFG(DM365, PWM3_G81, 1, 18, 3, 3, false)
568MUX_CFG(DM365, PWM3_G85, 1, 14, 3, 2, false)
569MUX_CFG(DM365, PWM3_G86, 1, 12, 3, 2, false)
570
571MUX_CFG(DM365, SPI1_SCLK, 4, 2, 3, 1, false)
572MUX_CFG(DM365, SPI1_SDI, 3, 31, 1, 1, false)
573MUX_CFG(DM365, SPI1_SDO, 4, 0, 3, 1, false)
574MUX_CFG(DM365, SPI1_SDENA0, 4, 4, 3, 1, false)
575MUX_CFG(DM365, SPI1_SDENA1, 4, 0, 3, 2, false)
576
577MUX_CFG(DM365, SPI2_SCLK, 4, 10, 3, 1, false)
578MUX_CFG(DM365, SPI2_SDI, 4, 6, 3, 1, false)
579MUX_CFG(DM365, SPI2_SDO, 4, 8, 3, 1, false)
580MUX_CFG(DM365, SPI2_SDENA0, 4, 12, 3, 1, false)
581MUX_CFG(DM365, SPI2_SDENA1, 4, 8, 3, 2, false)
582
583MUX_CFG(DM365, SPI3_SCLK, 0, 0, 3, 2, false)
584MUX_CFG(DM365, SPI3_SDI, 0, 2, 3, 2, false)
585MUX_CFG(DM365, SPI3_SDO, 0, 6, 3, 2, false)
586MUX_CFG(DM365, SPI3_SDENA0, 0, 4, 3, 2, false)
587MUX_CFG(DM365, SPI3_SDENA1, 0, 6, 3, 3, false)
588
589MUX_CFG(DM365, SPI4_SCLK, 4, 18, 3, 1, false)
590MUX_CFG(DM365, SPI4_SDI, 4, 14, 3, 1, false)
591MUX_CFG(DM365, SPI4_SDO, 4, 16, 3, 1, false)
592MUX_CFG(DM365, SPI4_SDENA0, 4, 20, 3, 1, false)
593MUX_CFG(DM365, SPI4_SDENA1, 4, 16, 3, 2, false)
594
0efe2b74
TK		 595MUX_CFG(DM365, CLKOUT0, 4, 20, 3, 3, false)
596MUX_CFG(DM365, CLKOUT1, 4, 16, 3, 3, false)
597MUX_CFG(DM365, CLKOUT2, 4, 8, 3, 3, false)
598
af5dbaef 599MUX_CFG(DM365, GPIO20, 3, 21, 3, 0, false)
2168e76d
TK		 600MUX_CFG(DM365, GPIO30, 4, 6, 3, 0, false)
601MUX_CFG(DM365, GPIO31, 4, 8, 3, 0, false)
602MUX_CFG(DM365, GPIO32, 4, 10, 3, 0, false)
af5dbaef
SP		 603MUX_CFG(DM365, GPIO33, 4, 12, 3, 0, false)
604MUX_CFG(DM365, GPIO40, 4, 26, 3, 0, false)
ce100669 605MUX_CFG(DM365, GPIO64_57, 2, 6, 1, 0, false)
af5dbaef
SP		 606
607MUX_CFG(DM365, VOUT_FIELD, 1, 18, 3, 1, false)
608MUX_CFG(DM365, VOUT_FIELD_G81, 1, 18, 3, 0, false)
609MUX_CFG(DM365, VOUT_HVSYNC, 1, 16, 1, 0, false)
610MUX_CFG(DM365, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false)
611MUX_CFG(DM365, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false)
612MUX_CFG(DM365, VIN_CAM_WEN, 0, 14, 3, 0, false)
613MUX_CFG(DM365, VIN_CAM_VD, 0, 13, 1, 0, false)
614MUX_CFG(DM365, VIN_CAM_HD, 0, 12, 1, 0, false)
866d2869
SP		 615MUX_CFG(DM365, VIN_YIN4_7_EN, 0, 0, 0xff, 0, false)
616MUX_CFG(DM365, VIN_YIN0_3_EN, 0, 8, 0xf, 0, false)
af5dbaef 617
9f513153
SP		 618INT_CFG(DM365, INT_EDMA_CC, 2, 1, 1, false)
619INT_CFG(DM365, INT_EDMA_TC0_ERR, 3, 1, 1, false)
620INT_CFG(DM365, INT_EDMA_TC1_ERR, 4, 1, 1, false)
621INT_CFG(DM365, INT_EDMA_TC2_ERR, 22, 1, 1, false)
622INT_CFG(DM365, INT_EDMA_TC3_ERR, 23, 1, 1, false)
623INT_CFG(DM365, INT_PRTCSS, 10, 1, 1, false)
624INT_CFG(DM365, INT_EMAC_RXTHRESH, 14, 1, 1, false)
625INT_CFG(DM365, INT_EMAC_RXPULSE, 15, 1, 1, false)
626INT_CFG(DM365, INT_EMAC_TXPULSE, 16, 1, 1, false)
627INT_CFG(DM365, INT_EMAC_MISCPULSE, 17, 1, 1, false)
0c30e0d3
SP		 628INT_CFG(DM365, INT_IMX0_ENABLE, 0, 1, 0, false)
629INT_CFG(DM365, INT_IMX0_DISABLE, 0, 1, 1, false)
630INT_CFG(DM365, INT_HDVICP_ENABLE, 0, 1, 1, false)
631INT_CFG(DM365, INT_HDVICP_DISABLE, 0, 1, 0, false)
632INT_CFG(DM365, INT_IMX1_ENABLE, 24, 1, 1, false)
633INT_CFG(DM365, INT_IMX1_DISABLE, 24, 1, 0, false)
634INT_CFG(DM365, INT_NSF_ENABLE, 25, 1, 1, false)
635INT_CFG(DM365, INT_NSF_DISABLE, 25, 1, 0, false)
e9ab3214
MA		 636
637EVT_CFG(DM365, EVT2_ASP_TX, 0, 1, 0, false)
638EVT_CFG(DM365, EVT3_ASP_RX, 1, 1, 0, false)
e89861e9
MA		 639EVT_CFG(DM365, EVT2_VC_TX, 0, 1, 1, false)
640EVT_CFG(DM365, EVT3_VC_RX, 1, 1, 1, false)
fb8fcb89
SP		 641#endif
642};
643
a3e13e89
SP		 644static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
645
646static struct davinci_spi_platform_data dm365_spi0_pdata = {
647 .version = SPI_VERSION_1,
648 .num_chipselect = 2,
2e3e2a5e 649 .dma_event_q = EVENTQ_3,
1b0838b5 650 .prescaler_limit = 1,
a3e13e89
SP		 651};
652
653static struct resource dm365_spi0_resources[] = {
654 {
655 .start = 0x01c66000,
656 .end = 0x01c667ff,
657 .flags = IORESOURCE_MEM,
658 },
659 {
660 .start = IRQ_DM365_SPIINT0_0,
661 .flags = IORESOURCE_IRQ,
662 },
663 {
664 .start = 17,
665 .flags = IORESOURCE_DMA,
666 },
667 {
668 .start = 16,
669 .flags = IORESOURCE_DMA,
670 },
a3e13e89
SP		 671};
672
673static struct platform_device dm365_spi0_device = {
674 .name = "spi_davinci",
675 .id = 0,
676 .dev = {
677 .dma_mask = &dm365_spi0_dma_mask,
678 .coherent_dma_mask = DMA_BIT_MASK(32),
679 .platform_data = &dm365_spi0_pdata,
680 },
681 .num_resources = ARRAY_SIZE(dm365_spi0_resources),
682 .resource = dm365_spi0_resources,
683};
684
685void __init dm365_init_spi0(unsigned chipselect_mask,
d65566e5 686 const struct spi_board_info *info, unsigned len)
a3e13e89
SP		 687{
688 davinci_cfg_reg(DM365_SPI0_SCLK);
689 davinci_cfg_reg(DM365_SPI0_SDI);
690 davinci_cfg_reg(DM365_SPI0_SDO);
691
692 /* not all slaves will be wired up */
693 if (chipselect_mask & BIT(0))
694 davinci_cfg_reg(DM365_SPI0_SDENA0);
695 if (chipselect_mask & BIT(1))
696 davinci_cfg_reg(DM365_SPI0_SDENA1);
697
698 spi_register_board_info(info, len);
699
700 platform_device_register(&dm365_spi0_device);
701}
702
9cc1515c
PA		 703static struct resource dm365_gpio_resources[] = {
704 { /* registers */
705 .start = DAVINCI_GPIO_BASE,
706 .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
707 .flags = IORESOURCE_MEM,
708 },
709 { /* interrupt */
710 .start = IRQ_DM365_GPIO0,
711 .end = IRQ_DM365_GPIO7,
712 .flags = IORESOURCE_IRQ,
713 },
714};
715
716static struct davinci_gpio_platform_data dm365_gpio_platform_data = {
717 .ngpio = 104,
9cc1515c
PA		 718 .gpio_unbanked = 8,
719};
720
721int __init dm365_gpio_register(void)
722{
723 return davinci_gpio_register(dm365_gpio_resources,
e462f1f5 724 ARRAY_SIZE(dm365_gpio_resources),
9cc1515c
PA		 725 &dm365_gpio_platform_data);
726}
727
8ed0a9d4
SP		 728static struct emac_platform_data dm365_emac_pdata = {
729 .ctrl_reg_offset = DM365_EMAC_CNTRL_OFFSET,
730 .ctrl_mod_reg_offset = DM365_EMAC_CNTRL_MOD_OFFSET,
731 .ctrl_ram_offset = DM365_EMAC_CNTRL_RAM_OFFSET,
8ed0a9d4
SP		 732 .ctrl_ram_size = DM365_EMAC_CNTRL_RAM_SIZE,
733 .version = EMAC_VERSION_2,
734};
735
736static struct resource dm365_emac_resources[] = {
737 {
738 .start = DM365_EMAC_BASE,
d22960c8 739 .end = DM365_EMAC_BASE + SZ_16K - 1,
8ed0a9d4
SP		 740 .flags = IORESOURCE_MEM,
741 },
742 {
743 .start = IRQ_DM365_EMAC_RXTHRESH,
744 .end = IRQ_DM365_EMAC_RXTHRESH,
745 .flags = IORESOURCE_IRQ,
746 },
747 {
748 .start = IRQ_DM365_EMAC_RXPULSE,
749 .end = IRQ_DM365_EMAC_RXPULSE,
750 .flags = IORESOURCE_IRQ,
751 },
752 {
753 .start = IRQ_DM365_EMAC_TXPULSE,
754 .end = IRQ_DM365_EMAC_TXPULSE,
755 .flags = IORESOURCE_IRQ,
756 },
757 {
758 .start = IRQ_DM365_EMAC_MISCPULSE,
759 .end = IRQ_DM365_EMAC_MISCPULSE,
760 .flags = IORESOURCE_IRQ,
761 },
762};
763
764static struct platform_device dm365_emac_device = {
765 .name = "davinci_emac",
766 .id = 1,
767 .dev = {
768 .platform_data = &dm365_emac_pdata,
769 },
770 .num_resources = ARRAY_SIZE(dm365_emac_resources),
771 .resource = dm365_emac_resources,
772};
fb8fcb89 773
d22960c8
CC		 774static struct resource dm365_mdio_resources[] = {
775 {
776 .start = DM365_EMAC_MDIO_BASE,
777 .end = DM365_EMAC_MDIO_BASE + SZ_4K - 1,
778 .flags = IORESOURCE_MEM,
779 },
780};
781
782static struct platform_device dm365_mdio_device = {
783 .name = "davinci_mdio",
784 .id = 0,
785 .num_resources = ARRAY_SIZE(dm365_mdio_resources),
786 .resource = dm365_mdio_resources,
787};
788
fb8fcb89
SP		 789static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
790 [IRQ_VDINT0] = 2,
791 [IRQ_VDINT1] = 6,
792 [IRQ_VDINT2] = 6,
793 [IRQ_HISTINT] = 6,
794 [IRQ_H3AINT] = 6,
795 [IRQ_PRVUINT] = 6,
796 [IRQ_RSZINT] = 6,
797 [IRQ_DM365_INSFINT] = 7,
798 [IRQ_VENCINT] = 6,
799 [IRQ_ASQINT] = 6,
800 [IRQ_IMXINT] = 6,
801 [IRQ_DM365_IMCOPINT] = 4,
802 [IRQ_USBINT] = 4,
803 [IRQ_DM365_RTOINT] = 7,
804 [IRQ_DM365_TINT5] = 7,
805 [IRQ_DM365_TINT6] = 5,
806 [IRQ_CCINT0] = 5,
807 [IRQ_CCERRINT] = 5,
808 [IRQ_TCERRINT0] = 5,
809 [IRQ_TCERRINT] = 7,
810 [IRQ_PSCIN] = 4,
811 [IRQ_DM365_SPINT2_1] = 7,
812 [IRQ_DM365_TINT7] = 7,
813 [IRQ_DM365_SDIOINT0] = 7,
814 [IRQ_MBXINT] = 7,
815 [IRQ_MBRINT] = 7,
816 [IRQ_MMCINT] = 7,
817 [IRQ_DM365_MMCINT1] = 7,
818 [IRQ_DM365_PWMINT3] = 7,
fb8fcb89
SP		 819 [IRQ_AEMIFINT] = 2,
820 [IRQ_DM365_SDIOINT1] = 2,
821 [IRQ_TINT0_TINT12] = 7,
822 [IRQ_TINT0_TINT34] = 7,
823 [IRQ_TINT1_TINT12] = 7,
824 [IRQ_TINT1_TINT34] = 7,
825 [IRQ_PWMINT0] = 7,
826 [IRQ_PWMINT1] = 3,
827 [IRQ_PWMINT2] = 3,
828 [IRQ_I2C] = 3,
829 [IRQ_UARTINT0] = 3,
830 [IRQ_UARTINT1] = 3,
99381b4f 831 [IRQ_DM365_RTCINT] = 3,
fb8fcb89
SP		 832 [IRQ_DM365_SPIINT0_0] = 3,
833 [IRQ_DM365_SPIINT3_0] = 3,
834 [IRQ_DM365_GPIO0] = 3,
835 [IRQ_DM365_GPIO1] = 7,
836 [IRQ_DM365_GPIO2] = 4,
837 [IRQ_DM365_GPIO3] = 4,
838 [IRQ_DM365_GPIO4] = 7,
839 [IRQ_DM365_GPIO5] = 7,
840 [IRQ_DM365_GPIO6] = 7,
841 [IRQ_DM365_GPIO7] = 7,
842 [IRQ_DM365_EMAC_RXTHRESH] = 7,
843 [IRQ_DM365_EMAC_RXPULSE] = 7,
844 [IRQ_DM365_EMAC_TXPULSE] = 7,
845 [IRQ_DM365_EMAC_MISCPULSE] = 7,
846 [IRQ_DM365_GPIO12] = 7,
847 [IRQ_DM365_GPIO13] = 7,
848 [IRQ_DM365_GPIO14] = 7,
849 [IRQ_DM365_GPIO15] = 7,
850 [IRQ_DM365_KEYINT] = 7,
851 [IRQ_DM365_TCERRINT2] = 7,
852 [IRQ_DM365_TCERRINT3] = 7,
853 [IRQ_DM365_EMUINT] = 7,
854};
855
15061b5d 856/* Four Transfer Controllers on DM365 */
d4cb7f40 857static s8 dm365_queue_priority_mapping[][2] = {
15061b5d
SP		 858 /* {event queue no, Priority} */
859 {0, 7},
860 {1, 7},
861 {2, 7},
862 {3, 0},
863 {-1, -1},
864};
865
0c750e1f
PU		 866static const struct dma_slave_map dm365_edma_map[] = {
867 { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 2) },
868 { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 3) },
869 { "davinci_voicecodec", "tx", EDMA_FILTER_PARAM(0, 2) },
870 { "davinci_voicecodec", "rx", EDMA_FILTER_PARAM(0, 3) },
871 { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) },
872 { "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) },
873 { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) },
874 { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) },
875 { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) },
876 { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) },
877 { "spi_davinci.3", "tx", EDMA_FILTER_PARAM(0, 18) },
878 { "spi_davinci.3", "rx", EDMA_FILTER_PARAM(0, 19) },
879 { "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
880 { "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
881 { "dm6441-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) },
882 { "dm6441-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) },
883};
884
d4cb7f40 885static struct edma_soc_info dm365_edma_pdata = {
bc3ac9f3
SN		 886 .queue_priority_mapping = dm365_queue_priority_mapping,
887 .default_queue = EVENTQ_3,
0c750e1f
PU		 888 .slave_map = dm365_edma_map,
889 .slavecnt = ARRAY_SIZE(dm365_edma_map),
bc3ac9f3
SN		 890};
891
15061b5d
SP		 892static struct resource edma_resources[] = {
893 {
d4cb7f40 894 .name = "edma3_cc",
15061b5d
SP		 895 .start = 0x01c00000,
896 .end = 0x01c00000 + SZ_64K - 1,
897 .flags = IORESOURCE_MEM,
898 },
899 {
d4cb7f40 900 .name = "edma3_tc0",
15061b5d
SP		 901 .start = 0x01c10000,
902 .end = 0x01c10000 + SZ_1K - 1,
903 .flags = IORESOURCE_MEM,
904 },
905 {
d4cb7f40 906 .name = "edma3_tc1",
15061b5d
SP		 907 .start = 0x01c10400,
908 .end = 0x01c10400 + SZ_1K - 1,
909 .flags = IORESOURCE_MEM,
910 },
911 {
d4cb7f40 912 .name = "edma3_tc2",
15061b5d
SP		 913 .start = 0x01c10800,
914 .end = 0x01c10800 + SZ_1K - 1,
915 .flags = IORESOURCE_MEM,
916 },
917 {
d4cb7f40 918 .name = "edma3_tc3",
15061b5d
SP		 919 .start = 0x01c10c00,
920 .end = 0x01c10c00 + SZ_1K - 1,
921 .flags = IORESOURCE_MEM,
922 },
923 {
d4cb7f40 924 .name = "edma3_ccint",
15061b5d
SP		 925 .start = IRQ_CCINT0,
926 .flags = IORESOURCE_IRQ,
927 },
928 {
d4cb7f40 929 .name = "edma3_ccerrint",
15061b5d
SP		 930 .start = IRQ_CCERRINT,
931 .flags = IORESOURCE_IRQ,
932 },
933 /* not using TC*_ERR */
934};
935
936static struct platform_device dm365_edma_device = {
937 .name = "edma",
938 .id = 0,
d4cb7f40 939 .dev.platform_data = &dm365_edma_pdata,
15061b5d
SP		 940 .num_resources = ARRAY_SIZE(edma_resources),
941 .resource = edma_resources,
942};
943
e9ab3214
MA		 944static struct resource dm365_asp_resources[] = {
945 {
ee880dbd 946 .name = "mpu",
e9ab3214
MA		 947 .start = DAVINCI_DM365_ASP0_BASE,
948 .end = DAVINCI_DM365_ASP0_BASE + SZ_8K - 1,
949 .flags = IORESOURCE_MEM,
950 },
951 {
952 .start = DAVINCI_DMA_ASP0_TX,
953 .end = DAVINCI_DMA_ASP0_TX,
954 .flags = IORESOURCE_DMA,
955 },
956 {
957 .start = DAVINCI_DMA_ASP0_RX,
958 .end = DAVINCI_DMA_ASP0_RX,
959 .flags = IORESOURCE_DMA,
960 },
961};
962
963static struct platform_device dm365_asp_device = {
bedad0ca
CPE		 964 .name = "davinci-mcbsp",
965 .id = -1,
e9ab3214
MA		 966 .num_resources = ARRAY_SIZE(dm365_asp_resources),
967 .resource = dm365_asp_resources,
968};
969
e89861e9
MA		 970static struct resource dm365_vc_resources[] = {
971 {
972 .start = DAVINCI_DM365_VC_BASE,
973 .end = DAVINCI_DM365_VC_BASE + SZ_1K - 1,
974 .flags = IORESOURCE_MEM,
975 },
976 {
977 .start = DAVINCI_DMA_VC_TX,
978 .end = DAVINCI_DMA_VC_TX,
979 .flags = IORESOURCE_DMA,
980 },
981 {
982 .start = DAVINCI_DMA_VC_RX,
983 .end = DAVINCI_DMA_VC_RX,
984 .flags = IORESOURCE_DMA,
985 },
986};
987
988static struct platform_device dm365_vc_device = {
989 .name = "davinci_voicecodec",
990 .id = -1,
991 .num_resources = ARRAY_SIZE(dm365_vc_resources),
992 .resource = dm365_vc_resources,
993};
994
99381b4f
MA		 995static struct resource dm365_rtc_resources[] = {
996 {
997 .start = DM365_RTC_BASE,
998 .end = DM365_RTC_BASE + SZ_1K - 1,
999 .flags = IORESOURCE_MEM,
1000 },
1001 {
1002 .start = IRQ_DM365_RTCINT,
1003 .flags = IORESOURCE_IRQ,
1004 },
1005};
1006
1007static struct platform_device dm365_rtc_device = {
1008 .name = "rtc_davinci",
1009 .id = 0,
1010 .num_resources = ARRAY_SIZE(dm365_rtc_resources),
1011 .resource = dm365_rtc_resources,
1012};
1013
fb8fcb89
SP		 1014static struct map_desc dm365_io_desc[] = {
1015 {
1016 .virtual = IO_VIRT,
1017 .pfn = __phys_to_pfn(IO_PHYS),
1018 .length = IO_SIZE,
1019 .type = MT_DEVICE
1020 },
fb8fcb89
SP		 1021};
1022
990c09d5
MA		 1023static struct resource dm365_ks_resources[] = {
1024 {
1025 /* registers */
1026 .start = DM365_KEYSCAN_BASE,
1027 .end = DM365_KEYSCAN_BASE + SZ_1K - 1,
1028 .flags = IORESOURCE_MEM,
1029 },
1030 {
1031 /* interrupt */
1032 .start = IRQ_DM365_KEYINT,
1033 .end = IRQ_DM365_KEYINT,
1034 .flags = IORESOURCE_IRQ,
1035 },
1036};
1037
1038static struct platform_device dm365_ks_device = {
1039 .name = "davinci_keyscan",
1040 .id = 0,
1041 .num_resources = ARRAY_SIZE(dm365_ks_resources),
1042 .resource = dm365_ks_resources,
1043};
1044
fb8fcb89
SP		 1045/* Contents of JTAG ID register used to identify exact cpu type */
1046static struct davinci_id dm365_ids[] = {
1047 {
1048 .variant = 0x0,
1049 .part_no = 0xb83e,
1050 .manufacturer = 0x017,
1051 .cpu_id = DAVINCI_CPU_ID_DM365,
cc36e97b
SP		 1052 .name = "dm365_rev1.1",
1053 },
1054 {
1055 .variant = 0x8,
1056 .part_no = 0xb83e,
1057 .manufacturer = 0x017,
1058 .cpu_id = DAVINCI_CPU_ID_DM365,
1059 .name = "dm365_rev1.2",
fb8fcb89
SP		 1060 },
1061};
1062
e4c822c7 1063static u32 dm365_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
fb8fcb89 1064
28552c2e 1065static struct davinci_timer_info dm365_timer_info = {
fb8fcb89
SP		 1066 .timers = davinci_timer_instance,
1067 .clockevent_id = T0_BOT,
1068 .clocksource_id = T0_TOP,
1069};
1070
a2767b41
TK		 1071#define DM365_UART1_BASE (IO_PHYS + 0x106000)
1072
19955c3d 1073static struct plat_serial8250_port dm365_serial0_platform_data[] = {
fb8fcb89
SP		 1074 {
1075 .mapbase = DAVINCI_UART0_BASE,
1076 .irq = IRQ_UARTINT0,
1077 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
1078 UPF_IOREMAP,
1079 .iotype = UPIO_MEM,
1080 .regshift = 2,
1081 },
19955c3d
MP		 1082 {
1083 .flags = 0,
1084 }
1085};
1086static struct plat_serial8250_port dm365_serial1_platform_data[] = {
fb8fcb89 1087 {
a2767b41 1088 .mapbase = DM365_UART1_BASE,
fb8fcb89
SP		 1089 .irq = IRQ_UARTINT1,
1090 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
1091 UPF_IOREMAP,
1092 .iotype = UPIO_MEM,
1093 .regshift = 2,
1094 },
1095 {
19955c3d
MP		 1096 .flags = 0,
1097 }
fb8fcb89
SP		 1098};
1099
fcf7157b 1100struct platform_device dm365_serial_device[] = {
19955c3d
MP		 1101 {
1102 .name = "serial8250",
1103 .id = PLAT8250_DEV_PLATFORM,
1104 .dev = {
1105 .platform_data = dm365_serial0_platform_data,
1106 }
fb8fcb89 1107 },
19955c3d
MP		 1108 {
1109 .name = "serial8250",
1110 .id = PLAT8250_DEV_PLATFORM1,
1111 .dev = {
1112 .platform_data = dm365_serial1_platform_data,
1113 }
fb8fcb89 1114 },
19955c3d
MP		 1115 {
1116 }
fb8fcb89
SP		 1117};
1118
1119static struct davinci_soc_info davinci_soc_info_dm365 = {
1120 .io_desc = dm365_io_desc,
1121 .io_desc_num = ARRAY_SIZE(dm365_io_desc),
3347db83 1122 .jtag_id_reg = 0x01c40028,
fb8fcb89
SP		 1123 .ids = dm365_ids,
1124 .ids_num = ARRAY_SIZE(dm365_ids),
1125 .cpu_clks = dm365_clks,
1126 .psc_bases = dm365_psc_bases,
1127 .psc_bases_num = ARRAY_SIZE(dm365_psc_bases),
779b0d53 1128 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
fb8fcb89
SP		 1129 .pinmux_pins = dm365_pins,
1130 .pinmux_pins_num = ARRAY_SIZE(dm365_pins),
bd808947 1131 .intc_base = DAVINCI_ARM_INTC_BASE,
fb8fcb89
SP		 1132 .intc_type = DAVINCI_INTC_TYPE_AINTC,
1133 .intc_irq_prios = dm365_default_priorities,
1134 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
1135 .timer_info = &dm365_timer_info,
8ed0a9d4 1136 .emac_pdata = &dm365_emac_pdata,
fb8fcb89
SP		 1137 .sram_dma = 0x00010000,
1138 .sram_len = SZ_32K,
1139};
1140
e9ab3214
MA		 1141void __init dm365_init_asp(struct snd_platform_data *pdata)
1142{
1143 davinci_cfg_reg(DM365_MCBSP0_BDX);
1144 davinci_cfg_reg(DM365_MCBSP0_X);
1145 davinci_cfg_reg(DM365_MCBSP0_BFSX);
1146 davinci_cfg_reg(DM365_MCBSP0_BDR);
1147 davinci_cfg_reg(DM365_MCBSP0_R);
1148 davinci_cfg_reg(DM365_MCBSP0_BFSR);
1149 davinci_cfg_reg(DM365_EVT2_ASP_TX);
1150 davinci_cfg_reg(DM365_EVT3_ASP_RX);
1151 dm365_asp_device.dev.platform_data = pdata;
1152 platform_device_register(&dm365_asp_device);
1153}
1154
e89861e9
MA		 1155void __init dm365_init_vc(struct snd_platform_data *pdata)
1156{
1157 davinci_cfg_reg(DM365_EVT2_VC_TX);
1158 davinci_cfg_reg(DM365_EVT3_VC_RX);
1159 dm365_vc_device.dev.platform_data = pdata;
1160 platform_device_register(&dm365_vc_device);
1161}
1162
990c09d5
MA		 1163void __init dm365_init_ks(struct davinci_ks_platform_data *pdata)
1164{
990c09d5
MA		 1165 dm365_ks_device.dev.platform_data = pdata;
1166 platform_device_register(&dm365_ks_device);
1167}
1168
99381b4f
MA		 1169void __init dm365_init_rtc(void)
1170{
1171 davinci_cfg_reg(DM365_INT_PRTCSS);
1172 platform_device_register(&dm365_rtc_device);
1173}
1174
fb8fcb89
SP		 1175void __init dm365_init(void)
1176{
1177 davinci_common_init(&davinci_soc_info_dm365);
5cfb19ac 1178 davinci_map_sysmod();
6fc9ebbd 1179 davinci_clk_init(davinci_soc_info_dm365.cpu_clks);
fb8fcb89 1180}
8ed0a9d4 1181
f2a4c59d
MK		 1182static struct resource dm365_vpss_resources[] = {
1183 {
1184 /* VPSS ISP5 Base address */
1185 .name = "isp5",
1186 .start = 0x01c70000,
1187 .end = 0x01c70000 + 0xff,
1188 .flags = IORESOURCE_MEM,
1189 },
1190 {
1191 /* VPSS CLK Base address */
1192 .name = "vpss",
1193 .start = 0x01c70200,
1194 .end = 0x01c70200 + 0xff,
1195 .flags = IORESOURCE_MEM,
1196 },
1197};
1198
1199static struct platform_device dm365_vpss_device = {
1200 .name = "vpss",
1201 .id = -1,
1202 .dev.platform_data = "dm365_vpss",
1203 .num_resources = ARRAY_SIZE(dm365_vpss_resources),
1204 .resource = dm365_vpss_resources,
1205};
1206
1207static struct resource vpfe_resources[] = {
1208 {
1209 .start = IRQ_VDINT0,
1210 .end = IRQ_VDINT0,
1211 .flags = IORESOURCE_IRQ,
1212 },
1213 {
1214 .start = IRQ_VDINT1,
1215 .end = IRQ_VDINT1,
1216 .flags = IORESOURCE_IRQ,
1217 },
1218};
1219
1220static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
1221static struct platform_device vpfe_capture_dev = {
1222 .name = CAPTURE_DRV_NAME,
1223 .id = -1,
1224 .num_resources = ARRAY_SIZE(vpfe_resources),
1225 .resource = vpfe_resources,
1226 .dev = {
1227 .dma_mask = &vpfe_capture_dma_mask,
1228 .coherent_dma_mask = DMA_BIT_MASK(32),
1229 },
1230};
1231
1232static void dm365_isif_setup_pinmux(void)
1233{
1234 davinci_cfg_reg(DM365_VIN_CAM_WEN);
1235 davinci_cfg_reg(DM365_VIN_CAM_VD);
1236 davinci_cfg_reg(DM365_VIN_CAM_HD);
1237 davinci_cfg_reg(DM365_VIN_YIN4_7_EN);
1238 davinci_cfg_reg(DM365_VIN_YIN0_3_EN);
1239}
1240
1241static struct resource isif_resource[] = {
1242 /* ISIF Base address */
1243 {
1244 .start = 0x01c71000,
1245 .end = 0x01c71000 + 0x1ff,
1246 .flags = IORESOURCE_MEM,
1247 },
1248 /* ISIF Linearization table 0 */
1249 {
1250 .start = 0x1C7C000,
1251 .end = 0x1C7C000 + 0x2ff,
1252 .flags = IORESOURCE_MEM,
1253 },
1254 /* ISIF Linearization table 1 */
1255 {
1256 .start = 0x1C7C400,
1257 .end = 0x1C7C400 + 0x2ff,
1258 .flags = IORESOURCE_MEM,
1259 },
1260};
1261static struct platform_device dm365_isif_dev = {
1262 .name = "isif",
1263 .id = -1,
1264 .num_resources = ARRAY_SIZE(isif_resource),
1265 .resource = isif_resource,
1266 .dev = {
1267 .dma_mask = &vpfe_capture_dma_mask,
1268 .coherent_dma_mask = DMA_BIT_MASK(32),
1269 .platform_data = dm365_isif_setup_pinmux,
1270 },
1271};
1272
120c6604
LP		 1273static struct resource dm365_osd_resources[] = {
1274 {
1275 .start = DM365_OSD_BASE,
1276 .end = DM365_OSD_BASE + 0xff,
1277 .flags = IORESOURCE_MEM,
1278 },
1279};
1280
1281static u64 dm365_video_dma_mask = DMA_BIT_MASK(32);
1282
1283static struct platform_device dm365_osd_dev = {
1284 .name = DM365_VPBE_OSD_SUBDEV_NAME,
1285 .id = -1,
1286 .num_resources = ARRAY_SIZE(dm365_osd_resources),
1287 .resource = dm365_osd_resources,
1288 .dev = {
1289 .dma_mask = &dm365_video_dma_mask,
1290 .coherent_dma_mask = DMA_BIT_MASK(32),
1291 },
1292};
1293
1294static struct resource dm365_venc_resources[] = {
1295 {
1296 .start = IRQ_VENCINT,
1297 .end = IRQ_VENCINT,
1298 .flags = IORESOURCE_IRQ,
1299 },
1300 /* venc registers io space */
1301 {
1302 .start = DM365_VENC_BASE,
1303 .end = DM365_VENC_BASE + 0x177,
1304 .flags = IORESOURCE_MEM,
1305 },
1306 /* vdaccfg registers io space */
1307 {
1308 .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG,
1309 .end = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3,
1310 .flags = IORESOURCE_MEM,
1311 },
1312};
1313
1314static struct resource dm365_v4l2_disp_resources[] = {
1315 {
1316 .start = IRQ_VENCINT,
1317 .end = IRQ_VENCINT,
1318 .flags = IORESOURCE_IRQ,
1319 },
1320 /* venc registers io space */
1321 {
1322 .start = DM365_VENC_BASE,
1323 .end = DM365_VENC_BASE + 0x177,
1324 .flags = IORESOURCE_MEM,
1325 },
1326};
1327
27ffaeb0 1328static int dm365_vpbe_setup_pinmux(u32 if_type, int field)
120c6604
LP		 1329{
1330 switch (if_type) {
27ffaeb0 1331 case MEDIA_BUS_FMT_SGRBG8_1X8:
120c6604
LP		 1332 davinci_cfg_reg(DM365_VOUT_FIELD_G81);
1333 davinci_cfg_reg(DM365_VOUT_COUTL_EN);
1334 davinci_cfg_reg(DM365_VOUT_COUTH_EN);
1335 break;
27ffaeb0 1336 case MEDIA_BUS_FMT_YUYV10_1X20:
120c6604
LP		 1337 if (field)
1338 davinci_cfg_reg(DM365_VOUT_FIELD);
1339 else
1340 davinci_cfg_reg(DM365_VOUT_FIELD_G81);
1341 davinci_cfg_reg(DM365_VOUT_COUTL_EN);
1342 davinci_cfg_reg(DM365_VOUT_COUTH_EN);
1343 break;
1344 default:
1345 return -EINVAL;
1346 }
1347
1348 return 0;
1349}
1350
1351static int dm365_venc_setup_clock(enum vpbe_enc_timings_type type,
1352 unsigned int pclock)
1353{
1354 void __iomem *vpss_clkctl_reg;
1355 u32 val;
1356
1357 vpss_clkctl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL);
1358
1359 switch (type) {
1360 case VPBE_ENC_STD:
1361 val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
1362 break;
1363 case VPBE_ENC_DV_TIMINGS:
1364 if (pclock <= 27000000) {
1365 val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
1366 } else {
1367 /* set sysclk4 to output 74.25 MHz from pll1 */
1368 val = VPSS_PLLC2SYSCLK5_ENABLE | VPSS_DACCLKEN_ENABLE |
1369 VPSS_VENCCLKEN_ENABLE;
1370 }
1371 break;
1372 default:
1373 return -EINVAL;
1374 }
1375 writel(val, vpss_clkctl_reg);
1376
1377 return 0;
1378}
1379
1380static struct platform_device dm365_vpbe_display = {
1381 .name = "vpbe-v4l2",
1382 .id = -1,
1383 .num_resources = ARRAY_SIZE(dm365_v4l2_disp_resources),
1384 .resource = dm365_v4l2_disp_resources,
1385 .dev = {
1386 .dma_mask = &dm365_video_dma_mask,
1387 .coherent_dma_mask = DMA_BIT_MASK(32),
1388 },
1389};
1390
9c559708 1391static struct venc_platform_data dm365_venc_pdata = {
120c6604
LP		 1392 .setup_pinmux = dm365_vpbe_setup_pinmux,
1393 .setup_clock = dm365_venc_setup_clock,
1394};
1395
1396static struct platform_device dm365_venc_dev = {
1397 .name = DM365_VPBE_VENC_SUBDEV_NAME,
1398 .id = -1,
1399 .num_resources = ARRAY_SIZE(dm365_venc_resources),
1400 .resource = dm365_venc_resources,
1401 .dev = {
1402 .dma_mask = &dm365_video_dma_mask,
1403 .coherent_dma_mask = DMA_BIT_MASK(32),
1404 .platform_data = (void *)&dm365_venc_pdata,
1405 },
1406};
1407
1408static struct platform_device dm365_vpbe_dev = {
1409 .name = "vpbe_controller",
1410 .id = -1,
1411 .dev = {
1412 .dma_mask = &dm365_video_dma_mask,
1413 .coherent_dma_mask = DMA_BIT_MASK(32),
1414 },
1415};
1416
1417int __init dm365_init_video(struct vpfe_config *vpfe_cfg,
1418 struct vpbe_config *vpbe_cfg)
1419{
1420 if (vpfe_cfg || vpbe_cfg)
1421 platform_device_register(&dm365_vpss_device);
1422
1423 if (vpfe_cfg) {
1424 vpfe_capture_dev.dev.platform_data = vpfe_cfg;
1425 platform_device_register(&dm365_isif_dev);
1426 platform_device_register(&vpfe_capture_dev);
1427 }
1428 if (vpbe_cfg) {
1429 dm365_vpbe_dev.dev.platform_data = vpbe_cfg;
1430 platform_device_register(&dm365_osd_dev);
1431 platform_device_register(&dm365_venc_dev);
1432 platform_device_register(&dm365_vpbe_dev);
1433 platform_device_register(&dm365_vpbe_display);
1434 }
1435
1436 return 0;
1437}
1438
8ed0a9d4
SP		 1439static int __init dm365_init_devices(void)
1440{
1233090c
SN		 1441 int ret = 0;
1442
8ed0a9d4
SP		 1443 if (!cpu_is_davinci_dm365())
1444 return 0;
1445
15061b5d
SP		 1446 davinci_cfg_reg(DM365_INT_EDMA_CC);
1447 platform_device_register(&dm365_edma_device);
d22960c8
CC		 1448
1449 platform_device_register(&dm365_mdio_device);
8ed0a9d4 1450 platform_device_register(&dm365_emac_device);
d22960c8 1451
1233090c
SN		 1452 ret = davinci_init_wdt();
1453 if (ret)
1454 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
1455
1456 return ret;
8ed0a9d4
SP		 1457}
1458postcore_initcall(dm365_init_devices);
Linux kernel - Deliverables
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