projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
davinci: DMx and da8xx defconfig updates
[deliverable/linux.git] / arch / arm / mach-davinci / dm365.c
CommitLineData
fb8fcb89
SP		 1/*
2 * TI DaVinci DM365 chip specific setup
3 *
4 * Copyright (C) 2009 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
fb8fcb89
SP		 15#include <linux/init.h>
16#include <linux/clk.h>
17#include <linux/serial_8250.h>
18#include <linux/platform_device.h>
19#include <linux/dma-mapping.h>
20#include <linux/gpio.h>
21
22#include <asm/mach/map.h>
23
24#include <mach/dm365.h>
fb8fcb89
SP		 25#include <mach/cputype.h>
26#include <mach/edma.h>
27#include <mach/psc.h>
28#include <mach/mux.h>
29#include <mach/irqs.h>
30#include <mach/time.h>
31#include <mach/serial.h>
32#include <mach/common.h>
e9ab3214 33#include <mach/asp.h>
fb8fcb89
SP		 34
35#include "clock.h"
36#include "mux.h"
37
38#define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */
39
40static struct pll_data pll1_data = {
41 .num = 1,
42 .phys_base = DAVINCI_PLL1_BASE,
43 .flags = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
44};
45
46static struct pll_data pll2_data = {
47 .num = 2,
48 .phys_base = DAVINCI_PLL2_BASE,
49 .flags = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
50};
51
52static struct clk ref_clk = {
53 .name = "ref_clk",
54 .rate = DM365_REF_FREQ,
55};
56
57static struct clk pll1_clk = {
58 .name = "pll1",
59 .parent = &ref_clk,
60 .flags = CLK_PLL,
61 .pll_data = &pll1_data,
62};
63
64static struct clk pll1_aux_clk = {
65 .name = "pll1_aux_clk",
66 .parent = &pll1_clk,
67 .flags = CLK_PLL | PRE_PLL,
68};
69
70static struct clk pll1_sysclkbp = {
71 .name = "pll1_sysclkbp",
72 .parent = &pll1_clk,
73 .flags = CLK_PLL | PRE_PLL,
74 .div_reg = BPDIV
75};
76
77static struct clk clkout0_clk = {
78 .name = "clkout0",
79 .parent = &pll1_clk,
80 .flags = CLK_PLL | PRE_PLL,
81};
82
83static struct clk pll1_sysclk1 = {
84 .name = "pll1_sysclk1",
85 .parent = &pll1_clk,
86 .flags = CLK_PLL,
87 .div_reg = PLLDIV1,
88};
89
90static struct clk pll1_sysclk2 = {
91 .name = "pll1_sysclk2",
92 .parent = &pll1_clk,
93 .flags = CLK_PLL,
94 .div_reg = PLLDIV2,
95};
96
97static struct clk pll1_sysclk3 = {
98 .name = "pll1_sysclk3",
99 .parent = &pll1_clk,
100 .flags = CLK_PLL,
101 .div_reg = PLLDIV3,
102};
103
104static struct clk pll1_sysclk4 = {
105 .name = "pll1_sysclk4",
106 .parent = &pll1_clk,
107 .flags = CLK_PLL,
108 .div_reg = PLLDIV4,
109};
110
111static struct clk pll1_sysclk5 = {
112 .name = "pll1_sysclk5",
113 .parent = &pll1_clk,
114 .flags = CLK_PLL,
115 .div_reg = PLLDIV5,
116};
117
118static struct clk pll1_sysclk6 = {
119 .name = "pll1_sysclk6",
120 .parent = &pll1_clk,
121 .flags = CLK_PLL,
122 .div_reg = PLLDIV6,
123};
124
125static struct clk pll1_sysclk7 = {
126 .name = "pll1_sysclk7",
127 .parent = &pll1_clk,
128 .flags = CLK_PLL,
129 .div_reg = PLLDIV7,
130};
131
132static struct clk pll1_sysclk8 = {
133 .name = "pll1_sysclk8",
134 .parent = &pll1_clk,
135 .flags = CLK_PLL,
136 .div_reg = PLLDIV8,
137};
138
139static struct clk pll1_sysclk9 = {
140 .name = "pll1_sysclk9",
141 .parent = &pll1_clk,
142 .flags = CLK_PLL,
143 .div_reg = PLLDIV9,
144};
145
146static struct clk pll2_clk = {
147 .name = "pll2",
148 .parent = &ref_clk,
149 .flags = CLK_PLL,
150 .pll_data = &pll2_data,
151};
152
153static struct clk pll2_aux_clk = {
154 .name = "pll2_aux_clk",
155 .parent = &pll2_clk,
156 .flags = CLK_PLL | PRE_PLL,
157};
158
159static struct clk clkout1_clk = {
160 .name = "clkout1",
161 .parent = &pll2_clk,
162 .flags = CLK_PLL | PRE_PLL,
163};
164
165static struct clk pll2_sysclk1 = {
166 .name = "pll2_sysclk1",
167 .parent = &pll2_clk,
168 .flags = CLK_PLL,
169 .div_reg = PLLDIV1,
170};
171
172static struct clk pll2_sysclk2 = {
173 .name = "pll2_sysclk2",
174 .parent = &pll2_clk,
175 .flags = CLK_PLL,
176 .div_reg = PLLDIV2,
177};
178
179static struct clk pll2_sysclk3 = {
180 .name = "pll2_sysclk3",
181 .parent = &pll2_clk,
182 .flags = CLK_PLL,
183 .div_reg = PLLDIV3,
184};
185
186static struct clk pll2_sysclk4 = {
187 .name = "pll2_sysclk4",
188 .parent = &pll2_clk,
189 .flags = CLK_PLL,
190 .div_reg = PLLDIV4,
191};
192
193static struct clk pll2_sysclk5 = {
194 .name = "pll2_sysclk5",
195 .parent = &pll2_clk,
196 .flags = CLK_PLL,
197 .div_reg = PLLDIV5,
198};
199
200static struct clk pll2_sysclk6 = {
201 .name = "pll2_sysclk6",
202 .parent = &pll2_clk,
203 .flags = CLK_PLL,
204 .div_reg = PLLDIV6,
205};
206
207static struct clk pll2_sysclk7 = {
208 .name = "pll2_sysclk7",
209 .parent = &pll2_clk,
210 .flags = CLK_PLL,
211 .div_reg = PLLDIV7,
212};
213
214static struct clk pll2_sysclk8 = {
215 .name = "pll2_sysclk8",
216 .parent = &pll2_clk,
217 .flags = CLK_PLL,
218 .div_reg = PLLDIV8,
219};
220
221static struct clk pll2_sysclk9 = {
222 .name = "pll2_sysclk9",
223 .parent = &pll2_clk,
224 .flags = CLK_PLL,
225 .div_reg = PLLDIV9,
226};
227
228static struct clk vpss_dac_clk = {
229 .name = "vpss_dac",
230 .parent = &pll1_sysclk3,
231 .lpsc = DM365_LPSC_DAC_CLK,
232};
233
234static struct clk vpss_master_clk = {
235 .name = "vpss_master",
236 .parent = &pll1_sysclk5,
237 .lpsc = DM365_LPSC_VPSSMSTR,
238 .flags = CLK_PSC,
239};
240
241static struct clk arm_clk = {
242 .name = "arm_clk",
243 .parent = &pll2_sysclk2,
244 .lpsc = DAVINCI_LPSC_ARM,
245 .flags = ALWAYS_ENABLED,
246};
247
248static struct clk uart0_clk = {
249 .name = "uart0",
250 .parent = &pll1_aux_clk,
251 .lpsc = DAVINCI_LPSC_UART0,
252};
253
254static struct clk uart1_clk = {
255 .name = "uart1",
256 .parent = &pll1_sysclk4,
257 .lpsc = DAVINCI_LPSC_UART1,
258};
259
260static struct clk i2c_clk = {
261 .name = "i2c",
262 .parent = &pll1_aux_clk,
263 .lpsc = DAVINCI_LPSC_I2C,
264};
265
266static struct clk mmcsd0_clk = {
267 .name = "mmcsd0",
268 .parent = &pll1_sysclk8,
269 .lpsc = DAVINCI_LPSC_MMC_SD,
270};
271
272static struct clk mmcsd1_clk = {
273 .name = "mmcsd1",
274 .parent = &pll1_sysclk4,
275 .lpsc = DM365_LPSC_MMC_SD1,
276};
277
278static struct clk spi0_clk = {
279 .name = "spi0",
280 .parent = &pll1_sysclk4,
281 .lpsc = DAVINCI_LPSC_SPI,
282};
283
284static struct clk spi1_clk = {
285 .name = "spi1",
286 .parent = &pll1_sysclk4,
287 .lpsc = DM365_LPSC_SPI1,
288};
289
290static struct clk spi2_clk = {
291 .name = "spi2",
292 .parent = &pll1_sysclk4,
293 .lpsc = DM365_LPSC_SPI2,
294};
295
296static struct clk spi3_clk = {
297 .name = "spi3",
298 .parent = &pll1_sysclk4,
299 .lpsc = DM365_LPSC_SPI3,
300};
301
302static struct clk spi4_clk = {
303 .name = "spi4",
304 .parent = &pll1_aux_clk,
305 .lpsc = DM365_LPSC_SPI4,
306};
307
308static struct clk gpio_clk = {
309 .name = "gpio",
310 .parent = &pll1_sysclk4,
311 .lpsc = DAVINCI_LPSC_GPIO,
312};
313
314static struct clk aemif_clk = {
315 .name = "aemif",
316 .parent = &pll1_sysclk4,
317 .lpsc = DAVINCI_LPSC_AEMIF,
318};
319
320static struct clk pwm0_clk = {
321 .name = "pwm0",
322 .parent = &pll1_aux_clk,
323 .lpsc = DAVINCI_LPSC_PWM0,
324};
325
326static struct clk pwm1_clk = {
327 .name = "pwm1",
328 .parent = &pll1_aux_clk,
329 .lpsc = DAVINCI_LPSC_PWM1,
330};
331
332static struct clk pwm2_clk = {
333 .name = "pwm2",
334 .parent = &pll1_aux_clk,
335 .lpsc = DAVINCI_LPSC_PWM2,
336};
337
338static struct clk pwm3_clk = {
339 .name = "pwm3",
340 .parent = &ref_clk,
341 .lpsc = DM365_LPSC_PWM3,
342};
343
344static struct clk timer0_clk = {
345 .name = "timer0",
346 .parent = &pll1_aux_clk,
347 .lpsc = DAVINCI_LPSC_TIMER0,
348};
349
350static struct clk timer1_clk = {
351 .name = "timer1",
352 .parent = &pll1_aux_clk,
353 .lpsc = DAVINCI_LPSC_TIMER1,
354};
355
356static struct clk timer2_clk = {
357 .name = "timer2",
358 .parent = &pll1_aux_clk,
359 .lpsc = DAVINCI_LPSC_TIMER2,
360 .usecount = 1,
361};
362
363static struct clk timer3_clk = {
364 .name = "timer3",
365 .parent = &pll1_aux_clk,
366 .lpsc = DM365_LPSC_TIMER3,
367};
368
369static struct clk usb_clk = {
370 .name = "usb",
ed160672 371 .parent = &pll1_aux_clk,
fb8fcb89
SP		 372 .lpsc = DAVINCI_LPSC_USB,
373};
374
375static struct clk emac_clk = {
376 .name = "emac",
377 .parent = &pll1_sysclk4,
378 .lpsc = DM365_LPSC_EMAC,
379};
380
381static struct clk voicecodec_clk = {
382 .name = "voice_codec",
383 .parent = &pll2_sysclk4,
384 .lpsc = DM365_LPSC_VOICE_CODEC,
385};
386
387static struct clk asp0_clk = {
388 .name = "asp0",
389 .parent = &pll1_sysclk4,
390 .lpsc = DM365_LPSC_McBSP1,
391};
392
393static struct clk rto_clk = {
394 .name = "rto",
395 .parent = &pll1_sysclk4,
396 .lpsc = DM365_LPSC_RTO,
397};
398
399static struct clk mjcp_clk = {
400 .name = "mjcp",
401 .parent = &pll1_sysclk3,
402 .lpsc = DM365_LPSC_MJCP,
403};
404
405static struct davinci_clk dm365_clks[] = {
406 CLK(NULL, "ref", &ref_clk),
407 CLK(NULL, "pll1", &pll1_clk),
408 CLK(NULL, "pll1_aux", &pll1_aux_clk),
409 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
410 CLK(NULL, "clkout0", &clkout0_clk),
411 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
412 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
413 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
414 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
415 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
416 CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
417 CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
418 CLK(NULL, "pll1_sysclk8", &pll1_sysclk8),
419 CLK(NULL, "pll1_sysclk9", &pll1_sysclk9),
420 CLK(NULL, "pll2", &pll2_clk),
421 CLK(NULL, "pll2_aux", &pll2_aux_clk),
422 CLK(NULL, "clkout1", &clkout1_clk),
423 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
424 CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
425 CLK(NULL, "pll2_sysclk3", &pll2_sysclk3),
426 CLK(NULL, "pll2_sysclk4", &pll2_sysclk4),
427 CLK(NULL, "pll2_sysclk5", &pll2_sysclk5),
428 CLK(NULL, "pll2_sysclk6", &pll2_sysclk6),
429 CLK(NULL, "pll2_sysclk7", &pll2_sysclk7),
430 CLK(NULL, "pll2_sysclk8", &pll2_sysclk8),
431 CLK(NULL, "pll2_sysclk9", &pll2_sysclk9),
432 CLK(NULL, "vpss_dac", &vpss_dac_clk),
433 CLK(NULL, "vpss_master", &vpss_master_clk),
434 CLK(NULL, "arm", &arm_clk),
435 CLK(NULL, "uart0", &uart0_clk),
436 CLK(NULL, "uart1", &uart1_clk),
437 CLK("i2c_davinci.1", NULL, &i2c_clk),
438 CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
439 CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
440 CLK("spi_davinci.0", NULL, &spi0_clk),
441 CLK("spi_davinci.1", NULL, &spi1_clk),
442 CLK("spi_davinci.2", NULL, &spi2_clk),
443 CLK("spi_davinci.3", NULL, &spi3_clk),
444 CLK("spi_davinci.4", NULL, &spi4_clk),
445 CLK(NULL, "gpio", &gpio_clk),
446 CLK(NULL, "aemif", &aemif_clk),
447 CLK(NULL, "pwm0", &pwm0_clk),
448 CLK(NULL, "pwm1", &pwm1_clk),
449 CLK(NULL, "pwm2", &pwm2_clk),
450 CLK(NULL, "pwm3", &pwm3_clk),
451 CLK(NULL, "timer0", &timer0_clk),
452 CLK(NULL, "timer1", &timer1_clk),
453 CLK("watchdog", NULL, &timer2_clk),
454 CLK(NULL, "timer3", &timer3_clk),
455 CLK(NULL, "usb", &usb_clk),
456 CLK("davinci_emac.1", NULL, &emac_clk),
457 CLK("voice_codec", NULL, &voicecodec_clk),
e9ab3214 458 CLK("davinci-asp.0", NULL, &asp0_clk),
fb8fcb89
SP		 459 CLK(NULL, "rto", &rto_clk),
460 CLK(NULL, "mjcp", &mjcp_clk),
461 CLK(NULL, NULL, NULL),
462};
463
464/*----------------------------------------------------------------------*/
465
466#define PINMUX0 0x00
467#define PINMUX1 0x04
468#define PINMUX2 0x08
469#define PINMUX3 0x0c
470#define PINMUX4 0x10
471#define INTMUX 0x18
472#define EVTMUX 0x1c
473
474
475static const struct mux_config dm365_pins[] = {
476#ifdef CONFIG_DAVINCI_MUX
477MUX_CFG(DM365, MMCSD0, 0, 24, 1, 0, false)
478
479MUX_CFG(DM365, SD1_CLK, 0, 16, 3, 1, false)
480MUX_CFG(DM365, SD1_CMD, 4, 30, 3, 1, false)
481MUX_CFG(DM365, SD1_DATA3, 4, 28, 3, 1, false)
482MUX_CFG(DM365, SD1_DATA2, 4, 26, 3, 1, false)
483MUX_CFG(DM365, SD1_DATA1, 4, 24, 3, 1, false)
484MUX_CFG(DM365, SD1_DATA0, 4, 22, 3, 1, false)
485
486MUX_CFG(DM365, I2C_SDA, 3, 23, 3, 2, false)
487MUX_CFG(DM365, I2C_SCL, 3, 21, 3, 2, false)
488
489MUX_CFG(DM365, AEMIF_AR, 2, 0, 3, 1, false)
490MUX_CFG(DM365, AEMIF_A3, 2, 2, 3, 1, false)
491MUX_CFG(DM365, AEMIF_A7, 2, 4, 3, 1, false)
492MUX_CFG(DM365, AEMIF_D15_8, 2, 6, 1, 1, false)
493MUX_CFG(DM365, AEMIF_CE0, 2, 7, 1, 0, false)
494
495MUX_CFG(DM365, MCBSP0_BDX, 0, 23, 1, 1, false)
496MUX_CFG(DM365, MCBSP0_X, 0, 22, 1, 1, false)
497MUX_CFG(DM365, MCBSP0_BFSX, 0, 21, 1, 1, false)
498MUX_CFG(DM365, MCBSP0_BDR, 0, 20, 1, 1, false)
499MUX_CFG(DM365, MCBSP0_R, 0, 19, 1, 1, false)
500MUX_CFG(DM365, MCBSP0_BFSR, 0, 18, 1, 1, false)
501
502MUX_CFG(DM365, SPI0_SCLK, 3, 28, 1, 1, false)
503MUX_CFG(DM365, SPI0_SDI, 3, 26, 3, 1, false)
504MUX_CFG(DM365, SPI0_SDO, 3, 25, 1, 1, false)
505MUX_CFG(DM365, SPI0_SDENA0, 3, 29, 3, 1, false)
506MUX_CFG(DM365, SPI0_SDENA1, 3, 26, 3, 2, false)
507
508MUX_CFG(DM365, UART0_RXD, 3, 20, 1, 1, false)
509MUX_CFG(DM365, UART0_TXD, 3, 19, 1, 1, false)
510MUX_CFG(DM365, UART1_RXD, 3, 17, 3, 2, false)
511MUX_CFG(DM365, UART1_TXD, 3, 15, 3, 2, false)
512MUX_CFG(DM365, UART1_RTS, 3, 23, 3, 1, false)
513MUX_CFG(DM365, UART1_CTS, 3, 21, 3, 1, false)
514
515MUX_CFG(DM365, EMAC_TX_EN, 3, 17, 3, 1, false)
516MUX_CFG(DM365, EMAC_TX_CLK, 3, 15, 3, 1, false)
517MUX_CFG(DM365, EMAC_COL, 3, 14, 1, 1, false)
518MUX_CFG(DM365, EMAC_TXD3, 3, 13, 1, 1, false)
519MUX_CFG(DM365, EMAC_TXD2, 3, 12, 1, 1, false)
520MUX_CFG(DM365, EMAC_TXD1, 3, 11, 1, 1, false)
521MUX_CFG(DM365, EMAC_TXD0, 3, 10, 1, 1, false)
522MUX_CFG(DM365, EMAC_RXD3, 3, 9, 1, 1, false)
523MUX_CFG(DM365, EMAC_RXD2, 3, 8, 1, 1, false)
524MUX_CFG(DM365, EMAC_RXD1, 3, 7, 1, 1, false)
525MUX_CFG(DM365, EMAC_RXD0, 3, 6, 1, 1, false)
526MUX_CFG(DM365, EMAC_RX_CLK, 3, 5, 1, 1, false)
527MUX_CFG(DM365, EMAC_RX_DV, 3, 4, 1, 1, false)
528MUX_CFG(DM365, EMAC_RX_ER, 3, 3, 1, 1, false)
529MUX_CFG(DM365, EMAC_CRS, 3, 2, 1, 1, false)
530MUX_CFG(DM365, EMAC_MDIO, 3, 1, 1, 1, false)
531MUX_CFG(DM365, EMAC_MDCLK, 3, 0, 1, 1, false)
9f513153
SP		 532
533MUX_CFG(DM365, KEYPAD, 2, 0, 0x3f, 0x3f, false)
534
af5dbaef
SP		 535MUX_CFG(DM365, PWM0, 1, 0, 3, 2, false)
536MUX_CFG(DM365, PWM0_G23, 3, 26, 3, 3, false)
537MUX_CFG(DM365, PWM1, 1, 2, 3, 2, false)
538MUX_CFG(DM365, PWM1_G25, 3, 29, 3, 2, false)
539MUX_CFG(DM365, PWM2_G87, 1, 10, 3, 2, false)
540MUX_CFG(DM365, PWM2_G88, 1, 8, 3, 2, false)
541MUX_CFG(DM365, PWM2_G89, 1, 6, 3, 2, false)
542MUX_CFG(DM365, PWM2_G90, 1, 4, 3, 2, false)
543MUX_CFG(DM365, PWM3_G80, 1, 20, 3, 3, false)
544MUX_CFG(DM365, PWM3_G81, 1, 18, 3, 3, false)
545MUX_CFG(DM365, PWM3_G85, 1, 14, 3, 2, false)
546MUX_CFG(DM365, PWM3_G86, 1, 12, 3, 2, false)
547
548MUX_CFG(DM365, SPI1_SCLK, 4, 2, 3, 1, false)
549MUX_CFG(DM365, SPI1_SDI, 3, 31, 1, 1, false)
550MUX_CFG(DM365, SPI1_SDO, 4, 0, 3, 1, false)
551MUX_CFG(DM365, SPI1_SDENA0, 4, 4, 3, 1, false)
552MUX_CFG(DM365, SPI1_SDENA1, 4, 0, 3, 2, false)
553
554MUX_CFG(DM365, SPI2_SCLK, 4, 10, 3, 1, false)
555MUX_CFG(DM365, SPI2_SDI, 4, 6, 3, 1, false)
556MUX_CFG(DM365, SPI2_SDO, 4, 8, 3, 1, false)
557MUX_CFG(DM365, SPI2_SDENA0, 4, 12, 3, 1, false)
558MUX_CFG(DM365, SPI2_SDENA1, 4, 8, 3, 2, false)
559
560MUX_CFG(DM365, SPI3_SCLK, 0, 0, 3, 2, false)
561MUX_CFG(DM365, SPI3_SDI, 0, 2, 3, 2, false)
562MUX_CFG(DM365, SPI3_SDO, 0, 6, 3, 2, false)
563MUX_CFG(DM365, SPI3_SDENA0, 0, 4, 3, 2, false)
564MUX_CFG(DM365, SPI3_SDENA1, 0, 6, 3, 3, false)
565
566MUX_CFG(DM365, SPI4_SCLK, 4, 18, 3, 1, false)
567MUX_CFG(DM365, SPI4_SDI, 4, 14, 3, 1, false)
568MUX_CFG(DM365, SPI4_SDO, 4, 16, 3, 1, false)
569MUX_CFG(DM365, SPI4_SDENA0, 4, 20, 3, 1, false)
570MUX_CFG(DM365, SPI4_SDENA1, 4, 16, 3, 2, false)
571
572MUX_CFG(DM365, GPIO20, 3, 21, 3, 0, false)
573MUX_CFG(DM365, GPIO33, 4, 12, 3, 0, false)
574MUX_CFG(DM365, GPIO40, 4, 26, 3, 0, false)
575
576MUX_CFG(DM365, VOUT_FIELD, 1, 18, 3, 1, false)
577MUX_CFG(DM365, VOUT_FIELD_G81, 1, 18, 3, 0, false)
578MUX_CFG(DM365, VOUT_HVSYNC, 1, 16, 1, 0, false)
579MUX_CFG(DM365, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false)
580MUX_CFG(DM365, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false)
581MUX_CFG(DM365, VIN_CAM_WEN, 0, 14, 3, 0, false)
582MUX_CFG(DM365, VIN_CAM_VD, 0, 13, 1, 0, false)
583MUX_CFG(DM365, VIN_CAM_HD, 0, 12, 1, 0, false)
866d2869
SP		 584MUX_CFG(DM365, VIN_YIN4_7_EN, 0, 0, 0xff, 0, false)
585MUX_CFG(DM365, VIN_YIN0_3_EN, 0, 8, 0xf, 0, false)
af5dbaef 586
9f513153
SP		 587INT_CFG(DM365, INT_EDMA_CC, 2, 1, 1, false)
588INT_CFG(DM365, INT_EDMA_TC0_ERR, 3, 1, 1, false)
589INT_CFG(DM365, INT_EDMA_TC1_ERR, 4, 1, 1, false)
590INT_CFG(DM365, INT_EDMA_TC2_ERR, 22, 1, 1, false)
591INT_CFG(DM365, INT_EDMA_TC3_ERR, 23, 1, 1, false)
592INT_CFG(DM365, INT_PRTCSS, 10, 1, 1, false)
593INT_CFG(DM365, INT_EMAC_RXTHRESH, 14, 1, 1, false)
594INT_CFG(DM365, INT_EMAC_RXPULSE, 15, 1, 1, false)
595INT_CFG(DM365, INT_EMAC_TXPULSE, 16, 1, 1, false)
596INT_CFG(DM365, INT_EMAC_MISCPULSE, 17, 1, 1, false)
0c30e0d3
SP		 597INT_CFG(DM365, INT_IMX0_ENABLE, 0, 1, 0, false)
598INT_CFG(DM365, INT_IMX0_DISABLE, 0, 1, 1, false)
599INT_CFG(DM365, INT_HDVICP_ENABLE, 0, 1, 1, false)
600INT_CFG(DM365, INT_HDVICP_DISABLE, 0, 1, 0, false)
601INT_CFG(DM365, INT_IMX1_ENABLE, 24, 1, 1, false)
602INT_CFG(DM365, INT_IMX1_DISABLE, 24, 1, 0, false)
603INT_CFG(DM365, INT_NSF_ENABLE, 25, 1, 1, false)
604INT_CFG(DM365, INT_NSF_DISABLE, 25, 1, 0, false)
e9ab3214
MA		 605
606EVT_CFG(DM365, EVT2_ASP_TX, 0, 1, 0, false)
607EVT_CFG(DM365, EVT3_ASP_RX, 1, 1, 0, false)
fb8fcb89
SP		 608#endif
609};
610
8ed0a9d4
SP		 611static struct emac_platform_data dm365_emac_pdata = {
612 .ctrl_reg_offset = DM365_EMAC_CNTRL_OFFSET,
613 .ctrl_mod_reg_offset = DM365_EMAC_CNTRL_MOD_OFFSET,
614 .ctrl_ram_offset = DM365_EMAC_CNTRL_RAM_OFFSET,
615 .mdio_reg_offset = DM365_EMAC_MDIO_OFFSET,
616 .ctrl_ram_size = DM365_EMAC_CNTRL_RAM_SIZE,
617 .version = EMAC_VERSION_2,
618};
619
620static struct resource dm365_emac_resources[] = {
621 {
622 .start = DM365_EMAC_BASE,
623 .end = DM365_EMAC_BASE + 0x47ff,
624 .flags = IORESOURCE_MEM,
625 },
626 {
627 .start = IRQ_DM365_EMAC_RXTHRESH,
628 .end = IRQ_DM365_EMAC_RXTHRESH,
629 .flags = IORESOURCE_IRQ,
630 },
631 {
632 .start = IRQ_DM365_EMAC_RXPULSE,
633 .end = IRQ_DM365_EMAC_RXPULSE,
634 .flags = IORESOURCE_IRQ,
635 },
636 {
637 .start = IRQ_DM365_EMAC_TXPULSE,
638 .end = IRQ_DM365_EMAC_TXPULSE,
639 .flags = IORESOURCE_IRQ,
640 },
641 {
642 .start = IRQ_DM365_EMAC_MISCPULSE,
643 .end = IRQ_DM365_EMAC_MISCPULSE,
644 .flags = IORESOURCE_IRQ,
645 },
646};
647
648static struct platform_device dm365_emac_device = {
649 .name = "davinci_emac",
650 .id = 1,
651 .dev = {
652 .platform_data = &dm365_emac_pdata,
653 },
654 .num_resources = ARRAY_SIZE(dm365_emac_resources),
655 .resource = dm365_emac_resources,
656};
fb8fcb89
SP		 657
658static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
659 [IRQ_VDINT0] = 2,
660 [IRQ_VDINT1] = 6,
661 [IRQ_VDINT2] = 6,
662 [IRQ_HISTINT] = 6,
663 [IRQ_H3AINT] = 6,
664 [IRQ_PRVUINT] = 6,
665 [IRQ_RSZINT] = 6,
666 [IRQ_DM365_INSFINT] = 7,
667 [IRQ_VENCINT] = 6,
668 [IRQ_ASQINT] = 6,
669 [IRQ_IMXINT] = 6,
670 [IRQ_DM365_IMCOPINT] = 4,
671 [IRQ_USBINT] = 4,
672 [IRQ_DM365_RTOINT] = 7,
673 [IRQ_DM365_TINT5] = 7,
674 [IRQ_DM365_TINT6] = 5,
675 [IRQ_CCINT0] = 5,
676 [IRQ_CCERRINT] = 5,
677 [IRQ_TCERRINT0] = 5,
678 [IRQ_TCERRINT] = 7,
679 [IRQ_PSCIN] = 4,
680 [IRQ_DM365_SPINT2_1] = 7,
681 [IRQ_DM365_TINT7] = 7,
682 [IRQ_DM365_SDIOINT0] = 7,
683 [IRQ_MBXINT] = 7,
684 [IRQ_MBRINT] = 7,
685 [IRQ_MMCINT] = 7,
686 [IRQ_DM365_MMCINT1] = 7,
687 [IRQ_DM365_PWMINT3] = 7,
688 [IRQ_DDRINT] = 4,
689 [IRQ_AEMIFINT] = 2,
690 [IRQ_DM365_SDIOINT1] = 2,
691 [IRQ_TINT0_TINT12] = 7,
692 [IRQ_TINT0_TINT34] = 7,
693 [IRQ_TINT1_TINT12] = 7,
694 [IRQ_TINT1_TINT34] = 7,
695 [IRQ_PWMINT0] = 7,
696 [IRQ_PWMINT1] = 3,
697 [IRQ_PWMINT2] = 3,
698 [IRQ_I2C] = 3,
699 [IRQ_UARTINT0] = 3,
700 [IRQ_UARTINT1] = 3,
701 [IRQ_DM365_SPIINT0_0] = 3,
702 [IRQ_DM365_SPIINT3_0] = 3,
703 [IRQ_DM365_GPIO0] = 3,
704 [IRQ_DM365_GPIO1] = 7,
705 [IRQ_DM365_GPIO2] = 4,
706 [IRQ_DM365_GPIO3] = 4,
707 [IRQ_DM365_GPIO4] = 7,
708 [IRQ_DM365_GPIO5] = 7,
709 [IRQ_DM365_GPIO6] = 7,
710 [IRQ_DM365_GPIO7] = 7,
711 [IRQ_DM365_EMAC_RXTHRESH] = 7,
712 [IRQ_DM365_EMAC_RXPULSE] = 7,
713 [IRQ_DM365_EMAC_TXPULSE] = 7,
714 [IRQ_DM365_EMAC_MISCPULSE] = 7,
715 [IRQ_DM365_GPIO12] = 7,
716 [IRQ_DM365_GPIO13] = 7,
717 [IRQ_DM365_GPIO14] = 7,
718 [IRQ_DM365_GPIO15] = 7,
719 [IRQ_DM365_KEYINT] = 7,
720 [IRQ_DM365_TCERRINT2] = 7,
721 [IRQ_DM365_TCERRINT3] = 7,
722 [IRQ_DM365_EMUINT] = 7,
723};
724
15061b5d
SP		 725/* Four Transfer Controllers on DM365 */
726static const s8
727dm365_queue_tc_mapping[][2] = {
728 /* {event queue no, TC no} */
729 {0, 0},
730 {1, 1},
731 {2, 2},
732 {3, 3},
733 {-1, -1},
734};
735
736static const s8
737dm365_queue_priority_mapping[][2] = {
738 /* {event queue no, Priority} */
739 {0, 7},
740 {1, 7},
741 {2, 7},
742 {3, 0},
743 {-1, -1},
744};
745
746static struct edma_soc_info dm365_edma_info[] = {
747 {
748 .n_channel = 64,
749 .n_region = 4,
750 .n_slot = 256,
751 .n_tc = 4,
752 .n_cc = 1,
753 .queue_tc_mapping = dm365_queue_tc_mapping,
754 .queue_priority_mapping = dm365_queue_priority_mapping,
a0f0202e 755 .default_queue = EVENTQ_2,
15061b5d
SP		 756 },
757};
758
759static struct resource edma_resources[] = {
760 {
761 .name = "edma_cc0",
762 .start = 0x01c00000,
763 .end = 0x01c00000 + SZ_64K - 1,
764 .flags = IORESOURCE_MEM,
765 },
766 {
767 .name = "edma_tc0",
768 .start = 0x01c10000,
769 .end = 0x01c10000 + SZ_1K - 1,
770 .flags = IORESOURCE_MEM,
771 },
772 {
773 .name = "edma_tc1",
774 .start = 0x01c10400,
775 .end = 0x01c10400 + SZ_1K - 1,
776 .flags = IORESOURCE_MEM,
777 },
778 {
779 .name = "edma_tc2",
780 .start = 0x01c10800,
781 .end = 0x01c10800 + SZ_1K - 1,
782 .flags = IORESOURCE_MEM,
783 },
784 {
785 .name = "edma_tc3",
786 .start = 0x01c10c00,
787 .end = 0x01c10c00 + SZ_1K - 1,
788 .flags = IORESOURCE_MEM,
789 },
790 {
791 .name = "edma0",
792 .start = IRQ_CCINT0,
793 .flags = IORESOURCE_IRQ,
794 },
795 {
796 .name = "edma0_err",
797 .start = IRQ_CCERRINT,
798 .flags = IORESOURCE_IRQ,
799 },
800 /* not using TC*_ERR */
801};
802
803static struct platform_device dm365_edma_device = {
804 .name = "edma",
805 .id = 0,
806 .dev.platform_data = dm365_edma_info,
807 .num_resources = ARRAY_SIZE(edma_resources),
808 .resource = edma_resources,
809};
810
e9ab3214
MA		 811static struct resource dm365_asp_resources[] = {
812 {
813 .start = DAVINCI_DM365_ASP0_BASE,
814 .end = DAVINCI_DM365_ASP0_BASE + SZ_8K - 1,
815 .flags = IORESOURCE_MEM,
816 },
817 {
818 .start = DAVINCI_DMA_ASP0_TX,
819 .end = DAVINCI_DMA_ASP0_TX,
820 .flags = IORESOURCE_DMA,
821 },
822 {
823 .start = DAVINCI_DMA_ASP0_RX,
824 .end = DAVINCI_DMA_ASP0_RX,
825 .flags = IORESOURCE_DMA,
826 },
827};
828
829static struct platform_device dm365_asp_device = {
830 .name = "davinci-asp",
831 .id = 0,
832 .num_resources = ARRAY_SIZE(dm365_asp_resources),
833 .resource = dm365_asp_resources,
834};
835
fb8fcb89
SP		 836static struct map_desc dm365_io_desc[] = {
837 {
838 .virtual = IO_VIRT,
839 .pfn = __phys_to_pfn(IO_PHYS),
840 .length = IO_SIZE,
841 .type = MT_DEVICE
842 },
843 {
844 .virtual = SRAM_VIRT,
845 .pfn = __phys_to_pfn(0x00010000),
846 .length = SZ_32K,
847 /* MT_MEMORY_NONCACHED requires supersection alignment */
848 .type = MT_DEVICE,
849 },
850};
851
852/* Contents of JTAG ID register used to identify exact cpu type */
853static struct davinci_id dm365_ids[] = {
854 {
855 .variant = 0x0,
856 .part_no = 0xb83e,
857 .manufacturer = 0x017,
858 .cpu_id = DAVINCI_CPU_ID_DM365,
cc36e97b
SP		 859 .name = "dm365_rev1.1",
860 },
861 {
862 .variant = 0x8,
863 .part_no = 0xb83e,
864 .manufacturer = 0x017,
865 .cpu_id = DAVINCI_CPU_ID_DM365,
866 .name = "dm365_rev1.2",
fb8fcb89
SP		 867 },
868};
869
870static void __iomem *dm365_psc_bases[] = {
871 IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
872};
873
874struct davinci_timer_info dm365_timer_info = {
875 .timers = davinci_timer_instance,
876 .clockevent_id = T0_BOT,
877 .clocksource_id = T0_TOP,
878};
879
880static struct plat_serial8250_port dm365_serial_platform_data[] = {
881 {
882 .mapbase = DAVINCI_UART0_BASE,
883 .irq = IRQ_UARTINT0,
884 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
885 UPF_IOREMAP,
886 .iotype = UPIO_MEM,
887 .regshift = 2,
888 },
889 {
890 .mapbase = DAVINCI_UART1_BASE,
891 .irq = IRQ_UARTINT1,
892 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
893 UPF_IOREMAP,
894 .iotype = UPIO_MEM,
895 .regshift = 2,
896 },
897 {
898 .flags = 0
899 },
900};
901
902static struct platform_device dm365_serial_device = {
903 .name = "serial8250",
904 .id = PLAT8250_DEV_PLATFORM,
905 .dev = {
906 .platform_data = dm365_serial_platform_data,
907 },
908};
909
910static struct davinci_soc_info davinci_soc_info_dm365 = {
911 .io_desc = dm365_io_desc,
912 .io_desc_num = ARRAY_SIZE(dm365_io_desc),
913 .jtag_id_base = IO_ADDRESS(0x01c40028),
914 .ids = dm365_ids,
915 .ids_num = ARRAY_SIZE(dm365_ids),
916 .cpu_clks = dm365_clks,
917 .psc_bases = dm365_psc_bases,
918 .psc_bases_num = ARRAY_SIZE(dm365_psc_bases),
919 .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
920 .pinmux_pins = dm365_pins,
921 .pinmux_pins_num = ARRAY_SIZE(dm365_pins),
922 .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
923 .intc_type = DAVINCI_INTC_TYPE_AINTC,
924 .intc_irq_prios = dm365_default_priorities,
925 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
926 .timer_info = &dm365_timer_info,
927 .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE),
928 .gpio_num = 104,
7a36071e
DB		 929 .gpio_irq = IRQ_DM365_GPIO0,
930 .gpio_unbanked = 8, /* really 16 ... skip muxed GPIOs */
fb8fcb89 931 .serial_dev = &dm365_serial_device,
8ed0a9d4 932 .emac_pdata = &dm365_emac_pdata,
fb8fcb89
SP		 933 .sram_dma = 0x00010000,
934 .sram_len = SZ_32K,
935};
936
e9ab3214
MA		 937void __init dm365_init_asp(struct snd_platform_data *pdata)
938{
939 davinci_cfg_reg(DM365_MCBSP0_BDX);
940 davinci_cfg_reg(DM365_MCBSP0_X);
941 davinci_cfg_reg(DM365_MCBSP0_BFSX);
942 davinci_cfg_reg(DM365_MCBSP0_BDR);
943 davinci_cfg_reg(DM365_MCBSP0_R);
944 davinci_cfg_reg(DM365_MCBSP0_BFSR);
945 davinci_cfg_reg(DM365_EVT2_ASP_TX);
946 davinci_cfg_reg(DM365_EVT3_ASP_RX);
947 dm365_asp_device.dev.platform_data = pdata;
948 platform_device_register(&dm365_asp_device);
949}
950
fb8fcb89
SP		 951void __init dm365_init(void)
952{
953 davinci_common_init(&davinci_soc_info_dm365);
954}
8ed0a9d4
SP		 955
956static int __init dm365_init_devices(void)
957{
958 if (!cpu_is_davinci_dm365())
959 return 0;
960
15061b5d
SP		 961 davinci_cfg_reg(DM365_INT_EDMA_CC);
962 platform_device_register(&dm365_edma_device);
8ed0a9d4
SP		 963 platform_device_register(&dm365_emac_device);
964
965 return 0;
966}
967postcore_initcall(dm365_init_devices);
Linux kernel - Deliverables
This page took 0.083892 seconds and 5 git commands to generate.