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ARM: davinci: dm646x: move private definitions to C file
[deliverable/linux.git] / arch / arm / mach-davinci / dm646x.c
CommitLineData
e38d92fd
KH		 1/*
2 * TI DaVinci DM644x chip specific setup
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
b7f080cf 11#include <linux/dma-mapping.h>
e38d92fd
KH		 12#include <linux/init.h>
13#include <linux/clk.h>
65e866a9 14#include <linux/serial_8250.h>
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KH		 15#include <linux/platform_device.h>
16
79c3c0b7
MG		 17#include <asm/mach/map.h>
18
e38d92fd 19#include <mach/dm646x.h>
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KH		 20#include <mach/cputype.h>
21#include <mach/edma.h>
22#include <mach/irqs.h>
23#include <mach/psc.h>
24#include <mach/mux.h>
f64691b3 25#include <mach/time.h>
65e866a9 26#include <mach/serial.h>
79c3c0b7 27#include <mach/common.h>
25acf553 28#include <mach/asp.h>
5f3fcf96 29#include <mach/gpio-davinci.h>
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KH		 30
31#include "clock.h"
32#include "mux.h"
33
85609c1c
MK		 34#define DAVINCI_VPIF_BASE (0x01C12000)
35#define VDD3P3V_PWDN_OFFSET (0x48)
36#define VSCLKDIS_OFFSET (0x6C)
37
38#define VDD3P3V_VID_MASK (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\
39 BIT_MASK(0))
40#define VSCLKDIS_MASK (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\
41 BIT_MASK(8))
42
e38d92fd
KH		 43/*
44 * Device specific clocks
45 */
56e580d7 46#define DM646X_REF_FREQ 27000000
e38d92fd
KH		 47#define DM646X_AUX_FREQ 24000000
48
3d091406
MH		 49#define DM646X_EMAC_BASE 0x01c80000
50#define DM646X_EMAC_MDIO_BASE (DM646X_EMAC_BASE + 0x4000)
51#define DM646X_EMAC_CNTRL_OFFSET 0x0000
52#define DM646X_EMAC_CNTRL_MOD_OFFSET 0x1000
53#define DM646X_EMAC_CNTRL_RAM_OFFSET 0x2000
54#define DM646X_EMAC_CNTRL_RAM_SIZE 0x2000
55
e38d92fd
KH		 56static struct pll_data pll1_data = {
57 .num = 1,
58 .phys_base = DAVINCI_PLL1_BASE,
59};
60
61static struct pll_data pll2_data = {
62 .num = 2,
63 .phys_base = DAVINCI_PLL2_BASE,
64};
65
66static struct clk ref_clk = {
67 .name = "ref_clk",
56e580d7
SN		 68 .rate = DM646X_REF_FREQ,
69 .set_rate = davinci_simple_set_rate,
e38d92fd
KH		 70};
71
72static struct clk aux_clkin = {
73 .name = "aux_clkin",
74 .rate = DM646X_AUX_FREQ,
75};
76
77static struct clk pll1_clk = {
78 .name = "pll1",
79 .parent = &ref_clk,
80 .pll_data = &pll1_data,
81 .flags = CLK_PLL,
82};
83
84static struct clk pll1_sysclk1 = {
85 .name = "pll1_sysclk1",
86 .parent = &pll1_clk,
87 .flags = CLK_PLL,
88 .div_reg = PLLDIV1,
89};
90
91static struct clk pll1_sysclk2 = {
92 .name = "pll1_sysclk2",
93 .parent = &pll1_clk,
94 .flags = CLK_PLL,
95 .div_reg = PLLDIV2,
96};
97
98static struct clk pll1_sysclk3 = {
99 .name = "pll1_sysclk3",
100 .parent = &pll1_clk,
101 .flags = CLK_PLL,
102 .div_reg = PLLDIV3,
103};
104
105static struct clk pll1_sysclk4 = {
106 .name = "pll1_sysclk4",
107 .parent = &pll1_clk,
108 .flags = CLK_PLL,
109 .div_reg = PLLDIV4,
110};
111
112static struct clk pll1_sysclk5 = {
113 .name = "pll1_sysclk5",
114 .parent = &pll1_clk,
115 .flags = CLK_PLL,
116 .div_reg = PLLDIV5,
117};
118
119static struct clk pll1_sysclk6 = {
120 .name = "pll1_sysclk6",
121 .parent = &pll1_clk,
122 .flags = CLK_PLL,
123 .div_reg = PLLDIV6,
124};
125
126static struct clk pll1_sysclk8 = {
127 .name = "pll1_sysclk8",
128 .parent = &pll1_clk,
129 .flags = CLK_PLL,
130 .div_reg = PLLDIV8,
131};
132
133static struct clk pll1_sysclk9 = {
134 .name = "pll1_sysclk9",
135 .parent = &pll1_clk,
136 .flags = CLK_PLL,
137 .div_reg = PLLDIV9,
138};
139
140static struct clk pll1_sysclkbp = {
141 .name = "pll1_sysclkbp",
142 .parent = &pll1_clk,
143 .flags = CLK_PLL | PRE_PLL,
144 .div_reg = BPDIV,
145};
146
147static struct clk pll1_aux_clk = {
148 .name = "pll1_aux_clk",
149 .parent = &pll1_clk,
150 .flags = CLK_PLL | PRE_PLL,
151};
152
153static struct clk pll2_clk = {
154 .name = "pll2_clk",
155 .parent = &ref_clk,
156 .pll_data = &pll2_data,
157 .flags = CLK_PLL,
158};
159
160static struct clk pll2_sysclk1 = {
161 .name = "pll2_sysclk1",
162 .parent = &pll2_clk,
163 .flags = CLK_PLL,
164 .div_reg = PLLDIV1,
165};
166
167static struct clk dsp_clk = {
168 .name = "dsp",
169 .parent = &pll1_sysclk1,
170 .lpsc = DM646X_LPSC_C64X_CPU,
e38d92fd
KH		 171 .usecount = 1, /* REVISIT how to disable? */
172};
173
174static struct clk arm_clk = {
175 .name = "arm",
176 .parent = &pll1_sysclk2,
177 .lpsc = DM646X_LPSC_ARM,
178 .flags = ALWAYS_ENABLED,
179};
180
2bcb613a
SR		 181static struct clk edma_cc_clk = {
182 .name = "edma_cc",
183 .parent = &pll1_sysclk2,
184 .lpsc = DM646X_LPSC_TPCC,
185 .flags = ALWAYS_ENABLED,
186};
187
188static struct clk edma_tc0_clk = {
189 .name = "edma_tc0",
190 .parent = &pll1_sysclk2,
191 .lpsc = DM646X_LPSC_TPTC0,
192 .flags = ALWAYS_ENABLED,
193};
194
195static struct clk edma_tc1_clk = {
196 .name = "edma_tc1",
197 .parent = &pll1_sysclk2,
198 .lpsc = DM646X_LPSC_TPTC1,
199 .flags = ALWAYS_ENABLED,
200};
201
202static struct clk edma_tc2_clk = {
203 .name = "edma_tc2",
204 .parent = &pll1_sysclk2,
205 .lpsc = DM646X_LPSC_TPTC2,
206 .flags = ALWAYS_ENABLED,
207};
208
209static struct clk edma_tc3_clk = {
210 .name = "edma_tc3",
211 .parent = &pll1_sysclk2,
212 .lpsc = DM646X_LPSC_TPTC3,
213 .flags = ALWAYS_ENABLED,
214};
215
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KH		 216static struct clk uart0_clk = {
217 .name = "uart0",
218 .parent = &aux_clkin,
219 .lpsc = DM646X_LPSC_UART0,
220};
221
222static struct clk uart1_clk = {
223 .name = "uart1",
224 .parent = &aux_clkin,
225 .lpsc = DM646X_LPSC_UART1,
226};
227
228static struct clk uart2_clk = {
229 .name = "uart2",
230 .parent = &aux_clkin,
231 .lpsc = DM646X_LPSC_UART2,
232};
233
234static struct clk i2c_clk = {
235 .name = "I2CCLK",
236 .parent = &pll1_sysclk3,
237 .lpsc = DM646X_LPSC_I2C,
238};
239
240static struct clk gpio_clk = {
241 .name = "gpio",
242 .parent = &pll1_sysclk3,
243 .lpsc = DM646X_LPSC_GPIO,
244};
245
75d0fa70
C		 246static struct clk mcasp0_clk = {
247 .name = "mcasp0",
248 .parent = &pll1_sysclk3,
249 .lpsc = DM646X_LPSC_McASP0,
250};
251
252static struct clk mcasp1_clk = {
253 .name = "mcasp1",
254 .parent = &pll1_sysclk3,
255 .lpsc = DM646X_LPSC_McASP1,
256};
257
e38d92fd
KH		 258static struct clk aemif_clk = {
259 .name = "aemif",
260 .parent = &pll1_sysclk3,
261 .lpsc = DM646X_LPSC_AEMIF,
262 .flags = ALWAYS_ENABLED,
263};
264
265static struct clk emac_clk = {
266 .name = "emac",
267 .parent = &pll1_sysclk3,
268 .lpsc = DM646X_LPSC_EMAC,
269};
270
271static struct clk pwm0_clk = {
272 .name = "pwm0",
273 .parent = &pll1_sysclk3,
274 .lpsc = DM646X_LPSC_PWM0,
275 .usecount = 1, /* REVIST: disabling hangs system */
276};
277
278static struct clk pwm1_clk = {
279 .name = "pwm1",
280 .parent = &pll1_sysclk3,
281 .lpsc = DM646X_LPSC_PWM1,
282 .usecount = 1, /* REVIST: disabling hangs system */
283};
284
285static struct clk timer0_clk = {
286 .name = "timer0",
287 .parent = &pll1_sysclk3,
288 .lpsc = DM646X_LPSC_TIMER0,
289};
290
291static struct clk timer1_clk = {
292 .name = "timer1",
293 .parent = &pll1_sysclk3,
294 .lpsc = DM646X_LPSC_TIMER1,
295};
296
297static struct clk timer2_clk = {
298 .name = "timer2",
299 .parent = &pll1_sysclk3,
300 .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */
301};
302
3e25d5f4
HP		 303
304static struct clk ide_clk = {
305 .name = "ide",
306 .parent = &pll1_sysclk4,
307 .lpsc = DAVINCI_LPSC_ATA,
308};
309
e38d92fd
KH		 310static struct clk vpif0_clk = {
311 .name = "vpif0",
312 .parent = &ref_clk,
313 .lpsc = DM646X_LPSC_VPSSMSTR,
314 .flags = ALWAYS_ENABLED,
315};
316
317static struct clk vpif1_clk = {
318 .name = "vpif1",
319 .parent = &ref_clk,
320 .lpsc = DM646X_LPSC_VPSSSLV,
321 .flags = ALWAYS_ENABLED,
322};
323
28552c2e 324static struct clk_lookup dm646x_clks[] = {
e38d92fd
KH		 325 CLK(NULL, "ref", &ref_clk),
326 CLK(NULL, "aux", &aux_clkin),
327 CLK(NULL, "pll1", &pll1_clk),
328 CLK(NULL, "pll1_sysclk", &pll1_sysclk1),
329 CLK(NULL, "pll1_sysclk", &pll1_sysclk2),
330 CLK(NULL, "pll1_sysclk", &pll1_sysclk3),
331 CLK(NULL, "pll1_sysclk", &pll1_sysclk4),
332 CLK(NULL, "pll1_sysclk", &pll1_sysclk5),
333 CLK(NULL, "pll1_sysclk", &pll1_sysclk6),
334 CLK(NULL, "pll1_sysclk", &pll1_sysclk8),
335 CLK(NULL, "pll1_sysclk", &pll1_sysclk9),
336 CLK(NULL, "pll1_sysclk", &pll1_sysclkbp),
337 CLK(NULL, "pll1_aux", &pll1_aux_clk),
338 CLK(NULL, "pll2", &pll2_clk),
339 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
340 CLK(NULL, "dsp", &dsp_clk),
341 CLK(NULL, "arm", &arm_clk),
2bcb613a
SR		 342 CLK(NULL, "edma_cc", &edma_cc_clk),
343 CLK(NULL, "edma_tc0", &edma_tc0_clk),
344 CLK(NULL, "edma_tc1", &edma_tc1_clk),
345 CLK(NULL, "edma_tc2", &edma_tc2_clk),
346 CLK(NULL, "edma_tc3", &edma_tc3_clk),
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KH		 347 CLK(NULL, "uart0", &uart0_clk),
348 CLK(NULL, "uart1", &uart1_clk),
349 CLK(NULL, "uart2", &uart2_clk),
350 CLK("i2c_davinci.1", NULL, &i2c_clk),
351 CLK(NULL, "gpio", &gpio_clk),
61aa0732
KH		 352 CLK("davinci-mcasp.0", NULL, &mcasp0_clk),
353 CLK("davinci-mcasp.1", NULL, &mcasp1_clk),
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KH		 354 CLK(NULL, "aemif", &aemif_clk),
355 CLK("davinci_emac.1", NULL, &emac_clk),
356 CLK(NULL, "pwm0", &pwm0_clk),
357 CLK(NULL, "pwm1", &pwm1_clk),
358 CLK(NULL, "timer0", &timer0_clk),
359 CLK(NULL, "timer1", &timer1_clk),
360 CLK("watchdog", NULL, &timer2_clk),
3e25d5f4 361 CLK("palm_bk3710", NULL, &ide_clk),
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KH		 362 CLK(NULL, "vpif0", &vpif0_clk),
363 CLK(NULL, "vpif1", &vpif1_clk),
364 CLK(NULL, NULL, NULL),
365};
366
972412b6
MG		 367static struct emac_platform_data dm646x_emac_pdata = {
368 .ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET,
369 .ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET,
370 .ctrl_ram_offset = DM646X_EMAC_CNTRL_RAM_OFFSET,
972412b6
MG		 371 .ctrl_ram_size = DM646X_EMAC_CNTRL_RAM_SIZE,
372 .version = EMAC_VERSION_2,
373};
374
ac7b75b5
KH		 375static struct resource dm646x_emac_resources[] = {
376 {
377 .start = DM646X_EMAC_BASE,
d22960c8 378 .end = DM646X_EMAC_BASE + SZ_16K - 1,
ac7b75b5
KH		 379 .flags = IORESOURCE_MEM,
380 },
381 {
382 .start = IRQ_DM646X_EMACRXTHINT,
383 .end = IRQ_DM646X_EMACRXTHINT,
384 .flags = IORESOURCE_IRQ,
385 },
386 {
387 .start = IRQ_DM646X_EMACRXINT,
388 .end = IRQ_DM646X_EMACRXINT,
389 .flags = IORESOURCE_IRQ,
390 },
391 {
392 .start = IRQ_DM646X_EMACTXINT,
393 .end = IRQ_DM646X_EMACTXINT,
394 .flags = IORESOURCE_IRQ,
395 },
396 {
397 .start = IRQ_DM646X_EMACMISCINT,
398 .end = IRQ_DM646X_EMACMISCINT,
399 .flags = IORESOURCE_IRQ,
400 },
401};
402
403static struct platform_device dm646x_emac_device = {
404 .name = "davinci_emac",
405 .id = 1,
972412b6
MG		 406 .dev = {
407 .platform_data = &dm646x_emac_pdata,
408 },
ac7b75b5
KH		 409 .num_resources = ARRAY_SIZE(dm646x_emac_resources),
410 .resource = dm646x_emac_resources,
411};
412
d22960c8
CC		 413static struct resource dm646x_mdio_resources[] = {
414 {
415 .start = DM646X_EMAC_MDIO_BASE,
416 .end = DM646X_EMAC_MDIO_BASE + SZ_4K - 1,
417 .flags = IORESOURCE_MEM,
418 },
419};
420
421static struct platform_device dm646x_mdio_device = {
422 .name = "davinci_mdio",
423 .id = 0,
424 .num_resources = ARRAY_SIZE(dm646x_mdio_resources),
425 .resource = dm646x_mdio_resources,
426};
427
e38d92fd
KH		 428/*
429 * Device specific mux setup
430 *
431 * soc description mux mode mode mux dbg
432 * reg offset mask mode
433 */
434static const struct mux_config dm646x_pins[] = {
0e585952 435#ifdef CONFIG_DAVINCI_MUX
3e25d5f4 436MUX_CFG(DM646X, ATAEN, 0, 0, 5, 1, true)
e38d92fd
KH		 437
438MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false)
439
440MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false)
441
442MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true)
443
444MUX_CFG(DM646X, STSOMUX_DISABLE, 0, 22, 3, 0, true)
445
446MUX_CFG(DM646X, STSIMUX_DISABLE, 0, 20, 3, 0, true)
447
448MUX_CFG(DM646X, PTSOMUX_DISABLE, 0, 18, 3, 0, true)
449
450MUX_CFG(DM646X, PTSIMUX_DISABLE, 0, 16, 3, 0, true)
451
452MUX_CFG(DM646X, STSOMUX, 0, 22, 3, 2, true)
453
454MUX_CFG(DM646X, STSIMUX, 0, 20, 3, 2, true)
455
456MUX_CFG(DM646X, PTSOMUX_PARALLEL, 0, 18, 3, 2, true)
457
458MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true)
459
460MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true)
461
462MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true)
0e585952 463#endif
e38d92fd
KH		 464};
465
673dd36f
MG		 466static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
467 [IRQ_DM646X_VP_VERTINT0] = 7,
468 [IRQ_DM646X_VP_VERTINT1] = 7,
469 [IRQ_DM646X_VP_VERTINT2] = 7,
470 [IRQ_DM646X_VP_VERTINT3] = 7,
471 [IRQ_DM646X_VP_ERRINT] = 7,
472 [IRQ_DM646X_RESERVED_1] = 7,
473 [IRQ_DM646X_RESERVED_2] = 7,
474 [IRQ_DM646X_WDINT] = 7,
475 [IRQ_DM646X_CRGENINT0] = 7,
476 [IRQ_DM646X_CRGENINT1] = 7,
477 [IRQ_DM646X_TSIFINT0] = 7,
478 [IRQ_DM646X_TSIFINT1] = 7,
479 [IRQ_DM646X_VDCEINT] = 7,
480 [IRQ_DM646X_USBINT] = 7,
481 [IRQ_DM646X_USBDMAINT] = 7,
482 [IRQ_DM646X_PCIINT] = 7,
483 [IRQ_CCINT0] = 7, /* dma */
484 [IRQ_CCERRINT] = 7, /* dma */
485 [IRQ_TCERRINT0] = 7, /* dma */
486 [IRQ_TCERRINT] = 7, /* dma */
487 [IRQ_DM646X_TCERRINT2] = 7,
488 [IRQ_DM646X_TCERRINT3] = 7,
489 [IRQ_DM646X_IDE] = 7,
490 [IRQ_DM646X_HPIINT] = 7,
491 [IRQ_DM646X_EMACRXTHINT] = 7,
492 [IRQ_DM646X_EMACRXINT] = 7,
493 [IRQ_DM646X_EMACTXINT] = 7,
494 [IRQ_DM646X_EMACMISCINT] = 7,
495 [IRQ_DM646X_MCASP0TXINT] = 7,
496 [IRQ_DM646X_MCASP0RXINT] = 7,
497 [IRQ_AEMIFINT] = 7,
498 [IRQ_DM646X_RESERVED_3] = 7,
499 [IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */
500 [IRQ_TINT0_TINT34] = 7, /* clocksource */
501 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
502 [IRQ_TINT1_TINT34] = 7, /* system tick */
503 [IRQ_PWMINT0] = 7,
504 [IRQ_PWMINT1] = 7,
505 [IRQ_DM646X_VLQINT] = 7,
506 [IRQ_I2C] = 7,
507 [IRQ_UARTINT0] = 7,
508 [IRQ_UARTINT1] = 7,
509 [IRQ_DM646X_UARTINT2] = 7,
510 [IRQ_DM646X_SPINT0] = 7,
511 [IRQ_DM646X_SPINT1] = 7,
512 [IRQ_DM646X_DSP2ARMINT] = 7,
513 [IRQ_DM646X_RESERVED_4] = 7,
514 [IRQ_DM646X_PSCINT] = 7,
515 [IRQ_DM646X_GPIO0] = 7,
516 [IRQ_DM646X_GPIO1] = 7,
517 [IRQ_DM646X_GPIO2] = 7,
518 [IRQ_DM646X_GPIO3] = 7,
519 [IRQ_DM646X_GPIO4] = 7,
520 [IRQ_DM646X_GPIO5] = 7,
521 [IRQ_DM646X_GPIO6] = 7,
522 [IRQ_DM646X_GPIO7] = 7,
523 [IRQ_DM646X_GPIOBNK0] = 7,
524 [IRQ_DM646X_GPIOBNK1] = 7,
525 [IRQ_DM646X_GPIOBNK2] = 7,
526 [IRQ_DM646X_DDRINT] = 7,
527 [IRQ_DM646X_AEMIFINT] = 7,
528 [IRQ_COMMTX] = 7,
529 [IRQ_COMMRX] = 7,
530 [IRQ_EMUINT] = 7,
531};
532
e38d92fd
KH		 533/*----------------------------------------------------------------------*/
534
60902a2c
SR		 535/* Four Transfer Controllers on DM646x */
536static const s8
537dm646x_queue_tc_mapping[][2] = {
538 /* {event queue no, TC no} */
539 {0, 0},
540 {1, 1},
541 {2, 2},
542 {3, 3},
543 {-1, -1},
544};
545
546static const s8
547dm646x_queue_priority_mapping[][2] = {
548 /* {event queue no, Priority} */
549 {0, 4},
550 {1, 0},
551 {2, 5},
552 {3, 1},
553 {-1, -1},
554};
555
bc3ac9f3
SN		 556static struct edma_soc_info edma_cc0_info = {
557 .n_channel = 64,
558 .n_region = 6, /* 0-1, 4-7 */
559 .n_slot = 512,
560 .n_tc = 4,
561 .n_cc = 1,
562 .queue_tc_mapping = dm646x_queue_tc_mapping,
563 .queue_priority_mapping = dm646x_queue_priority_mapping,
f23fe857 564 .default_queue = EVENTQ_1,
bc3ac9f3
SN		 565};
566
567static struct edma_soc_info *dm646x_edma_info[EDMA_MAX_CC] = {
568 &edma_cc0_info,
e38d92fd
KH		 569};
570
571static struct resource edma_resources[] = {
572 {
60902a2c 573 .name = "edma_cc0",
e38d92fd
KH		 574 .start = 0x01c00000,
575 .end = 0x01c00000 + SZ_64K - 1,
576 .flags = IORESOURCE_MEM,
577 },
578 {
579 .name = "edma_tc0",
580 .start = 0x01c10000,
581 .end = 0x01c10000 + SZ_1K - 1,
582 .flags = IORESOURCE_MEM,
583 },
584 {
585 .name = "edma_tc1",
586 .start = 0x01c10400,
587 .end = 0x01c10400 + SZ_1K - 1,
588 .flags = IORESOURCE_MEM,
589 },
590 {
591 .name = "edma_tc2",
592 .start = 0x01c10800,
593 .end = 0x01c10800 + SZ_1K - 1,
594 .flags = IORESOURCE_MEM,
595 },
596 {
597 .name = "edma_tc3",
598 .start = 0x01c10c00,
599 .end = 0x01c10c00 + SZ_1K - 1,
600 .flags = IORESOURCE_MEM,
601 },
602 {
60902a2c 603 .name = "edma0",
e38d92fd
KH		 604 .start = IRQ_CCINT0,
605 .flags = IORESOURCE_IRQ,
606 },
607 {
60902a2c 608 .name = "edma0_err",
e38d92fd
KH		 609 .start = IRQ_CCERRINT,
610 .flags = IORESOURCE_IRQ,
611 },
612 /* not using TC*_ERR */
613};
614
615static struct platform_device dm646x_edma_device = {
616 .name = "edma",
60902a2c
SR		 617 .id = 0,
618 .dev.platform_data = dm646x_edma_info,
e38d92fd
KH		 619 .num_resources = ARRAY_SIZE(edma_resources),
620 .resource = edma_resources,
621};
622
25acf553
C		 623static struct resource dm646x_mcasp0_resources[] = {
624 {
625 .name = "mcasp0",
626 .start = DAVINCI_DM646X_MCASP0_REG_BASE,
627 .end = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
628 .flags = IORESOURCE_MEM,
629 },
630 /* first TX, then RX */
631 {
632 .start = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
633 .end = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
634 .flags = IORESOURCE_DMA,
635 },
636 {
637 .start = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
638 .end = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
639 .flags = IORESOURCE_DMA,
640 },
641};
642
643static struct resource dm646x_mcasp1_resources[] = {
644 {
645 .name = "mcasp1",
646 .start = DAVINCI_DM646X_MCASP1_REG_BASE,
647 .end = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
648 .flags = IORESOURCE_MEM,
649 },
650 /* DIT mode, only TX event */
651 {
652 .start = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
653 .end = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
654 .flags = IORESOURCE_DMA,
655 },
656 /* DIT mode, dummy entry */
657 {
658 .start = -1,
659 .end = -1,
660 .flags = IORESOURCE_DMA,
661 },
662};
663
664static struct platform_device dm646x_mcasp0_device = {
665 .name = "davinci-mcasp",
666 .id = 0,
667 .num_resources = ARRAY_SIZE(dm646x_mcasp0_resources),
668 .resource = dm646x_mcasp0_resources,
669};
670
671static struct platform_device dm646x_mcasp1_device = {
672 .name = "davinci-mcasp",
673 .id = 1,
674 .num_resources = ARRAY_SIZE(dm646x_mcasp1_resources),
675 .resource = dm646x_mcasp1_resources,
676};
677
678static struct platform_device dm646x_dit_device = {
679 .name = "spdif-dit",
680 .id = -1,
681};
682
85609c1c
MK		 683static u64 vpif_dma_mask = DMA_BIT_MASK(32);
684
685static struct resource vpif_resource[] = {
686 {
687 .start = DAVINCI_VPIF_BASE,
688 .end = DAVINCI_VPIF_BASE + 0x03ff,
689 .flags = IORESOURCE_MEM,
690 }
691};
692
693static struct platform_device vpif_dev = {
694 .name = "vpif",
695 .id = -1,
696 .dev = {
697 .dma_mask = &vpif_dma_mask,
698 .coherent_dma_mask = DMA_BIT_MASK(32),
699 },
700 .resource = vpif_resource,
701 .num_resources = ARRAY_SIZE(vpif_resource),
702};
703
704static struct resource vpif_display_resource[] = {
705 {
706 .start = IRQ_DM646X_VP_VERTINT2,
707 .end = IRQ_DM646X_VP_VERTINT2,
708 .flags = IORESOURCE_IRQ,
709 },
710 {
711 .start = IRQ_DM646X_VP_VERTINT3,
712 .end = IRQ_DM646X_VP_VERTINT3,
713 .flags = IORESOURCE_IRQ,
714 },
715};
716
717static struct platform_device vpif_display_dev = {
718 .name = "vpif_display",
719 .id = -1,
720 .dev = {
721 .dma_mask = &vpif_dma_mask,
722 .coherent_dma_mask = DMA_BIT_MASK(32),
723 },
724 .resource = vpif_display_resource,
725 .num_resources = ARRAY_SIZE(vpif_display_resource),
726};
727
728static struct resource vpif_capture_resource[] = {
729 {
730 .start = IRQ_DM646X_VP_VERTINT0,
731 .end = IRQ_DM646X_VP_VERTINT0,
732 .flags = IORESOURCE_IRQ,
733 },
734 {
735 .start = IRQ_DM646X_VP_VERTINT1,
736 .end = IRQ_DM646X_VP_VERTINT1,
737 .flags = IORESOURCE_IRQ,
738 },
739};
740
741static struct platform_device vpif_capture_dev = {
742 .name = "vpif_capture",
743 .id = -1,
744 .dev = {
745 .dma_mask = &vpif_dma_mask,
746 .coherent_dma_mask = DMA_BIT_MASK(32),
747 },
748 .resource = vpif_capture_resource,
749 .num_resources = ARRAY_SIZE(vpif_capture_resource),
750};
751
e38d92fd
KH		 752/*----------------------------------------------------------------------*/
753
79c3c0b7
MG		 754static struct map_desc dm646x_io_desc[] = {
755 {
756 .virtual = IO_VIRT,
757 .pfn = __phys_to_pfn(IO_PHYS),
758 .length = IO_SIZE,
759 .type = MT_DEVICE
760 },
0d04eb47
DB		 761 {
762 .virtual = SRAM_VIRT,
763 .pfn = __phys_to_pfn(0x00010000),
764 .length = SZ_32K,
2de5c00a 765 .type = MT_MEMORY_NONCACHED,
0d04eb47 766 },
79c3c0b7
MG		 767};
768
b9ab1279
MG		 769/* Contents of JTAG ID register used to identify exact cpu type */
770static struct davinci_id dm646x_ids[] = {
771 {
772 .variant = 0x0,
773 .part_no = 0xb770,
774 .manufacturer = 0x017,
775 .cpu_id = DAVINCI_CPU_ID_DM6467,
f63dd12d
HP		 776 .name = "dm6467_rev1.x",
777 },
778 {
779 .variant = 0x1,
780 .part_no = 0xb770,
781 .manufacturer = 0x017,
782 .cpu_id = DAVINCI_CPU_ID_DM6467,
783 .name = "dm6467_rev3.x",
b9ab1279
MG		 784 },
785};
786
e4c822c7 787static u32 dm646x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
d81d188c 788
f64691b3
MG		 789/*
790 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
791 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
792 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
793 * T1_TOP: Timer 1, top : <unused>
794 */
28552c2e 795static struct davinci_timer_info dm646x_timer_info = {
f64691b3
MG		 796 .timers = davinci_timer_instance,
797 .clockevent_id = T0_BOT,
798 .clocksource_id = T0_TOP,
799};
800
65e866a9
MG		 801static struct plat_serial8250_port dm646x_serial_platform_data[] = {
802 {
803 .mapbase = DAVINCI_UART0_BASE,
804 .irq = IRQ_UARTINT0,
805 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
806 UPF_IOREMAP,
807 .iotype = UPIO_MEM32,
808 .regshift = 2,
809 },
810 {
811 .mapbase = DAVINCI_UART1_BASE,
812 .irq = IRQ_UARTINT1,
813 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
814 UPF_IOREMAP,
815 .iotype = UPIO_MEM32,
816 .regshift = 2,
817 },
818 {
819 .mapbase = DAVINCI_UART2_BASE,
820 .irq = IRQ_DM646X_UARTINT2,
821 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
822 UPF_IOREMAP,
823 .iotype = UPIO_MEM32,
824 .regshift = 2,
825 },
826 {
827 .flags = 0
828 },
829};
830
831static struct platform_device dm646x_serial_device = {
832 .name = "serial8250",
833 .id = PLAT8250_DEV_PLATFORM,
834 .dev = {
835 .platform_data = dm646x_serial_platform_data,
836 },
837};
838
79c3c0b7
MG		 839static struct davinci_soc_info davinci_soc_info_dm646x = {
840 .io_desc = dm646x_io_desc,
841 .io_desc_num = ARRAY_SIZE(dm646x_io_desc),
3347db83 842 .jtag_id_reg = 0x01c40028,
b9ab1279
MG		 843 .ids = dm646x_ids,
844 .ids_num = ARRAY_SIZE(dm646x_ids),
66e0c399 845 .cpu_clks = dm646x_clks,
d81d188c
MG		 846 .psc_bases = dm646x_psc_bases,
847 .psc_bases_num = ARRAY_SIZE(dm646x_psc_bases),
779b0d53 848 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
0e585952
MG		 849 .pinmux_pins = dm646x_pins,
850 .pinmux_pins_num = ARRAY_SIZE(dm646x_pins),
bd808947 851 .intc_base = DAVINCI_ARM_INTC_BASE,
673dd36f
MG		 852 .intc_type = DAVINCI_INTC_TYPE_AINTC,
853 .intc_irq_prios = dm646x_default_priorities,
854 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
f64691b3 855 .timer_info = &dm646x_timer_info,
686b634a 856 .gpio_type = GPIO_TYPE_DAVINCI,
b8d44293 857 .gpio_base = DAVINCI_GPIO_BASE,
a994955c
MG		 858 .gpio_num = 43, /* Only 33 usable */
859 .gpio_irq = IRQ_DM646X_GPIOBNK0,
65e866a9 860 .serial_dev = &dm646x_serial_device,
972412b6 861 .emac_pdata = &dm646x_emac_pdata,
0d04eb47
DB		 862 .sram_dma = 0x10010000,
863 .sram_len = SZ_32K,
79c3c0b7
MG		 864};
865
25acf553
C		 866void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
867{
868 dm646x_mcasp0_device.dev.platform_data = pdata;
869 platform_device_register(&dm646x_mcasp0_device);
870}
871
872void __init dm646x_init_mcasp1(struct snd_platform_data *pdata)
873{
874 dm646x_mcasp1_device.dev.platform_data = pdata;
875 platform_device_register(&dm646x_mcasp1_device);
876 platform_device_register(&dm646x_dit_device);
877}
878
85609c1c
MK		 879void dm646x_setup_vpif(struct vpif_display_config *display_config,
880 struct vpif_capture_config *capture_config)
881{
882 unsigned int value;
883 void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
884
885 value = __raw_readl(base + VSCLKDIS_OFFSET);
886 value &= ~VSCLKDIS_MASK;
887 __raw_writel(value, base + VSCLKDIS_OFFSET);
888
889 value = __raw_readl(base + VDD3P3V_PWDN_OFFSET);
890 value &= ~VDD3P3V_VID_MASK;
891 __raw_writel(value, base + VDD3P3V_PWDN_OFFSET);
892
893 davinci_cfg_reg(DM646X_STSOMUX_DISABLE);
894 davinci_cfg_reg(DM646X_STSIMUX_DISABLE);
895 davinci_cfg_reg(DM646X_PTSOMUX_DISABLE);
896 davinci_cfg_reg(DM646X_PTSIMUX_DISABLE);
897
898 vpif_display_dev.dev.platform_data = display_config;
899 vpif_capture_dev.dev.platform_data = capture_config;
900 platform_device_register(&vpif_dev);
901 platform_device_register(&vpif_display_dev);
902 platform_device_register(&vpif_capture_dev);
903}
904
cce3dddb
RS		 905int __init dm646x_init_edma(struct edma_rsv_info *rsv)
906{
907 edma_cc0_info.rsv = rsv;
908
909 return platform_device_register(&dm646x_edma_device);
910}
911
e38d92fd
KH		 912void __init dm646x_init(void)
913{
79c3c0b7 914 davinci_common_init(&davinci_soc_info_dm646x);
e38d92fd
KH		 915}
916
917static int __init dm646x_init_devices(void)
918{
919 if (!cpu_is_davinci_dm646x())
920 return 0;
921
d22960c8 922 platform_device_register(&dm646x_mdio_device);
972412b6 923 platform_device_register(&dm646x_emac_device);
d22960c8
CC		 924 clk_add_alias(NULL, dev_name(&dm646x_mdio_device.dev),
925 NULL, &dm646x_emac_device.dev);
926
e38d92fd
KH		 927 return 0;
928}
929postcore_initcall(dm646x_init_devices);
Linux kernel - Deliverables
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