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e38d92fd KH |
1 | /* |
2 | * TI DaVinci DM644x chip specific setup | |
3 | * | |
4 | * Author: Kevin Hilman, Deep Root Systems, LLC | |
5 | * | |
6 | * 2007 (c) Deep Root Systems, LLC. This file is licensed under | |
7 | * the terms of the GNU General Public License version 2. This program | |
8 | * is licensed "as is" without any warranty of any kind, whether express | |
9 | * or implied. | |
10 | */ | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/clk.h> | |
65e866a9 | 14 | #include <linux/serial_8250.h> |
e38d92fd | 15 | #include <linux/platform_device.h> |
a994955c | 16 | #include <linux/gpio.h> |
e38d92fd | 17 | |
79c3c0b7 MG |
18 | #include <asm/mach/map.h> |
19 | ||
e38d92fd KH |
20 | #include <mach/dm646x.h> |
21 | #include <mach/clock.h> | |
22 | #include <mach/cputype.h> | |
23 | #include <mach/edma.h> | |
24 | #include <mach/irqs.h> | |
25 | #include <mach/psc.h> | |
26 | #include <mach/mux.h> | |
f64691b3 | 27 | #include <mach/time.h> |
65e866a9 | 28 | #include <mach/serial.h> |
79c3c0b7 | 29 | #include <mach/common.h> |
25acf553 | 30 | #include <mach/asp.h> |
e38d92fd KH |
31 | |
32 | #include "clock.h" | |
33 | #include "mux.h" | |
34 | ||
85609c1c MK |
35 | #define DAVINCI_VPIF_BASE (0x01C12000) |
36 | #define VDD3P3V_PWDN_OFFSET (0x48) | |
37 | #define VSCLKDIS_OFFSET (0x6C) | |
38 | ||
39 | #define VDD3P3V_VID_MASK (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\ | |
40 | BIT_MASK(0)) | |
41 | #define VSCLKDIS_MASK (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\ | |
42 | BIT_MASK(8)) | |
43 | ||
e38d92fd KH |
44 | /* |
45 | * Device specific clocks | |
46 | */ | |
47 | #define DM646X_REF_FREQ 27000000 | |
48 | #define DM646X_AUX_FREQ 24000000 | |
49 | ||
50 | static struct pll_data pll1_data = { | |
51 | .num = 1, | |
52 | .phys_base = DAVINCI_PLL1_BASE, | |
53 | }; | |
54 | ||
55 | static struct pll_data pll2_data = { | |
56 | .num = 2, | |
57 | .phys_base = DAVINCI_PLL2_BASE, | |
58 | }; | |
59 | ||
60 | static struct clk ref_clk = { | |
61 | .name = "ref_clk", | |
62 | .rate = DM646X_REF_FREQ, | |
63 | }; | |
64 | ||
65 | static struct clk aux_clkin = { | |
66 | .name = "aux_clkin", | |
67 | .rate = DM646X_AUX_FREQ, | |
68 | }; | |
69 | ||
70 | static struct clk pll1_clk = { | |
71 | .name = "pll1", | |
72 | .parent = &ref_clk, | |
73 | .pll_data = &pll1_data, | |
74 | .flags = CLK_PLL, | |
75 | }; | |
76 | ||
77 | static struct clk pll1_sysclk1 = { | |
78 | .name = "pll1_sysclk1", | |
79 | .parent = &pll1_clk, | |
80 | .flags = CLK_PLL, | |
81 | .div_reg = PLLDIV1, | |
82 | }; | |
83 | ||
84 | static struct clk pll1_sysclk2 = { | |
85 | .name = "pll1_sysclk2", | |
86 | .parent = &pll1_clk, | |
87 | .flags = CLK_PLL, | |
88 | .div_reg = PLLDIV2, | |
89 | }; | |
90 | ||
91 | static struct clk pll1_sysclk3 = { | |
92 | .name = "pll1_sysclk3", | |
93 | .parent = &pll1_clk, | |
94 | .flags = CLK_PLL, | |
95 | .div_reg = PLLDIV3, | |
96 | }; | |
97 | ||
98 | static struct clk pll1_sysclk4 = { | |
99 | .name = "pll1_sysclk4", | |
100 | .parent = &pll1_clk, | |
101 | .flags = CLK_PLL, | |
102 | .div_reg = PLLDIV4, | |
103 | }; | |
104 | ||
105 | static struct clk pll1_sysclk5 = { | |
106 | .name = "pll1_sysclk5", | |
107 | .parent = &pll1_clk, | |
108 | .flags = CLK_PLL, | |
109 | .div_reg = PLLDIV5, | |
110 | }; | |
111 | ||
112 | static struct clk pll1_sysclk6 = { | |
113 | .name = "pll1_sysclk6", | |
114 | .parent = &pll1_clk, | |
115 | .flags = CLK_PLL, | |
116 | .div_reg = PLLDIV6, | |
117 | }; | |
118 | ||
119 | static struct clk pll1_sysclk8 = { | |
120 | .name = "pll1_sysclk8", | |
121 | .parent = &pll1_clk, | |
122 | .flags = CLK_PLL, | |
123 | .div_reg = PLLDIV8, | |
124 | }; | |
125 | ||
126 | static struct clk pll1_sysclk9 = { | |
127 | .name = "pll1_sysclk9", | |
128 | .parent = &pll1_clk, | |
129 | .flags = CLK_PLL, | |
130 | .div_reg = PLLDIV9, | |
131 | }; | |
132 | ||
133 | static struct clk pll1_sysclkbp = { | |
134 | .name = "pll1_sysclkbp", | |
135 | .parent = &pll1_clk, | |
136 | .flags = CLK_PLL | PRE_PLL, | |
137 | .div_reg = BPDIV, | |
138 | }; | |
139 | ||
140 | static struct clk pll1_aux_clk = { | |
141 | .name = "pll1_aux_clk", | |
142 | .parent = &pll1_clk, | |
143 | .flags = CLK_PLL | PRE_PLL, | |
144 | }; | |
145 | ||
146 | static struct clk pll2_clk = { | |
147 | .name = "pll2_clk", | |
148 | .parent = &ref_clk, | |
149 | .pll_data = &pll2_data, | |
150 | .flags = CLK_PLL, | |
151 | }; | |
152 | ||
153 | static struct clk pll2_sysclk1 = { | |
154 | .name = "pll2_sysclk1", | |
155 | .parent = &pll2_clk, | |
156 | .flags = CLK_PLL, | |
157 | .div_reg = PLLDIV1, | |
158 | }; | |
159 | ||
160 | static struct clk dsp_clk = { | |
161 | .name = "dsp", | |
162 | .parent = &pll1_sysclk1, | |
163 | .lpsc = DM646X_LPSC_C64X_CPU, | |
164 | .flags = PSC_DSP, | |
165 | .usecount = 1, /* REVISIT how to disable? */ | |
166 | }; | |
167 | ||
168 | static struct clk arm_clk = { | |
169 | .name = "arm", | |
170 | .parent = &pll1_sysclk2, | |
171 | .lpsc = DM646X_LPSC_ARM, | |
172 | .flags = ALWAYS_ENABLED, | |
173 | }; | |
174 | ||
2bcb613a SR |
175 | static struct clk edma_cc_clk = { |
176 | .name = "edma_cc", | |
177 | .parent = &pll1_sysclk2, | |
178 | .lpsc = DM646X_LPSC_TPCC, | |
179 | .flags = ALWAYS_ENABLED, | |
180 | }; | |
181 | ||
182 | static struct clk edma_tc0_clk = { | |
183 | .name = "edma_tc0", | |
184 | .parent = &pll1_sysclk2, | |
185 | .lpsc = DM646X_LPSC_TPTC0, | |
186 | .flags = ALWAYS_ENABLED, | |
187 | }; | |
188 | ||
189 | static struct clk edma_tc1_clk = { | |
190 | .name = "edma_tc1", | |
191 | .parent = &pll1_sysclk2, | |
192 | .lpsc = DM646X_LPSC_TPTC1, | |
193 | .flags = ALWAYS_ENABLED, | |
194 | }; | |
195 | ||
196 | static struct clk edma_tc2_clk = { | |
197 | .name = "edma_tc2", | |
198 | .parent = &pll1_sysclk2, | |
199 | .lpsc = DM646X_LPSC_TPTC2, | |
200 | .flags = ALWAYS_ENABLED, | |
201 | }; | |
202 | ||
203 | static struct clk edma_tc3_clk = { | |
204 | .name = "edma_tc3", | |
205 | .parent = &pll1_sysclk2, | |
206 | .lpsc = DM646X_LPSC_TPTC3, | |
207 | .flags = ALWAYS_ENABLED, | |
208 | }; | |
209 | ||
e38d92fd KH |
210 | static struct clk uart0_clk = { |
211 | .name = "uart0", | |
212 | .parent = &aux_clkin, | |
213 | .lpsc = DM646X_LPSC_UART0, | |
214 | }; | |
215 | ||
216 | static struct clk uart1_clk = { | |
217 | .name = "uart1", | |
218 | .parent = &aux_clkin, | |
219 | .lpsc = DM646X_LPSC_UART1, | |
220 | }; | |
221 | ||
222 | static struct clk uart2_clk = { | |
223 | .name = "uart2", | |
224 | .parent = &aux_clkin, | |
225 | .lpsc = DM646X_LPSC_UART2, | |
226 | }; | |
227 | ||
228 | static struct clk i2c_clk = { | |
229 | .name = "I2CCLK", | |
230 | .parent = &pll1_sysclk3, | |
231 | .lpsc = DM646X_LPSC_I2C, | |
232 | }; | |
233 | ||
234 | static struct clk gpio_clk = { | |
235 | .name = "gpio", | |
236 | .parent = &pll1_sysclk3, | |
237 | .lpsc = DM646X_LPSC_GPIO, | |
238 | }; | |
239 | ||
75d0fa70 C |
240 | static struct clk mcasp0_clk = { |
241 | .name = "mcasp0", | |
242 | .parent = &pll1_sysclk3, | |
243 | .lpsc = DM646X_LPSC_McASP0, | |
244 | }; | |
245 | ||
246 | static struct clk mcasp1_clk = { | |
247 | .name = "mcasp1", | |
248 | .parent = &pll1_sysclk3, | |
249 | .lpsc = DM646X_LPSC_McASP1, | |
250 | }; | |
251 | ||
e38d92fd KH |
252 | static struct clk aemif_clk = { |
253 | .name = "aemif", | |
254 | .parent = &pll1_sysclk3, | |
255 | .lpsc = DM646X_LPSC_AEMIF, | |
256 | .flags = ALWAYS_ENABLED, | |
257 | }; | |
258 | ||
259 | static struct clk emac_clk = { | |
260 | .name = "emac", | |
261 | .parent = &pll1_sysclk3, | |
262 | .lpsc = DM646X_LPSC_EMAC, | |
263 | }; | |
264 | ||
265 | static struct clk pwm0_clk = { | |
266 | .name = "pwm0", | |
267 | .parent = &pll1_sysclk3, | |
268 | .lpsc = DM646X_LPSC_PWM0, | |
269 | .usecount = 1, /* REVIST: disabling hangs system */ | |
270 | }; | |
271 | ||
272 | static struct clk pwm1_clk = { | |
273 | .name = "pwm1", | |
274 | .parent = &pll1_sysclk3, | |
275 | .lpsc = DM646X_LPSC_PWM1, | |
276 | .usecount = 1, /* REVIST: disabling hangs system */ | |
277 | }; | |
278 | ||
279 | static struct clk timer0_clk = { | |
280 | .name = "timer0", | |
281 | .parent = &pll1_sysclk3, | |
282 | .lpsc = DM646X_LPSC_TIMER0, | |
283 | }; | |
284 | ||
285 | static struct clk timer1_clk = { | |
286 | .name = "timer1", | |
287 | .parent = &pll1_sysclk3, | |
288 | .lpsc = DM646X_LPSC_TIMER1, | |
289 | }; | |
290 | ||
291 | static struct clk timer2_clk = { | |
292 | .name = "timer2", | |
293 | .parent = &pll1_sysclk3, | |
294 | .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */ | |
295 | }; | |
296 | ||
3e25d5f4 HP |
297 | |
298 | static struct clk ide_clk = { | |
299 | .name = "ide", | |
300 | .parent = &pll1_sysclk4, | |
301 | .lpsc = DAVINCI_LPSC_ATA, | |
302 | }; | |
303 | ||
e38d92fd KH |
304 | static struct clk vpif0_clk = { |
305 | .name = "vpif0", | |
306 | .parent = &ref_clk, | |
307 | .lpsc = DM646X_LPSC_VPSSMSTR, | |
308 | .flags = ALWAYS_ENABLED, | |
309 | }; | |
310 | ||
311 | static struct clk vpif1_clk = { | |
312 | .name = "vpif1", | |
313 | .parent = &ref_clk, | |
314 | .lpsc = DM646X_LPSC_VPSSSLV, | |
315 | .flags = ALWAYS_ENABLED, | |
316 | }; | |
317 | ||
318 | struct davinci_clk dm646x_clks[] = { | |
319 | CLK(NULL, "ref", &ref_clk), | |
320 | CLK(NULL, "aux", &aux_clkin), | |
321 | CLK(NULL, "pll1", &pll1_clk), | |
322 | CLK(NULL, "pll1_sysclk", &pll1_sysclk1), | |
323 | CLK(NULL, "pll1_sysclk", &pll1_sysclk2), | |
324 | CLK(NULL, "pll1_sysclk", &pll1_sysclk3), | |
325 | CLK(NULL, "pll1_sysclk", &pll1_sysclk4), | |
326 | CLK(NULL, "pll1_sysclk", &pll1_sysclk5), | |
327 | CLK(NULL, "pll1_sysclk", &pll1_sysclk6), | |
328 | CLK(NULL, "pll1_sysclk", &pll1_sysclk8), | |
329 | CLK(NULL, "pll1_sysclk", &pll1_sysclk9), | |
330 | CLK(NULL, "pll1_sysclk", &pll1_sysclkbp), | |
331 | CLK(NULL, "pll1_aux", &pll1_aux_clk), | |
332 | CLK(NULL, "pll2", &pll2_clk), | |
333 | CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), | |
334 | CLK(NULL, "dsp", &dsp_clk), | |
335 | CLK(NULL, "arm", &arm_clk), | |
2bcb613a SR |
336 | CLK(NULL, "edma_cc", &edma_cc_clk), |
337 | CLK(NULL, "edma_tc0", &edma_tc0_clk), | |
338 | CLK(NULL, "edma_tc1", &edma_tc1_clk), | |
339 | CLK(NULL, "edma_tc2", &edma_tc2_clk), | |
340 | CLK(NULL, "edma_tc3", &edma_tc3_clk), | |
e38d92fd KH |
341 | CLK(NULL, "uart0", &uart0_clk), |
342 | CLK(NULL, "uart1", &uart1_clk), | |
343 | CLK(NULL, "uart2", &uart2_clk), | |
344 | CLK("i2c_davinci.1", NULL, &i2c_clk), | |
345 | CLK(NULL, "gpio", &gpio_clk), | |
61aa0732 KH |
346 | CLK("davinci-mcasp.0", NULL, &mcasp0_clk), |
347 | CLK("davinci-mcasp.1", NULL, &mcasp1_clk), | |
e38d92fd KH |
348 | CLK(NULL, "aemif", &aemif_clk), |
349 | CLK("davinci_emac.1", NULL, &emac_clk), | |
350 | CLK(NULL, "pwm0", &pwm0_clk), | |
351 | CLK(NULL, "pwm1", &pwm1_clk), | |
352 | CLK(NULL, "timer0", &timer0_clk), | |
353 | CLK(NULL, "timer1", &timer1_clk), | |
354 | CLK("watchdog", NULL, &timer2_clk), | |
3e25d5f4 | 355 | CLK("palm_bk3710", NULL, &ide_clk), |
e38d92fd KH |
356 | CLK(NULL, "vpif0", &vpif0_clk), |
357 | CLK(NULL, "vpif1", &vpif1_clk), | |
358 | CLK(NULL, NULL, NULL), | |
359 | }; | |
360 | ||
972412b6 MG |
361 | static struct emac_platform_data dm646x_emac_pdata = { |
362 | .ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET, | |
363 | .ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET, | |
364 | .ctrl_ram_offset = DM646X_EMAC_CNTRL_RAM_OFFSET, | |
365 | .mdio_reg_offset = DM646X_EMAC_MDIO_OFFSET, | |
366 | .ctrl_ram_size = DM646X_EMAC_CNTRL_RAM_SIZE, | |
367 | .version = EMAC_VERSION_2, | |
368 | }; | |
369 | ||
ac7b75b5 KH |
370 | static struct resource dm646x_emac_resources[] = { |
371 | { | |
372 | .start = DM646X_EMAC_BASE, | |
373 | .end = DM646X_EMAC_BASE + 0x47ff, | |
374 | .flags = IORESOURCE_MEM, | |
375 | }, | |
376 | { | |
377 | .start = IRQ_DM646X_EMACRXTHINT, | |
378 | .end = IRQ_DM646X_EMACRXTHINT, | |
379 | .flags = IORESOURCE_IRQ, | |
380 | }, | |
381 | { | |
382 | .start = IRQ_DM646X_EMACRXINT, | |
383 | .end = IRQ_DM646X_EMACRXINT, | |
384 | .flags = IORESOURCE_IRQ, | |
385 | }, | |
386 | { | |
387 | .start = IRQ_DM646X_EMACTXINT, | |
388 | .end = IRQ_DM646X_EMACTXINT, | |
389 | .flags = IORESOURCE_IRQ, | |
390 | }, | |
391 | { | |
392 | .start = IRQ_DM646X_EMACMISCINT, | |
393 | .end = IRQ_DM646X_EMACMISCINT, | |
394 | .flags = IORESOURCE_IRQ, | |
395 | }, | |
396 | }; | |
397 | ||
398 | static struct platform_device dm646x_emac_device = { | |
399 | .name = "davinci_emac", | |
400 | .id = 1, | |
972412b6 MG |
401 | .dev = { |
402 | .platform_data = &dm646x_emac_pdata, | |
403 | }, | |
ac7b75b5 KH |
404 | .num_resources = ARRAY_SIZE(dm646x_emac_resources), |
405 | .resource = dm646x_emac_resources, | |
406 | }; | |
407 | ||
5570078c MG |
408 | #define PINMUX0 0x00 |
409 | #define PINMUX1 0x04 | |
410 | ||
e38d92fd KH |
411 | /* |
412 | * Device specific mux setup | |
413 | * | |
414 | * soc description mux mode mode mux dbg | |
415 | * reg offset mask mode | |
416 | */ | |
417 | static const struct mux_config dm646x_pins[] = { | |
0e585952 | 418 | #ifdef CONFIG_DAVINCI_MUX |
3e25d5f4 | 419 | MUX_CFG(DM646X, ATAEN, 0, 0, 5, 1, true) |
e38d92fd KH |
420 | |
421 | MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false) | |
422 | ||
423 | MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false) | |
424 | ||
425 | MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true) | |
426 | ||
427 | MUX_CFG(DM646X, STSOMUX_DISABLE, 0, 22, 3, 0, true) | |
428 | ||
429 | MUX_CFG(DM646X, STSIMUX_DISABLE, 0, 20, 3, 0, true) | |
430 | ||
431 | MUX_CFG(DM646X, PTSOMUX_DISABLE, 0, 18, 3, 0, true) | |
432 | ||
433 | MUX_CFG(DM646X, PTSIMUX_DISABLE, 0, 16, 3, 0, true) | |
434 | ||
435 | MUX_CFG(DM646X, STSOMUX, 0, 22, 3, 2, true) | |
436 | ||
437 | MUX_CFG(DM646X, STSIMUX, 0, 20, 3, 2, true) | |
438 | ||
439 | MUX_CFG(DM646X, PTSOMUX_PARALLEL, 0, 18, 3, 2, true) | |
440 | ||
441 | MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true) | |
442 | ||
443 | MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true) | |
444 | ||
445 | MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true) | |
0e585952 | 446 | #endif |
e38d92fd KH |
447 | }; |
448 | ||
673dd36f MG |
449 | static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = { |
450 | [IRQ_DM646X_VP_VERTINT0] = 7, | |
451 | [IRQ_DM646X_VP_VERTINT1] = 7, | |
452 | [IRQ_DM646X_VP_VERTINT2] = 7, | |
453 | [IRQ_DM646X_VP_VERTINT3] = 7, | |
454 | [IRQ_DM646X_VP_ERRINT] = 7, | |
455 | [IRQ_DM646X_RESERVED_1] = 7, | |
456 | [IRQ_DM646X_RESERVED_2] = 7, | |
457 | [IRQ_DM646X_WDINT] = 7, | |
458 | [IRQ_DM646X_CRGENINT0] = 7, | |
459 | [IRQ_DM646X_CRGENINT1] = 7, | |
460 | [IRQ_DM646X_TSIFINT0] = 7, | |
461 | [IRQ_DM646X_TSIFINT1] = 7, | |
462 | [IRQ_DM646X_VDCEINT] = 7, | |
463 | [IRQ_DM646X_USBINT] = 7, | |
464 | [IRQ_DM646X_USBDMAINT] = 7, | |
465 | [IRQ_DM646X_PCIINT] = 7, | |
466 | [IRQ_CCINT0] = 7, /* dma */ | |
467 | [IRQ_CCERRINT] = 7, /* dma */ | |
468 | [IRQ_TCERRINT0] = 7, /* dma */ | |
469 | [IRQ_TCERRINT] = 7, /* dma */ | |
470 | [IRQ_DM646X_TCERRINT2] = 7, | |
471 | [IRQ_DM646X_TCERRINT3] = 7, | |
472 | [IRQ_DM646X_IDE] = 7, | |
473 | [IRQ_DM646X_HPIINT] = 7, | |
474 | [IRQ_DM646X_EMACRXTHINT] = 7, | |
475 | [IRQ_DM646X_EMACRXINT] = 7, | |
476 | [IRQ_DM646X_EMACTXINT] = 7, | |
477 | [IRQ_DM646X_EMACMISCINT] = 7, | |
478 | [IRQ_DM646X_MCASP0TXINT] = 7, | |
479 | [IRQ_DM646X_MCASP0RXINT] = 7, | |
480 | [IRQ_AEMIFINT] = 7, | |
481 | [IRQ_DM646X_RESERVED_3] = 7, | |
482 | [IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */ | |
483 | [IRQ_TINT0_TINT34] = 7, /* clocksource */ | |
484 | [IRQ_TINT1_TINT12] = 7, /* DSP timer */ | |
485 | [IRQ_TINT1_TINT34] = 7, /* system tick */ | |
486 | [IRQ_PWMINT0] = 7, | |
487 | [IRQ_PWMINT1] = 7, | |
488 | [IRQ_DM646X_VLQINT] = 7, | |
489 | [IRQ_I2C] = 7, | |
490 | [IRQ_UARTINT0] = 7, | |
491 | [IRQ_UARTINT1] = 7, | |
492 | [IRQ_DM646X_UARTINT2] = 7, | |
493 | [IRQ_DM646X_SPINT0] = 7, | |
494 | [IRQ_DM646X_SPINT1] = 7, | |
495 | [IRQ_DM646X_DSP2ARMINT] = 7, | |
496 | [IRQ_DM646X_RESERVED_4] = 7, | |
497 | [IRQ_DM646X_PSCINT] = 7, | |
498 | [IRQ_DM646X_GPIO0] = 7, | |
499 | [IRQ_DM646X_GPIO1] = 7, | |
500 | [IRQ_DM646X_GPIO2] = 7, | |
501 | [IRQ_DM646X_GPIO3] = 7, | |
502 | [IRQ_DM646X_GPIO4] = 7, | |
503 | [IRQ_DM646X_GPIO5] = 7, | |
504 | [IRQ_DM646X_GPIO6] = 7, | |
505 | [IRQ_DM646X_GPIO7] = 7, | |
506 | [IRQ_DM646X_GPIOBNK0] = 7, | |
507 | [IRQ_DM646X_GPIOBNK1] = 7, | |
508 | [IRQ_DM646X_GPIOBNK2] = 7, | |
509 | [IRQ_DM646X_DDRINT] = 7, | |
510 | [IRQ_DM646X_AEMIFINT] = 7, | |
511 | [IRQ_COMMTX] = 7, | |
512 | [IRQ_COMMRX] = 7, | |
513 | [IRQ_EMUINT] = 7, | |
514 | }; | |
515 | ||
e38d92fd KH |
516 | /*----------------------------------------------------------------------*/ |
517 | ||
518 | static const s8 dma_chan_dm646x_no_event[] = { | |
519 | 0, 1, 2, 3, 13, | |
520 | 14, 15, 24, 25, 26, | |
521 | 27, 30, 31, 54, 55, | |
522 | 56, | |
523 | -1 | |
524 | }; | |
525 | ||
60902a2c SR |
526 | /* Four Transfer Controllers on DM646x */ |
527 | static const s8 | |
528 | dm646x_queue_tc_mapping[][2] = { | |
529 | /* {event queue no, TC no} */ | |
530 | {0, 0}, | |
531 | {1, 1}, | |
532 | {2, 2}, | |
533 | {3, 3}, | |
534 | {-1, -1}, | |
535 | }; | |
536 | ||
537 | static const s8 | |
538 | dm646x_queue_priority_mapping[][2] = { | |
539 | /* {event queue no, Priority} */ | |
540 | {0, 4}, | |
541 | {1, 0}, | |
542 | {2, 5}, | |
543 | {3, 1}, | |
544 | {-1, -1}, | |
545 | }; | |
546 | ||
547 | static struct edma_soc_info dm646x_edma_info[] = { | |
548 | { | |
549 | .n_channel = 64, | |
550 | .n_region = 6, /* 0-1, 4-7 */ | |
551 | .n_slot = 512, | |
552 | .n_tc = 4, | |
553 | .n_cc = 1, | |
554 | .noevent = dma_chan_dm646x_no_event, | |
555 | .queue_tc_mapping = dm646x_queue_tc_mapping, | |
556 | .queue_priority_mapping = dm646x_queue_priority_mapping, | |
557 | }, | |
e38d92fd KH |
558 | }; |
559 | ||
560 | static struct resource edma_resources[] = { | |
561 | { | |
60902a2c | 562 | .name = "edma_cc0", |
e38d92fd KH |
563 | .start = 0x01c00000, |
564 | .end = 0x01c00000 + SZ_64K - 1, | |
565 | .flags = IORESOURCE_MEM, | |
566 | }, | |
567 | { | |
568 | .name = "edma_tc0", | |
569 | .start = 0x01c10000, | |
570 | .end = 0x01c10000 + SZ_1K - 1, | |
571 | .flags = IORESOURCE_MEM, | |
572 | }, | |
573 | { | |
574 | .name = "edma_tc1", | |
575 | .start = 0x01c10400, | |
576 | .end = 0x01c10400 + SZ_1K - 1, | |
577 | .flags = IORESOURCE_MEM, | |
578 | }, | |
579 | { | |
580 | .name = "edma_tc2", | |
581 | .start = 0x01c10800, | |
582 | .end = 0x01c10800 + SZ_1K - 1, | |
583 | .flags = IORESOURCE_MEM, | |
584 | }, | |
585 | { | |
586 | .name = "edma_tc3", | |
587 | .start = 0x01c10c00, | |
588 | .end = 0x01c10c00 + SZ_1K - 1, | |
589 | .flags = IORESOURCE_MEM, | |
590 | }, | |
591 | { | |
60902a2c | 592 | .name = "edma0", |
e38d92fd KH |
593 | .start = IRQ_CCINT0, |
594 | .flags = IORESOURCE_IRQ, | |
595 | }, | |
596 | { | |
60902a2c | 597 | .name = "edma0_err", |
e38d92fd KH |
598 | .start = IRQ_CCERRINT, |
599 | .flags = IORESOURCE_IRQ, | |
600 | }, | |
601 | /* not using TC*_ERR */ | |
602 | }; | |
603 | ||
604 | static struct platform_device dm646x_edma_device = { | |
605 | .name = "edma", | |
60902a2c SR |
606 | .id = 0, |
607 | .dev.platform_data = dm646x_edma_info, | |
e38d92fd KH |
608 | .num_resources = ARRAY_SIZE(edma_resources), |
609 | .resource = edma_resources, | |
610 | }; | |
611 | ||
1c92a554 HP |
612 | static struct resource ide_resources[] = { |
613 | { | |
614 | .start = DM646X_ATA_REG_BASE, | |
615 | .end = DM646X_ATA_REG_BASE + 0x7ff, | |
616 | .flags = IORESOURCE_MEM, | |
617 | }, | |
618 | { | |
619 | .start = IRQ_DM646X_IDE, | |
620 | .end = IRQ_DM646X_IDE, | |
621 | .flags = IORESOURCE_IRQ, | |
622 | }, | |
623 | }; | |
624 | ||
625 | static u64 ide_dma_mask = DMA_BIT_MASK(32); | |
626 | ||
627 | static struct platform_device ide_dev = { | |
628 | .name = "palm_bk3710", | |
629 | .id = -1, | |
630 | .resource = ide_resources, | |
631 | .num_resources = ARRAY_SIZE(ide_resources), | |
632 | .dev = { | |
633 | .dma_mask = &ide_dma_mask, | |
634 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
635 | }, | |
636 | }; | |
637 | ||
25acf553 C |
638 | static struct resource dm646x_mcasp0_resources[] = { |
639 | { | |
640 | .name = "mcasp0", | |
641 | .start = DAVINCI_DM646X_MCASP0_REG_BASE, | |
642 | .end = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1, | |
643 | .flags = IORESOURCE_MEM, | |
644 | }, | |
645 | /* first TX, then RX */ | |
646 | { | |
647 | .start = DAVINCI_DM646X_DMA_MCASP0_AXEVT0, | |
648 | .end = DAVINCI_DM646X_DMA_MCASP0_AXEVT0, | |
649 | .flags = IORESOURCE_DMA, | |
650 | }, | |
651 | { | |
652 | .start = DAVINCI_DM646X_DMA_MCASP0_AREVT0, | |
653 | .end = DAVINCI_DM646X_DMA_MCASP0_AREVT0, | |
654 | .flags = IORESOURCE_DMA, | |
655 | }, | |
656 | }; | |
657 | ||
658 | static struct resource dm646x_mcasp1_resources[] = { | |
659 | { | |
660 | .name = "mcasp1", | |
661 | .start = DAVINCI_DM646X_MCASP1_REG_BASE, | |
662 | .end = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1, | |
663 | .flags = IORESOURCE_MEM, | |
664 | }, | |
665 | /* DIT mode, only TX event */ | |
666 | { | |
667 | .start = DAVINCI_DM646X_DMA_MCASP1_AXEVT1, | |
668 | .end = DAVINCI_DM646X_DMA_MCASP1_AXEVT1, | |
669 | .flags = IORESOURCE_DMA, | |
670 | }, | |
671 | /* DIT mode, dummy entry */ | |
672 | { | |
673 | .start = -1, | |
674 | .end = -1, | |
675 | .flags = IORESOURCE_DMA, | |
676 | }, | |
677 | }; | |
678 | ||
679 | static struct platform_device dm646x_mcasp0_device = { | |
680 | .name = "davinci-mcasp", | |
681 | .id = 0, | |
682 | .num_resources = ARRAY_SIZE(dm646x_mcasp0_resources), | |
683 | .resource = dm646x_mcasp0_resources, | |
684 | }; | |
685 | ||
686 | static struct platform_device dm646x_mcasp1_device = { | |
687 | .name = "davinci-mcasp", | |
688 | .id = 1, | |
689 | .num_resources = ARRAY_SIZE(dm646x_mcasp1_resources), | |
690 | .resource = dm646x_mcasp1_resources, | |
691 | }; | |
692 | ||
693 | static struct platform_device dm646x_dit_device = { | |
694 | .name = "spdif-dit", | |
695 | .id = -1, | |
696 | }; | |
697 | ||
85609c1c MK |
698 | static u64 vpif_dma_mask = DMA_BIT_MASK(32); |
699 | ||
700 | static struct resource vpif_resource[] = { | |
701 | { | |
702 | .start = DAVINCI_VPIF_BASE, | |
703 | .end = DAVINCI_VPIF_BASE + 0x03ff, | |
704 | .flags = IORESOURCE_MEM, | |
705 | } | |
706 | }; | |
707 | ||
708 | static struct platform_device vpif_dev = { | |
709 | .name = "vpif", | |
710 | .id = -1, | |
711 | .dev = { | |
712 | .dma_mask = &vpif_dma_mask, | |
713 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
714 | }, | |
715 | .resource = vpif_resource, | |
716 | .num_resources = ARRAY_SIZE(vpif_resource), | |
717 | }; | |
718 | ||
719 | static struct resource vpif_display_resource[] = { | |
720 | { | |
721 | .start = IRQ_DM646X_VP_VERTINT2, | |
722 | .end = IRQ_DM646X_VP_VERTINT2, | |
723 | .flags = IORESOURCE_IRQ, | |
724 | }, | |
725 | { | |
726 | .start = IRQ_DM646X_VP_VERTINT3, | |
727 | .end = IRQ_DM646X_VP_VERTINT3, | |
728 | .flags = IORESOURCE_IRQ, | |
729 | }, | |
730 | }; | |
731 | ||
732 | static struct platform_device vpif_display_dev = { | |
733 | .name = "vpif_display", | |
734 | .id = -1, | |
735 | .dev = { | |
736 | .dma_mask = &vpif_dma_mask, | |
737 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
738 | }, | |
739 | .resource = vpif_display_resource, | |
740 | .num_resources = ARRAY_SIZE(vpif_display_resource), | |
741 | }; | |
742 | ||
743 | static struct resource vpif_capture_resource[] = { | |
744 | { | |
745 | .start = IRQ_DM646X_VP_VERTINT0, | |
746 | .end = IRQ_DM646X_VP_VERTINT0, | |
747 | .flags = IORESOURCE_IRQ, | |
748 | }, | |
749 | { | |
750 | .start = IRQ_DM646X_VP_VERTINT1, | |
751 | .end = IRQ_DM646X_VP_VERTINT1, | |
752 | .flags = IORESOURCE_IRQ, | |
753 | }, | |
754 | }; | |
755 | ||
756 | static struct platform_device vpif_capture_dev = { | |
757 | .name = "vpif_capture", | |
758 | .id = -1, | |
759 | .dev = { | |
760 | .dma_mask = &vpif_dma_mask, | |
761 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
762 | }, | |
763 | .resource = vpif_capture_resource, | |
764 | .num_resources = ARRAY_SIZE(vpif_capture_resource), | |
765 | }; | |
766 | ||
e38d92fd KH |
767 | /*----------------------------------------------------------------------*/ |
768 | ||
79c3c0b7 MG |
769 | static struct map_desc dm646x_io_desc[] = { |
770 | { | |
771 | .virtual = IO_VIRT, | |
772 | .pfn = __phys_to_pfn(IO_PHYS), | |
773 | .length = IO_SIZE, | |
774 | .type = MT_DEVICE | |
775 | }, | |
0d04eb47 DB |
776 | { |
777 | .virtual = SRAM_VIRT, | |
778 | .pfn = __phys_to_pfn(0x00010000), | |
779 | .length = SZ_32K, | |
780 | /* MT_MEMORY_NONCACHED requires supersection alignment */ | |
781 | .type = MT_DEVICE, | |
782 | }, | |
79c3c0b7 MG |
783 | }; |
784 | ||
b9ab1279 MG |
785 | /* Contents of JTAG ID register used to identify exact cpu type */ |
786 | static struct davinci_id dm646x_ids[] = { | |
787 | { | |
788 | .variant = 0x0, | |
789 | .part_no = 0xb770, | |
790 | .manufacturer = 0x017, | |
791 | .cpu_id = DAVINCI_CPU_ID_DM6467, | |
792 | .name = "dm6467", | |
793 | }, | |
794 | }; | |
795 | ||
d81d188c MG |
796 | static void __iomem *dm646x_psc_bases[] = { |
797 | IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE), | |
798 | }; | |
799 | ||
f64691b3 MG |
800 | /* |
801 | * T0_BOT: Timer 0, bottom: clockevent source for hrtimers | |
802 | * T0_TOP: Timer 0, top : clocksource for generic timekeeping | |
803 | * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code) | |
804 | * T1_TOP: Timer 1, top : <unused> | |
805 | */ | |
806 | struct davinci_timer_info dm646x_timer_info = { | |
807 | .timers = davinci_timer_instance, | |
808 | .clockevent_id = T0_BOT, | |
809 | .clocksource_id = T0_TOP, | |
810 | }; | |
811 | ||
65e866a9 MG |
812 | static struct plat_serial8250_port dm646x_serial_platform_data[] = { |
813 | { | |
814 | .mapbase = DAVINCI_UART0_BASE, | |
815 | .irq = IRQ_UARTINT0, | |
816 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | |
817 | UPF_IOREMAP, | |
818 | .iotype = UPIO_MEM32, | |
819 | .regshift = 2, | |
820 | }, | |
821 | { | |
822 | .mapbase = DAVINCI_UART1_BASE, | |
823 | .irq = IRQ_UARTINT1, | |
824 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | |
825 | UPF_IOREMAP, | |
826 | .iotype = UPIO_MEM32, | |
827 | .regshift = 2, | |
828 | }, | |
829 | { | |
830 | .mapbase = DAVINCI_UART2_BASE, | |
831 | .irq = IRQ_DM646X_UARTINT2, | |
832 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | |
833 | UPF_IOREMAP, | |
834 | .iotype = UPIO_MEM32, | |
835 | .regshift = 2, | |
836 | }, | |
837 | { | |
838 | .flags = 0 | |
839 | }, | |
840 | }; | |
841 | ||
842 | static struct platform_device dm646x_serial_device = { | |
843 | .name = "serial8250", | |
844 | .id = PLAT8250_DEV_PLATFORM, | |
845 | .dev = { | |
846 | .platform_data = dm646x_serial_platform_data, | |
847 | }, | |
848 | }; | |
849 | ||
79c3c0b7 MG |
850 | static struct davinci_soc_info davinci_soc_info_dm646x = { |
851 | .io_desc = dm646x_io_desc, | |
852 | .io_desc_num = ARRAY_SIZE(dm646x_io_desc), | |
b9ab1279 MG |
853 | .jtag_id_base = IO_ADDRESS(0x01c40028), |
854 | .ids = dm646x_ids, | |
855 | .ids_num = ARRAY_SIZE(dm646x_ids), | |
66e0c399 | 856 | .cpu_clks = dm646x_clks, |
d81d188c MG |
857 | .psc_bases = dm646x_psc_bases, |
858 | .psc_bases_num = ARRAY_SIZE(dm646x_psc_bases), | |
0e585952 MG |
859 | .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE), |
860 | .pinmux_pins = dm646x_pins, | |
861 | .pinmux_pins_num = ARRAY_SIZE(dm646x_pins), | |
673dd36f MG |
862 | .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE), |
863 | .intc_type = DAVINCI_INTC_TYPE_AINTC, | |
864 | .intc_irq_prios = dm646x_default_priorities, | |
865 | .intc_irq_num = DAVINCI_N_AINTC_IRQ, | |
f64691b3 | 866 | .timer_info = &dm646x_timer_info, |
a994955c MG |
867 | .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE), |
868 | .gpio_num = 43, /* Only 33 usable */ | |
869 | .gpio_irq = IRQ_DM646X_GPIOBNK0, | |
65e866a9 | 870 | .serial_dev = &dm646x_serial_device, |
972412b6 | 871 | .emac_pdata = &dm646x_emac_pdata, |
0d04eb47 DB |
872 | .sram_dma = 0x10010000, |
873 | .sram_len = SZ_32K, | |
79c3c0b7 MG |
874 | }; |
875 | ||
1c92a554 HP |
876 | void __init dm646x_init_ide() |
877 | { | |
878 | davinci_cfg_reg(DM646X_ATAEN); | |
879 | platform_device_register(&ide_dev); | |
880 | } | |
881 | ||
25acf553 C |
882 | void __init dm646x_init_mcasp0(struct snd_platform_data *pdata) |
883 | { | |
884 | dm646x_mcasp0_device.dev.platform_data = pdata; | |
885 | platform_device_register(&dm646x_mcasp0_device); | |
886 | } | |
887 | ||
888 | void __init dm646x_init_mcasp1(struct snd_platform_data *pdata) | |
889 | { | |
890 | dm646x_mcasp1_device.dev.platform_data = pdata; | |
891 | platform_device_register(&dm646x_mcasp1_device); | |
892 | platform_device_register(&dm646x_dit_device); | |
893 | } | |
894 | ||
85609c1c MK |
895 | void dm646x_setup_vpif(struct vpif_display_config *display_config, |
896 | struct vpif_capture_config *capture_config) | |
897 | { | |
898 | unsigned int value; | |
899 | void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE); | |
900 | ||
901 | value = __raw_readl(base + VSCLKDIS_OFFSET); | |
902 | value &= ~VSCLKDIS_MASK; | |
903 | __raw_writel(value, base + VSCLKDIS_OFFSET); | |
904 | ||
905 | value = __raw_readl(base + VDD3P3V_PWDN_OFFSET); | |
906 | value &= ~VDD3P3V_VID_MASK; | |
907 | __raw_writel(value, base + VDD3P3V_PWDN_OFFSET); | |
908 | ||
909 | davinci_cfg_reg(DM646X_STSOMUX_DISABLE); | |
910 | davinci_cfg_reg(DM646X_STSIMUX_DISABLE); | |
911 | davinci_cfg_reg(DM646X_PTSOMUX_DISABLE); | |
912 | davinci_cfg_reg(DM646X_PTSIMUX_DISABLE); | |
913 | ||
914 | vpif_display_dev.dev.platform_data = display_config; | |
915 | vpif_capture_dev.dev.platform_data = capture_config; | |
916 | platform_device_register(&vpif_dev); | |
917 | platform_device_register(&vpif_display_dev); | |
918 | platform_device_register(&vpif_capture_dev); | |
919 | } | |
920 | ||
e38d92fd KH |
921 | void __init dm646x_init(void) |
922 | { | |
79c3c0b7 | 923 | davinci_common_init(&davinci_soc_info_dm646x); |
e38d92fd KH |
924 | } |
925 | ||
926 | static int __init dm646x_init_devices(void) | |
927 | { | |
928 | if (!cpu_is_davinci_dm646x()) | |
929 | return 0; | |
930 | ||
931 | platform_device_register(&dm646x_edma_device); | |
972412b6 | 932 | platform_device_register(&dm646x_emac_device); |
e38d92fd KH |
933 | return 0; |
934 | } | |
935 | postcore_initcall(dm646x_init_devices); |