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ARM: davinci: dm365: move private definitions to C file
[deliverable/linux.git] / arch / arm / mach-davinci / dm646x.c
CommitLineData
e38d92fd
KH		 1/*
2 * TI DaVinci DM644x chip specific setup
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
b7f080cf 11#include <linux/dma-mapping.h>
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KH		 12#include <linux/init.h>
13#include <linux/clk.h>
65e866a9 14#include <linux/serial_8250.h>
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KH		 15#include <linux/platform_device.h>
16
79c3c0b7
MG		 17#include <asm/mach/map.h>
18
e38d92fd 19#include <mach/dm646x.h>
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KH		 20#include <mach/cputype.h>
21#include <mach/edma.h>
22#include <mach/irqs.h>
23#include <mach/psc.h>
24#include <mach/mux.h>
f64691b3 25#include <mach/time.h>
65e866a9 26#include <mach/serial.h>
79c3c0b7 27#include <mach/common.h>
25acf553 28#include <mach/asp.h>
5f3fcf96 29#include <mach/gpio-davinci.h>
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KH		 30
31#include "clock.h"
32#include "mux.h"
33
85609c1c
MK		 34#define DAVINCI_VPIF_BASE (0x01C12000)
35#define VDD3P3V_PWDN_OFFSET (0x48)
36#define VSCLKDIS_OFFSET (0x6C)
37
38#define VDD3P3V_VID_MASK (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\
39 BIT_MASK(0))
40#define VSCLKDIS_MASK (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\
41 BIT_MASK(8))
42
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KH		 43/*
44 * Device specific clocks
45 */
56e580d7 46#define DM646X_REF_FREQ 27000000
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KH		 47#define DM646X_AUX_FREQ 24000000
48
49static struct pll_data pll1_data = {
50 .num = 1,
51 .phys_base = DAVINCI_PLL1_BASE,
52};
53
54static struct pll_data pll2_data = {
55 .num = 2,
56 .phys_base = DAVINCI_PLL2_BASE,
57};
58
59static struct clk ref_clk = {
60 .name = "ref_clk",
56e580d7
SN		 61 .rate = DM646X_REF_FREQ,
62 .set_rate = davinci_simple_set_rate,
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KH		 63};
64
65static struct clk aux_clkin = {
66 .name = "aux_clkin",
67 .rate = DM646X_AUX_FREQ,
68};
69
70static struct clk pll1_clk = {
71 .name = "pll1",
72 .parent = &ref_clk,
73 .pll_data = &pll1_data,
74 .flags = CLK_PLL,
75};
76
77static struct clk pll1_sysclk1 = {
78 .name = "pll1_sysclk1",
79 .parent = &pll1_clk,
80 .flags = CLK_PLL,
81 .div_reg = PLLDIV1,
82};
83
84static struct clk pll1_sysclk2 = {
85 .name = "pll1_sysclk2",
86 .parent = &pll1_clk,
87 .flags = CLK_PLL,
88 .div_reg = PLLDIV2,
89};
90
91static struct clk pll1_sysclk3 = {
92 .name = "pll1_sysclk3",
93 .parent = &pll1_clk,
94 .flags = CLK_PLL,
95 .div_reg = PLLDIV3,
96};
97
98static struct clk pll1_sysclk4 = {
99 .name = "pll1_sysclk4",
100 .parent = &pll1_clk,
101 .flags = CLK_PLL,
102 .div_reg = PLLDIV4,
103};
104
105static struct clk pll1_sysclk5 = {
106 .name = "pll1_sysclk5",
107 .parent = &pll1_clk,
108 .flags = CLK_PLL,
109 .div_reg = PLLDIV5,
110};
111
112static struct clk pll1_sysclk6 = {
113 .name = "pll1_sysclk6",
114 .parent = &pll1_clk,
115 .flags = CLK_PLL,
116 .div_reg = PLLDIV6,
117};
118
119static struct clk pll1_sysclk8 = {
120 .name = "pll1_sysclk8",
121 .parent = &pll1_clk,
122 .flags = CLK_PLL,
123 .div_reg = PLLDIV8,
124};
125
126static struct clk pll1_sysclk9 = {
127 .name = "pll1_sysclk9",
128 .parent = &pll1_clk,
129 .flags = CLK_PLL,
130 .div_reg = PLLDIV9,
131};
132
133static struct clk pll1_sysclkbp = {
134 .name = "pll1_sysclkbp",
135 .parent = &pll1_clk,
136 .flags = CLK_PLL | PRE_PLL,
137 .div_reg = BPDIV,
138};
139
140static struct clk pll1_aux_clk = {
141 .name = "pll1_aux_clk",
142 .parent = &pll1_clk,
143 .flags = CLK_PLL | PRE_PLL,
144};
145
146static struct clk pll2_clk = {
147 .name = "pll2_clk",
148 .parent = &ref_clk,
149 .pll_data = &pll2_data,
150 .flags = CLK_PLL,
151};
152
153static struct clk pll2_sysclk1 = {
154 .name = "pll2_sysclk1",
155 .parent = &pll2_clk,
156 .flags = CLK_PLL,
157 .div_reg = PLLDIV1,
158};
159
160static struct clk dsp_clk = {
161 .name = "dsp",
162 .parent = &pll1_sysclk1,
163 .lpsc = DM646X_LPSC_C64X_CPU,
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KH		 164 .usecount = 1, /* REVISIT how to disable? */
165};
166
167static struct clk arm_clk = {
168 .name = "arm",
169 .parent = &pll1_sysclk2,
170 .lpsc = DM646X_LPSC_ARM,
171 .flags = ALWAYS_ENABLED,
172};
173
2bcb613a
SR		 174static struct clk edma_cc_clk = {
175 .name = "edma_cc",
176 .parent = &pll1_sysclk2,
177 .lpsc = DM646X_LPSC_TPCC,
178 .flags = ALWAYS_ENABLED,
179};
180
181static struct clk edma_tc0_clk = {
182 .name = "edma_tc0",
183 .parent = &pll1_sysclk2,
184 .lpsc = DM646X_LPSC_TPTC0,
185 .flags = ALWAYS_ENABLED,
186};
187
188static struct clk edma_tc1_clk = {
189 .name = "edma_tc1",
190 .parent = &pll1_sysclk2,
191 .lpsc = DM646X_LPSC_TPTC1,
192 .flags = ALWAYS_ENABLED,
193};
194
195static struct clk edma_tc2_clk = {
196 .name = "edma_tc2",
197 .parent = &pll1_sysclk2,
198 .lpsc = DM646X_LPSC_TPTC2,
199 .flags = ALWAYS_ENABLED,
200};
201
202static struct clk edma_tc3_clk = {
203 .name = "edma_tc3",
204 .parent = &pll1_sysclk2,
205 .lpsc = DM646X_LPSC_TPTC3,
206 .flags = ALWAYS_ENABLED,
207};
208
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KH		 209static struct clk uart0_clk = {
210 .name = "uart0",
211 .parent = &aux_clkin,
212 .lpsc = DM646X_LPSC_UART0,
213};
214
215static struct clk uart1_clk = {
216 .name = "uart1",
217 .parent = &aux_clkin,
218 .lpsc = DM646X_LPSC_UART1,
219};
220
221static struct clk uart2_clk = {
222 .name = "uart2",
223 .parent = &aux_clkin,
224 .lpsc = DM646X_LPSC_UART2,
225};
226
227static struct clk i2c_clk = {
228 .name = "I2CCLK",
229 .parent = &pll1_sysclk3,
230 .lpsc = DM646X_LPSC_I2C,
231};
232
233static struct clk gpio_clk = {
234 .name = "gpio",
235 .parent = &pll1_sysclk3,
236 .lpsc = DM646X_LPSC_GPIO,
237};
238
75d0fa70
C		 239static struct clk mcasp0_clk = {
240 .name = "mcasp0",
241 .parent = &pll1_sysclk3,
242 .lpsc = DM646X_LPSC_McASP0,
243};
244
245static struct clk mcasp1_clk = {
246 .name = "mcasp1",
247 .parent = &pll1_sysclk3,
248 .lpsc = DM646X_LPSC_McASP1,
249};
250
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KH		 251static struct clk aemif_clk = {
252 .name = "aemif",
253 .parent = &pll1_sysclk3,
254 .lpsc = DM646X_LPSC_AEMIF,
255 .flags = ALWAYS_ENABLED,
256};
257
258static struct clk emac_clk = {
259 .name = "emac",
260 .parent = &pll1_sysclk3,
261 .lpsc = DM646X_LPSC_EMAC,
262};
263
264static struct clk pwm0_clk = {
265 .name = "pwm0",
266 .parent = &pll1_sysclk3,
267 .lpsc = DM646X_LPSC_PWM0,
268 .usecount = 1, /* REVIST: disabling hangs system */
269};
270
271static struct clk pwm1_clk = {
272 .name = "pwm1",
273 .parent = &pll1_sysclk3,
274 .lpsc = DM646X_LPSC_PWM1,
275 .usecount = 1, /* REVIST: disabling hangs system */
276};
277
278static struct clk timer0_clk = {
279 .name = "timer0",
280 .parent = &pll1_sysclk3,
281 .lpsc = DM646X_LPSC_TIMER0,
282};
283
284static struct clk timer1_clk = {
285 .name = "timer1",
286 .parent = &pll1_sysclk3,
287 .lpsc = DM646X_LPSC_TIMER1,
288};
289
290static struct clk timer2_clk = {
291 .name = "timer2",
292 .parent = &pll1_sysclk3,
293 .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */
294};
295
3e25d5f4
HP		 296
297static struct clk ide_clk = {
298 .name = "ide",
299 .parent = &pll1_sysclk4,
300 .lpsc = DAVINCI_LPSC_ATA,
301};
302
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KH		 303static struct clk vpif0_clk = {
304 .name = "vpif0",
305 .parent = &ref_clk,
306 .lpsc = DM646X_LPSC_VPSSMSTR,
307 .flags = ALWAYS_ENABLED,
308};
309
310static struct clk vpif1_clk = {
311 .name = "vpif1",
312 .parent = &ref_clk,
313 .lpsc = DM646X_LPSC_VPSSSLV,
314 .flags = ALWAYS_ENABLED,
315};
316
28552c2e 317static struct clk_lookup dm646x_clks[] = {
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KH		 318 CLK(NULL, "ref", &ref_clk),
319 CLK(NULL, "aux", &aux_clkin),
320 CLK(NULL, "pll1", &pll1_clk),
321 CLK(NULL, "pll1_sysclk", &pll1_sysclk1),
322 CLK(NULL, "pll1_sysclk", &pll1_sysclk2),
323 CLK(NULL, "pll1_sysclk", &pll1_sysclk3),
324 CLK(NULL, "pll1_sysclk", &pll1_sysclk4),
325 CLK(NULL, "pll1_sysclk", &pll1_sysclk5),
326 CLK(NULL, "pll1_sysclk", &pll1_sysclk6),
327 CLK(NULL, "pll1_sysclk", &pll1_sysclk8),
328 CLK(NULL, "pll1_sysclk", &pll1_sysclk9),
329 CLK(NULL, "pll1_sysclk", &pll1_sysclkbp),
330 CLK(NULL, "pll1_aux", &pll1_aux_clk),
331 CLK(NULL, "pll2", &pll2_clk),
332 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
333 CLK(NULL, "dsp", &dsp_clk),
334 CLK(NULL, "arm", &arm_clk),
2bcb613a
SR		 335 CLK(NULL, "edma_cc", &edma_cc_clk),
336 CLK(NULL, "edma_tc0", &edma_tc0_clk),
337 CLK(NULL, "edma_tc1", &edma_tc1_clk),
338 CLK(NULL, "edma_tc2", &edma_tc2_clk),
339 CLK(NULL, "edma_tc3", &edma_tc3_clk),
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KH		 340 CLK(NULL, "uart0", &uart0_clk),
341 CLK(NULL, "uart1", &uart1_clk),
342 CLK(NULL, "uart2", &uart2_clk),
343 CLK("i2c_davinci.1", NULL, &i2c_clk),
344 CLK(NULL, "gpio", &gpio_clk),
61aa0732
KH		 345 CLK("davinci-mcasp.0", NULL, &mcasp0_clk),
346 CLK("davinci-mcasp.1", NULL, &mcasp1_clk),
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KH		 347 CLK(NULL, "aemif", &aemif_clk),
348 CLK("davinci_emac.1", NULL, &emac_clk),
349 CLK(NULL, "pwm0", &pwm0_clk),
350 CLK(NULL, "pwm1", &pwm1_clk),
351 CLK(NULL, "timer0", &timer0_clk),
352 CLK(NULL, "timer1", &timer1_clk),
353 CLK("watchdog", NULL, &timer2_clk),
3e25d5f4 354 CLK("palm_bk3710", NULL, &ide_clk),
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KH		 355 CLK(NULL, "vpif0", &vpif0_clk),
356 CLK(NULL, "vpif1", &vpif1_clk),
357 CLK(NULL, NULL, NULL),
358};
359
972412b6
MG		 360static struct emac_platform_data dm646x_emac_pdata = {
361 .ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET,
362 .ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET,
363 .ctrl_ram_offset = DM646X_EMAC_CNTRL_RAM_OFFSET,
972412b6
MG		 364 .ctrl_ram_size = DM646X_EMAC_CNTRL_RAM_SIZE,
365 .version = EMAC_VERSION_2,
366};
367
ac7b75b5
KH		 368static struct resource dm646x_emac_resources[] = {
369 {
370 .start = DM646X_EMAC_BASE,
d22960c8 371 .end = DM646X_EMAC_BASE + SZ_16K - 1,
ac7b75b5
KH		 372 .flags = IORESOURCE_MEM,
373 },
374 {
375 .start = IRQ_DM646X_EMACRXTHINT,
376 .end = IRQ_DM646X_EMACRXTHINT,
377 .flags = IORESOURCE_IRQ,
378 },
379 {
380 .start = IRQ_DM646X_EMACRXINT,
381 .end = IRQ_DM646X_EMACRXINT,
382 .flags = IORESOURCE_IRQ,
383 },
384 {
385 .start = IRQ_DM646X_EMACTXINT,
386 .end = IRQ_DM646X_EMACTXINT,
387 .flags = IORESOURCE_IRQ,
388 },
389 {
390 .start = IRQ_DM646X_EMACMISCINT,
391 .end = IRQ_DM646X_EMACMISCINT,
392 .flags = IORESOURCE_IRQ,
393 },
394};
395
396static struct platform_device dm646x_emac_device = {
397 .name = "davinci_emac",
398 .id = 1,
972412b6
MG		 399 .dev = {
400 .platform_data = &dm646x_emac_pdata,
401 },
ac7b75b5
KH		 402 .num_resources = ARRAY_SIZE(dm646x_emac_resources),
403 .resource = dm646x_emac_resources,
404};
405
d22960c8
CC		 406static struct resource dm646x_mdio_resources[] = {
407 {
408 .start = DM646X_EMAC_MDIO_BASE,
409 .end = DM646X_EMAC_MDIO_BASE + SZ_4K - 1,
410 .flags = IORESOURCE_MEM,
411 },
412};
413
414static struct platform_device dm646x_mdio_device = {
415 .name = "davinci_mdio",
416 .id = 0,
417 .num_resources = ARRAY_SIZE(dm646x_mdio_resources),
418 .resource = dm646x_mdio_resources,
419};
420
e38d92fd
KH		 421/*
422 * Device specific mux setup
423 *
424 * soc description mux mode mode mux dbg
425 * reg offset mask mode
426 */
427static const struct mux_config dm646x_pins[] = {
0e585952 428#ifdef CONFIG_DAVINCI_MUX
3e25d5f4 429MUX_CFG(DM646X, ATAEN, 0, 0, 5, 1, true)
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KH		 430
431MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false)
432
433MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false)
434
435MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true)
436
437MUX_CFG(DM646X, STSOMUX_DISABLE, 0, 22, 3, 0, true)
438
439MUX_CFG(DM646X, STSIMUX_DISABLE, 0, 20, 3, 0, true)
440
441MUX_CFG(DM646X, PTSOMUX_DISABLE, 0, 18, 3, 0, true)
442
443MUX_CFG(DM646X, PTSIMUX_DISABLE, 0, 16, 3, 0, true)
444
445MUX_CFG(DM646X, STSOMUX, 0, 22, 3, 2, true)
446
447MUX_CFG(DM646X, STSIMUX, 0, 20, 3, 2, true)
448
449MUX_CFG(DM646X, PTSOMUX_PARALLEL, 0, 18, 3, 2, true)
450
451MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true)
452
453MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true)
454
455MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true)
0e585952 456#endif
e38d92fd
KH		 457};
458
673dd36f
MG		 459static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
460 [IRQ_DM646X_VP_VERTINT0] = 7,
461 [IRQ_DM646X_VP_VERTINT1] = 7,
462 [IRQ_DM646X_VP_VERTINT2] = 7,
463 [IRQ_DM646X_VP_VERTINT3] = 7,
464 [IRQ_DM646X_VP_ERRINT] = 7,
465 [IRQ_DM646X_RESERVED_1] = 7,
466 [IRQ_DM646X_RESERVED_2] = 7,
467 [IRQ_DM646X_WDINT] = 7,
468 [IRQ_DM646X_CRGENINT0] = 7,
469 [IRQ_DM646X_CRGENINT1] = 7,
470 [IRQ_DM646X_TSIFINT0] = 7,
471 [IRQ_DM646X_TSIFINT1] = 7,
472 [IRQ_DM646X_VDCEINT] = 7,
473 [IRQ_DM646X_USBINT] = 7,
474 [IRQ_DM646X_USBDMAINT] = 7,
475 [IRQ_DM646X_PCIINT] = 7,
476 [IRQ_CCINT0] = 7, /* dma */
477 [IRQ_CCERRINT] = 7, /* dma */
478 [IRQ_TCERRINT0] = 7, /* dma */
479 [IRQ_TCERRINT] = 7, /* dma */
480 [IRQ_DM646X_TCERRINT2] = 7,
481 [IRQ_DM646X_TCERRINT3] = 7,
482 [IRQ_DM646X_IDE] = 7,
483 [IRQ_DM646X_HPIINT] = 7,
484 [IRQ_DM646X_EMACRXTHINT] = 7,
485 [IRQ_DM646X_EMACRXINT] = 7,
486 [IRQ_DM646X_EMACTXINT] = 7,
487 [IRQ_DM646X_EMACMISCINT] = 7,
488 [IRQ_DM646X_MCASP0TXINT] = 7,
489 [IRQ_DM646X_MCASP0RXINT] = 7,
490 [IRQ_AEMIFINT] = 7,
491 [IRQ_DM646X_RESERVED_3] = 7,
492 [IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */
493 [IRQ_TINT0_TINT34] = 7, /* clocksource */
494 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
495 [IRQ_TINT1_TINT34] = 7, /* system tick */
496 [IRQ_PWMINT0] = 7,
497 [IRQ_PWMINT1] = 7,
498 [IRQ_DM646X_VLQINT] = 7,
499 [IRQ_I2C] = 7,
500 [IRQ_UARTINT0] = 7,
501 [IRQ_UARTINT1] = 7,
502 [IRQ_DM646X_UARTINT2] = 7,
503 [IRQ_DM646X_SPINT0] = 7,
504 [IRQ_DM646X_SPINT1] = 7,
505 [IRQ_DM646X_DSP2ARMINT] = 7,
506 [IRQ_DM646X_RESERVED_4] = 7,
507 [IRQ_DM646X_PSCINT] = 7,
508 [IRQ_DM646X_GPIO0] = 7,
509 [IRQ_DM646X_GPIO1] = 7,
510 [IRQ_DM646X_GPIO2] = 7,
511 [IRQ_DM646X_GPIO3] = 7,
512 [IRQ_DM646X_GPIO4] = 7,
513 [IRQ_DM646X_GPIO5] = 7,
514 [IRQ_DM646X_GPIO6] = 7,
515 [IRQ_DM646X_GPIO7] = 7,
516 [IRQ_DM646X_GPIOBNK0] = 7,
517 [IRQ_DM646X_GPIOBNK1] = 7,
518 [IRQ_DM646X_GPIOBNK2] = 7,
519 [IRQ_DM646X_DDRINT] = 7,
520 [IRQ_DM646X_AEMIFINT] = 7,
521 [IRQ_COMMTX] = 7,
522 [IRQ_COMMRX] = 7,
523 [IRQ_EMUINT] = 7,
524};
525
e38d92fd
KH		 526/*----------------------------------------------------------------------*/
527
60902a2c
SR		 528/* Four Transfer Controllers on DM646x */
529static const s8
530dm646x_queue_tc_mapping[][2] = {
531 /* {event queue no, TC no} */
532 {0, 0},
533 {1, 1},
534 {2, 2},
535 {3, 3},
536 {-1, -1},
537};
538
539static const s8
540dm646x_queue_priority_mapping[][2] = {
541 /* {event queue no, Priority} */
542 {0, 4},
543 {1, 0},
544 {2, 5},
545 {3, 1},
546 {-1, -1},
547};
548
bc3ac9f3
SN		 549static struct edma_soc_info edma_cc0_info = {
550 .n_channel = 64,
551 .n_region = 6, /* 0-1, 4-7 */
552 .n_slot = 512,
553 .n_tc = 4,
554 .n_cc = 1,
555 .queue_tc_mapping = dm646x_queue_tc_mapping,
556 .queue_priority_mapping = dm646x_queue_priority_mapping,
f23fe857 557 .default_queue = EVENTQ_1,
bc3ac9f3
SN		 558};
559
560static struct edma_soc_info *dm646x_edma_info[EDMA_MAX_CC] = {
561 &edma_cc0_info,
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KH		 562};
563
564static struct resource edma_resources[] = {
565 {
60902a2c 566 .name = "edma_cc0",
e38d92fd
KH		 567 .start = 0x01c00000,
568 .end = 0x01c00000 + SZ_64K - 1,
569 .flags = IORESOURCE_MEM,
570 },
571 {
572 .name = "edma_tc0",
573 .start = 0x01c10000,
574 .end = 0x01c10000 + SZ_1K - 1,
575 .flags = IORESOURCE_MEM,
576 },
577 {
578 .name = "edma_tc1",
579 .start = 0x01c10400,
580 .end = 0x01c10400 + SZ_1K - 1,
581 .flags = IORESOURCE_MEM,
582 },
583 {
584 .name = "edma_tc2",
585 .start = 0x01c10800,
586 .end = 0x01c10800 + SZ_1K - 1,
587 .flags = IORESOURCE_MEM,
588 },
589 {
590 .name = "edma_tc3",
591 .start = 0x01c10c00,
592 .end = 0x01c10c00 + SZ_1K - 1,
593 .flags = IORESOURCE_MEM,
594 },
595 {
60902a2c 596 .name = "edma0",
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KH		 597 .start = IRQ_CCINT0,
598 .flags = IORESOURCE_IRQ,
599 },
600 {
60902a2c 601 .name = "edma0_err",
e38d92fd
KH		 602 .start = IRQ_CCERRINT,
603 .flags = IORESOURCE_IRQ,
604 },
605 /* not using TC*_ERR */
606};
607
608static struct platform_device dm646x_edma_device = {
609 .name = "edma",
60902a2c
SR		 610 .id = 0,
611 .dev.platform_data = dm646x_edma_info,
e38d92fd
KH		 612 .num_resources = ARRAY_SIZE(edma_resources),
613 .resource = edma_resources,
614};
615
25acf553
C		 616static struct resource dm646x_mcasp0_resources[] = {
617 {
618 .name = "mcasp0",
619 .start = DAVINCI_DM646X_MCASP0_REG_BASE,
620 .end = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
621 .flags = IORESOURCE_MEM,
622 },
623 /* first TX, then RX */
624 {
625 .start = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
626 .end = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
627 .flags = IORESOURCE_DMA,
628 },
629 {
630 .start = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
631 .end = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
632 .flags = IORESOURCE_DMA,
633 },
634};
635
636static struct resource dm646x_mcasp1_resources[] = {
637 {
638 .name = "mcasp1",
639 .start = DAVINCI_DM646X_MCASP1_REG_BASE,
640 .end = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
641 .flags = IORESOURCE_MEM,
642 },
643 /* DIT mode, only TX event */
644 {
645 .start = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
646 .end = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
647 .flags = IORESOURCE_DMA,
648 },
649 /* DIT mode, dummy entry */
650 {
651 .start = -1,
652 .end = -1,
653 .flags = IORESOURCE_DMA,
654 },
655};
656
657static struct platform_device dm646x_mcasp0_device = {
658 .name = "davinci-mcasp",
659 .id = 0,
660 .num_resources = ARRAY_SIZE(dm646x_mcasp0_resources),
661 .resource = dm646x_mcasp0_resources,
662};
663
664static struct platform_device dm646x_mcasp1_device = {
665 .name = "davinci-mcasp",
666 .id = 1,
667 .num_resources = ARRAY_SIZE(dm646x_mcasp1_resources),
668 .resource = dm646x_mcasp1_resources,
669};
670
671static struct platform_device dm646x_dit_device = {
672 .name = "spdif-dit",
673 .id = -1,
674};
675
85609c1c
MK		 676static u64 vpif_dma_mask = DMA_BIT_MASK(32);
677
678static struct resource vpif_resource[] = {
679 {
680 .start = DAVINCI_VPIF_BASE,
681 .end = DAVINCI_VPIF_BASE + 0x03ff,
682 .flags = IORESOURCE_MEM,
683 }
684};
685
686static struct platform_device vpif_dev = {
687 .name = "vpif",
688 .id = -1,
689 .dev = {
690 .dma_mask = &vpif_dma_mask,
691 .coherent_dma_mask = DMA_BIT_MASK(32),
692 },
693 .resource = vpif_resource,
694 .num_resources = ARRAY_SIZE(vpif_resource),
695};
696
697static struct resource vpif_display_resource[] = {
698 {
699 .start = IRQ_DM646X_VP_VERTINT2,
700 .end = IRQ_DM646X_VP_VERTINT2,
701 .flags = IORESOURCE_IRQ,
702 },
703 {
704 .start = IRQ_DM646X_VP_VERTINT3,
705 .end = IRQ_DM646X_VP_VERTINT3,
706 .flags = IORESOURCE_IRQ,
707 },
708};
709
710static struct platform_device vpif_display_dev = {
711 .name = "vpif_display",
712 .id = -1,
713 .dev = {
714 .dma_mask = &vpif_dma_mask,
715 .coherent_dma_mask = DMA_BIT_MASK(32),
716 },
717 .resource = vpif_display_resource,
718 .num_resources = ARRAY_SIZE(vpif_display_resource),
719};
720
721static struct resource vpif_capture_resource[] = {
722 {
723 .start = IRQ_DM646X_VP_VERTINT0,
724 .end = IRQ_DM646X_VP_VERTINT0,
725 .flags = IORESOURCE_IRQ,
726 },
727 {
728 .start = IRQ_DM646X_VP_VERTINT1,
729 .end = IRQ_DM646X_VP_VERTINT1,
730 .flags = IORESOURCE_IRQ,
731 },
732};
733
734static struct platform_device vpif_capture_dev = {
735 .name = "vpif_capture",
736 .id = -1,
737 .dev = {
738 .dma_mask = &vpif_dma_mask,
739 .coherent_dma_mask = DMA_BIT_MASK(32),
740 },
741 .resource = vpif_capture_resource,
742 .num_resources = ARRAY_SIZE(vpif_capture_resource),
743};
744
e38d92fd
KH		 745/*----------------------------------------------------------------------*/
746
79c3c0b7
MG		 747static struct map_desc dm646x_io_desc[] = {
748 {
749 .virtual = IO_VIRT,
750 .pfn = __phys_to_pfn(IO_PHYS),
751 .length = IO_SIZE,
752 .type = MT_DEVICE
753 },
0d04eb47
DB		 754 {
755 .virtual = SRAM_VIRT,
756 .pfn = __phys_to_pfn(0x00010000),
757 .length = SZ_32K,
2de5c00a 758 .type = MT_MEMORY_NONCACHED,
0d04eb47 759 },
79c3c0b7
MG		 760};
761
b9ab1279
MG		 762/* Contents of JTAG ID register used to identify exact cpu type */
763static struct davinci_id dm646x_ids[] = {
764 {
765 .variant = 0x0,
766 .part_no = 0xb770,
767 .manufacturer = 0x017,
768 .cpu_id = DAVINCI_CPU_ID_DM6467,
f63dd12d
HP		 769 .name = "dm6467_rev1.x",
770 },
771 {
772 .variant = 0x1,
773 .part_no = 0xb770,
774 .manufacturer = 0x017,
775 .cpu_id = DAVINCI_CPU_ID_DM6467,
776 .name = "dm6467_rev3.x",
b9ab1279
MG		 777 },
778};
779
e4c822c7 780static u32 dm646x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
d81d188c 781
f64691b3
MG		 782/*
783 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
784 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
785 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
786 * T1_TOP: Timer 1, top : <unused>
787 */
28552c2e 788static struct davinci_timer_info dm646x_timer_info = {
f64691b3
MG		 789 .timers = davinci_timer_instance,
790 .clockevent_id = T0_BOT,
791 .clocksource_id = T0_TOP,
792};
793
65e866a9
MG		 794static struct plat_serial8250_port dm646x_serial_platform_data[] = {
795 {
796 .mapbase = DAVINCI_UART0_BASE,
797 .irq = IRQ_UARTINT0,
798 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
799 UPF_IOREMAP,
800 .iotype = UPIO_MEM32,
801 .regshift = 2,
802 },
803 {
804 .mapbase = DAVINCI_UART1_BASE,
805 .irq = IRQ_UARTINT1,
806 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
807 UPF_IOREMAP,
808 .iotype = UPIO_MEM32,
809 .regshift = 2,
810 },
811 {
812 .mapbase = DAVINCI_UART2_BASE,
813 .irq = IRQ_DM646X_UARTINT2,
814 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
815 UPF_IOREMAP,
816 .iotype = UPIO_MEM32,
817 .regshift = 2,
818 },
819 {
820 .flags = 0
821 },
822};
823
824static struct platform_device dm646x_serial_device = {
825 .name = "serial8250",
826 .id = PLAT8250_DEV_PLATFORM,
827 .dev = {
828 .platform_data = dm646x_serial_platform_data,
829 },
830};
831
79c3c0b7
MG		 832static struct davinci_soc_info davinci_soc_info_dm646x = {
833 .io_desc = dm646x_io_desc,
834 .io_desc_num = ARRAY_SIZE(dm646x_io_desc),
3347db83 835 .jtag_id_reg = 0x01c40028,
b9ab1279
MG		 836 .ids = dm646x_ids,
837 .ids_num = ARRAY_SIZE(dm646x_ids),
66e0c399 838 .cpu_clks = dm646x_clks,
d81d188c
MG		 839 .psc_bases = dm646x_psc_bases,
840 .psc_bases_num = ARRAY_SIZE(dm646x_psc_bases),
779b0d53 841 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
0e585952
MG		 842 .pinmux_pins = dm646x_pins,
843 .pinmux_pins_num = ARRAY_SIZE(dm646x_pins),
bd808947 844 .intc_base = DAVINCI_ARM_INTC_BASE,
673dd36f
MG		 845 .intc_type = DAVINCI_INTC_TYPE_AINTC,
846 .intc_irq_prios = dm646x_default_priorities,
847 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
f64691b3 848 .timer_info = &dm646x_timer_info,
686b634a 849 .gpio_type = GPIO_TYPE_DAVINCI,
b8d44293 850 .gpio_base = DAVINCI_GPIO_BASE,
a994955c
MG		 851 .gpio_num = 43, /* Only 33 usable */
852 .gpio_irq = IRQ_DM646X_GPIOBNK0,
65e866a9 853 .serial_dev = &dm646x_serial_device,
972412b6 854 .emac_pdata = &dm646x_emac_pdata,
0d04eb47
DB		 855 .sram_dma = 0x10010000,
856 .sram_len = SZ_32K,
79c3c0b7
MG		 857};
858
25acf553
C		 859void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
860{
861 dm646x_mcasp0_device.dev.platform_data = pdata;
862 platform_device_register(&dm646x_mcasp0_device);
863}
864
865void __init dm646x_init_mcasp1(struct snd_platform_data *pdata)
866{
867 dm646x_mcasp1_device.dev.platform_data = pdata;
868 platform_device_register(&dm646x_mcasp1_device);
869 platform_device_register(&dm646x_dit_device);
870}
871
85609c1c
MK		 872void dm646x_setup_vpif(struct vpif_display_config *display_config,
873 struct vpif_capture_config *capture_config)
874{
875 unsigned int value;
876 void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
877
878 value = __raw_readl(base + VSCLKDIS_OFFSET);
879 value &= ~VSCLKDIS_MASK;
880 __raw_writel(value, base + VSCLKDIS_OFFSET);
881
882 value = __raw_readl(base + VDD3P3V_PWDN_OFFSET);
883 value &= ~VDD3P3V_VID_MASK;
884 __raw_writel(value, base + VDD3P3V_PWDN_OFFSET);
885
886 davinci_cfg_reg(DM646X_STSOMUX_DISABLE);
887 davinci_cfg_reg(DM646X_STSIMUX_DISABLE);
888 davinci_cfg_reg(DM646X_PTSOMUX_DISABLE);
889 davinci_cfg_reg(DM646X_PTSIMUX_DISABLE);
890
891 vpif_display_dev.dev.platform_data = display_config;
892 vpif_capture_dev.dev.platform_data = capture_config;
893 platform_device_register(&vpif_dev);
894 platform_device_register(&vpif_display_dev);
895 platform_device_register(&vpif_capture_dev);
896}
897
cce3dddb
RS		 898int __init dm646x_init_edma(struct edma_rsv_info *rsv)
899{
900 edma_cc0_info.rsv = rsv;
901
902 return platform_device_register(&dm646x_edma_device);
903}
904
e38d92fd
KH		 905void __init dm646x_init(void)
906{
79c3c0b7 907 davinci_common_init(&davinci_soc_info_dm646x);
e38d92fd
KH		 908}
909
910static int __init dm646x_init_devices(void)
911{
912 if (!cpu_is_davinci_dm646x())
913 return 0;
914
d22960c8 915 platform_device_register(&dm646x_mdio_device);
972412b6 916 platform_device_register(&dm646x_emac_device);
d22960c8
CC		 917 clk_add_alias(NULL, dev_name(&dm646x_mdio_device.dev),
918 NULL, &dm646x_emac_device.dev);
919
e38d92fd
KH		 920 return 0;
921}
922postcore_initcall(dm646x_init_devices);
Linux kernel - Deliverables
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