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ARM: davinci: da8xx: remove hard coding of rtc device wakeup
[deliverable/linux.git] / arch / arm / mach-davinci / dm646x.c
CommitLineData
e38d92fd
KH		 1/*
2 * TI DaVinci DM644x chip specific setup
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
b7f080cf 11#include <linux/dma-mapping.h>
e38d92fd
KH		 12#include <linux/init.h>
13#include <linux/clk.h>
65e866a9 14#include <linux/serial_8250.h>
e38d92fd 15#include <linux/platform_device.h>
3ad7a42d 16#include <linux/platform_data/edma.h>
e38d92fd 17
79c3c0b7
MG		 18#include <asm/mach/map.h>
19
e38d92fd 20#include <mach/cputype.h>
e38d92fd
KH		 21#include <mach/irqs.h>
22#include <mach/psc.h>
23#include <mach/mux.h>
f64691b3 24#include <mach/time.h>
65e866a9 25#include <mach/serial.h>
79c3c0b7 26#include <mach/common.h>
5f3fcf96 27#include <mach/gpio-davinci.h>
e38d92fd 28
39c6d2d1 29#include "davinci.h"
e38d92fd
KH		 30#include "clock.h"
31#include "mux.h"
896f66b7 32#include "asp.h"
e38d92fd 33
85609c1c 34#define DAVINCI_VPIF_BASE (0x01C12000)
85609c1c
MK		 35
36#define VDD3P3V_VID_MASK (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\
37 BIT_MASK(0))
38#define VSCLKDIS_MASK (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\
39 BIT_MASK(8))
40
e38d92fd
KH		 41/*
42 * Device specific clocks
43 */
56e580d7 44#define DM646X_REF_FREQ 27000000
e38d92fd
KH		 45#define DM646X_AUX_FREQ 24000000
46
3d091406
MH		 47#define DM646X_EMAC_BASE 0x01c80000
48#define DM646X_EMAC_MDIO_BASE (DM646X_EMAC_BASE + 0x4000)
49#define DM646X_EMAC_CNTRL_OFFSET 0x0000
50#define DM646X_EMAC_CNTRL_MOD_OFFSET 0x1000
51#define DM646X_EMAC_CNTRL_RAM_OFFSET 0x2000
52#define DM646X_EMAC_CNTRL_RAM_SIZE 0x2000
53
e38d92fd
KH		 54static struct pll_data pll1_data = {
55 .num = 1,
56 .phys_base = DAVINCI_PLL1_BASE,
57};
58
59static struct pll_data pll2_data = {
60 .num = 2,
61 .phys_base = DAVINCI_PLL2_BASE,
62};
63
64static struct clk ref_clk = {
65 .name = "ref_clk",
56e580d7
SN		 66 .rate = DM646X_REF_FREQ,
67 .set_rate = davinci_simple_set_rate,
e38d92fd
KH		 68};
69
70static struct clk aux_clkin = {
71 .name = "aux_clkin",
72 .rate = DM646X_AUX_FREQ,
73};
74
75static struct clk pll1_clk = {
76 .name = "pll1",
77 .parent = &ref_clk,
78 .pll_data = &pll1_data,
79 .flags = CLK_PLL,
80};
81
82static struct clk pll1_sysclk1 = {
83 .name = "pll1_sysclk1",
84 .parent = &pll1_clk,
85 .flags = CLK_PLL,
86 .div_reg = PLLDIV1,
87};
88
89static struct clk pll1_sysclk2 = {
90 .name = "pll1_sysclk2",
91 .parent = &pll1_clk,
92 .flags = CLK_PLL,
93 .div_reg = PLLDIV2,
94};
95
96static struct clk pll1_sysclk3 = {
97 .name = "pll1_sysclk3",
98 .parent = &pll1_clk,
99 .flags = CLK_PLL,
100 .div_reg = PLLDIV3,
101};
102
103static struct clk pll1_sysclk4 = {
104 .name = "pll1_sysclk4",
105 .parent = &pll1_clk,
106 .flags = CLK_PLL,
107 .div_reg = PLLDIV4,
108};
109
110static struct clk pll1_sysclk5 = {
111 .name = "pll1_sysclk5",
112 .parent = &pll1_clk,
113 .flags = CLK_PLL,
114 .div_reg = PLLDIV5,
115};
116
117static struct clk pll1_sysclk6 = {
118 .name = "pll1_sysclk6",
119 .parent = &pll1_clk,
120 .flags = CLK_PLL,
121 .div_reg = PLLDIV6,
122};
123
124static struct clk pll1_sysclk8 = {
125 .name = "pll1_sysclk8",
126 .parent = &pll1_clk,
127 .flags = CLK_PLL,
128 .div_reg = PLLDIV8,
129};
130
131static struct clk pll1_sysclk9 = {
132 .name = "pll1_sysclk9",
133 .parent = &pll1_clk,
134 .flags = CLK_PLL,
135 .div_reg = PLLDIV9,
136};
137
138static struct clk pll1_sysclkbp = {
139 .name = "pll1_sysclkbp",
140 .parent = &pll1_clk,
141 .flags = CLK_PLL | PRE_PLL,
142 .div_reg = BPDIV,
143};
144
145static struct clk pll1_aux_clk = {
146 .name = "pll1_aux_clk",
147 .parent = &pll1_clk,
148 .flags = CLK_PLL | PRE_PLL,
149};
150
151static struct clk pll2_clk = {
152 .name = "pll2_clk",
153 .parent = &ref_clk,
154 .pll_data = &pll2_data,
155 .flags = CLK_PLL,
156};
157
158static struct clk pll2_sysclk1 = {
159 .name = "pll2_sysclk1",
160 .parent = &pll2_clk,
161 .flags = CLK_PLL,
162 .div_reg = PLLDIV1,
163};
164
165static struct clk dsp_clk = {
166 .name = "dsp",
167 .parent = &pll1_sysclk1,
168 .lpsc = DM646X_LPSC_C64X_CPU,
e38d92fd
KH		 169 .usecount = 1, /* REVISIT how to disable? */
170};
171
172static struct clk arm_clk = {
173 .name = "arm",
174 .parent = &pll1_sysclk2,
175 .lpsc = DM646X_LPSC_ARM,
176 .flags = ALWAYS_ENABLED,
177};
178
2bcb613a
SR		 179static struct clk edma_cc_clk = {
180 .name = "edma_cc",
181 .parent = &pll1_sysclk2,
182 .lpsc = DM646X_LPSC_TPCC,
183 .flags = ALWAYS_ENABLED,
184};
185
186static struct clk edma_tc0_clk = {
187 .name = "edma_tc0",
188 .parent = &pll1_sysclk2,
189 .lpsc = DM646X_LPSC_TPTC0,
190 .flags = ALWAYS_ENABLED,
191};
192
193static struct clk edma_tc1_clk = {
194 .name = "edma_tc1",
195 .parent = &pll1_sysclk2,
196 .lpsc = DM646X_LPSC_TPTC1,
197 .flags = ALWAYS_ENABLED,
198};
199
200static struct clk edma_tc2_clk = {
201 .name = "edma_tc2",
202 .parent = &pll1_sysclk2,
203 .lpsc = DM646X_LPSC_TPTC2,
204 .flags = ALWAYS_ENABLED,
205};
206
207static struct clk edma_tc3_clk = {
208 .name = "edma_tc3",
209 .parent = &pll1_sysclk2,
210 .lpsc = DM646X_LPSC_TPTC3,
211 .flags = ALWAYS_ENABLED,
212};
213
e38d92fd
KH		 214static struct clk uart0_clk = {
215 .name = "uart0",
216 .parent = &aux_clkin,
217 .lpsc = DM646X_LPSC_UART0,
218};
219
220static struct clk uart1_clk = {
221 .name = "uart1",
222 .parent = &aux_clkin,
223 .lpsc = DM646X_LPSC_UART1,
224};
225
226static struct clk uart2_clk = {
227 .name = "uart2",
228 .parent = &aux_clkin,
229 .lpsc = DM646X_LPSC_UART2,
230};
231
232static struct clk i2c_clk = {
233 .name = "I2CCLK",
234 .parent = &pll1_sysclk3,
235 .lpsc = DM646X_LPSC_I2C,
236};
237
238static struct clk gpio_clk = {
239 .name = "gpio",
240 .parent = &pll1_sysclk3,
241 .lpsc = DM646X_LPSC_GPIO,
242};
243
75d0fa70
C		 244static struct clk mcasp0_clk = {
245 .name = "mcasp0",
246 .parent = &pll1_sysclk3,
247 .lpsc = DM646X_LPSC_McASP0,
248};
249
250static struct clk mcasp1_clk = {
251 .name = "mcasp1",
252 .parent = &pll1_sysclk3,
253 .lpsc = DM646X_LPSC_McASP1,
254};
255
e38d92fd
KH		 256static struct clk aemif_clk = {
257 .name = "aemif",
258 .parent = &pll1_sysclk3,
259 .lpsc = DM646X_LPSC_AEMIF,
260 .flags = ALWAYS_ENABLED,
261};
262
263static struct clk emac_clk = {
264 .name = "emac",
265 .parent = &pll1_sysclk3,
266 .lpsc = DM646X_LPSC_EMAC,
267};
268
269static struct clk pwm0_clk = {
270 .name = "pwm0",
271 .parent = &pll1_sysclk3,
272 .lpsc = DM646X_LPSC_PWM0,
273 .usecount = 1, /* REVIST: disabling hangs system */
274};
275
276static struct clk pwm1_clk = {
277 .name = "pwm1",
278 .parent = &pll1_sysclk3,
279 .lpsc = DM646X_LPSC_PWM1,
280 .usecount = 1, /* REVIST: disabling hangs system */
281};
282
283static struct clk timer0_clk = {
284 .name = "timer0",
285 .parent = &pll1_sysclk3,
286 .lpsc = DM646X_LPSC_TIMER0,
287};
288
289static struct clk timer1_clk = {
290 .name = "timer1",
291 .parent = &pll1_sysclk3,
292 .lpsc = DM646X_LPSC_TIMER1,
293};
294
295static struct clk timer2_clk = {
296 .name = "timer2",
297 .parent = &pll1_sysclk3,
298 .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */
299};
300
3e25d5f4
HP		 301
302static struct clk ide_clk = {
303 .name = "ide",
304 .parent = &pll1_sysclk4,
305 .lpsc = DAVINCI_LPSC_ATA,
306};
307
e38d92fd
KH		 308static struct clk vpif0_clk = {
309 .name = "vpif0",
310 .parent = &ref_clk,
311 .lpsc = DM646X_LPSC_VPSSMSTR,
312 .flags = ALWAYS_ENABLED,
313};
314
315static struct clk vpif1_clk = {
316 .name = "vpif1",
317 .parent = &ref_clk,
318 .lpsc = DM646X_LPSC_VPSSSLV,
319 .flags = ALWAYS_ENABLED,
320};
321
28552c2e 322static struct clk_lookup dm646x_clks[] = {
e38d92fd
KH		 323 CLK(NULL, "ref", &ref_clk),
324 CLK(NULL, "aux", &aux_clkin),
325 CLK(NULL, "pll1", &pll1_clk),
326 CLK(NULL, "pll1_sysclk", &pll1_sysclk1),
327 CLK(NULL, "pll1_sysclk", &pll1_sysclk2),
328 CLK(NULL, "pll1_sysclk", &pll1_sysclk3),
329 CLK(NULL, "pll1_sysclk", &pll1_sysclk4),
330 CLK(NULL, "pll1_sysclk", &pll1_sysclk5),
331 CLK(NULL, "pll1_sysclk", &pll1_sysclk6),
332 CLK(NULL, "pll1_sysclk", &pll1_sysclk8),
333 CLK(NULL, "pll1_sysclk", &pll1_sysclk9),
334 CLK(NULL, "pll1_sysclk", &pll1_sysclkbp),
335 CLK(NULL, "pll1_aux", &pll1_aux_clk),
336 CLK(NULL, "pll2", &pll2_clk),
337 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
338 CLK(NULL, "dsp", &dsp_clk),
339 CLK(NULL, "arm", &arm_clk),
2bcb613a
SR		 340 CLK(NULL, "edma_cc", &edma_cc_clk),
341 CLK(NULL, "edma_tc0", &edma_tc0_clk),
342 CLK(NULL, "edma_tc1", &edma_tc1_clk),
343 CLK(NULL, "edma_tc2", &edma_tc2_clk),
344 CLK(NULL, "edma_tc3", &edma_tc3_clk),
19955c3d
MP		 345 CLK("serial8250.0", NULL, &uart0_clk),
346 CLK("serial8250.1", NULL, &uart1_clk),
347 CLK("serial8250.2", NULL, &uart2_clk),
e38d92fd
KH		 348 CLK("i2c_davinci.1", NULL, &i2c_clk),
349 CLK(NULL, "gpio", &gpio_clk),
61aa0732
KH		 350 CLK("davinci-mcasp.0", NULL, &mcasp0_clk),
351 CLK("davinci-mcasp.1", NULL, &mcasp1_clk),
e38d92fd
KH		 352 CLK(NULL, "aemif", &aemif_clk),
353 CLK("davinci_emac.1", NULL, &emac_clk),
354 CLK(NULL, "pwm0", &pwm0_clk),
355 CLK(NULL, "pwm1", &pwm1_clk),
356 CLK(NULL, "timer0", &timer0_clk),
357 CLK(NULL, "timer1", &timer1_clk),
358 CLK("watchdog", NULL, &timer2_clk),
3e25d5f4 359 CLK("palm_bk3710", NULL, &ide_clk),
e38d92fd
KH		 360 CLK(NULL, "vpif0", &vpif0_clk),
361 CLK(NULL, "vpif1", &vpif1_clk),
362 CLK(NULL, NULL, NULL),
363};
364
972412b6
MG		 365static struct emac_platform_data dm646x_emac_pdata = {
366 .ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET,
367 .ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET,
368 .ctrl_ram_offset = DM646X_EMAC_CNTRL_RAM_OFFSET,
972412b6
MG		 369 .ctrl_ram_size = DM646X_EMAC_CNTRL_RAM_SIZE,
370 .version = EMAC_VERSION_2,
371};
372
ac7b75b5
KH		 373static struct resource dm646x_emac_resources[] = {
374 {
375 .start = DM646X_EMAC_BASE,
d22960c8 376 .end = DM646X_EMAC_BASE + SZ_16K - 1,
ac7b75b5
KH		 377 .flags = IORESOURCE_MEM,
378 },
379 {
380 .start = IRQ_DM646X_EMACRXTHINT,
381 .end = IRQ_DM646X_EMACRXTHINT,
382 .flags = IORESOURCE_IRQ,
383 },
384 {
385 .start = IRQ_DM646X_EMACRXINT,
386 .end = IRQ_DM646X_EMACRXINT,
387 .flags = IORESOURCE_IRQ,
388 },
389 {
390 .start = IRQ_DM646X_EMACTXINT,
391 .end = IRQ_DM646X_EMACTXINT,
392 .flags = IORESOURCE_IRQ,
393 },
394 {
395 .start = IRQ_DM646X_EMACMISCINT,
396 .end = IRQ_DM646X_EMACMISCINT,
397 .flags = IORESOURCE_IRQ,
398 },
399};
400
401static struct platform_device dm646x_emac_device = {
402 .name = "davinci_emac",
403 .id = 1,
972412b6
MG		 404 .dev = {
405 .platform_data = &dm646x_emac_pdata,
406 },
ac7b75b5
KH		 407 .num_resources = ARRAY_SIZE(dm646x_emac_resources),
408 .resource = dm646x_emac_resources,
409};
410
d22960c8
CC		 411static struct resource dm646x_mdio_resources[] = {
412 {
413 .start = DM646X_EMAC_MDIO_BASE,
414 .end = DM646X_EMAC_MDIO_BASE + SZ_4K - 1,
415 .flags = IORESOURCE_MEM,
416 },
417};
418
419static struct platform_device dm646x_mdio_device = {
420 .name = "davinci_mdio",
421 .id = 0,
422 .num_resources = ARRAY_SIZE(dm646x_mdio_resources),
423 .resource = dm646x_mdio_resources,
424};
425
e38d92fd
KH		 426/*
427 * Device specific mux setup
428 *
429 * soc description mux mode mode mux dbg
430 * reg offset mask mode
431 */
432static const struct mux_config dm646x_pins[] = {
0e585952 433#ifdef CONFIG_DAVINCI_MUX
3e25d5f4 434MUX_CFG(DM646X, ATAEN, 0, 0, 5, 1, true)
e38d92fd
KH		 435
436MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false)
437
438MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false)
439
440MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true)
441
442MUX_CFG(DM646X, STSOMUX_DISABLE, 0, 22, 3, 0, true)
443
444MUX_CFG(DM646X, STSIMUX_DISABLE, 0, 20, 3, 0, true)
445
446MUX_CFG(DM646X, PTSOMUX_DISABLE, 0, 18, 3, 0, true)
447
448MUX_CFG(DM646X, PTSIMUX_DISABLE, 0, 16, 3, 0, true)
449
450MUX_CFG(DM646X, STSOMUX, 0, 22, 3, 2, true)
451
452MUX_CFG(DM646X, STSIMUX, 0, 20, 3, 2, true)
453
454MUX_CFG(DM646X, PTSOMUX_PARALLEL, 0, 18, 3, 2, true)
455
456MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true)
457
458MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true)
459
460MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true)
0e585952 461#endif
e38d92fd
KH		 462};
463
673dd36f
MG		 464static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
465 [IRQ_DM646X_VP_VERTINT0] = 7,
466 [IRQ_DM646X_VP_VERTINT1] = 7,
467 [IRQ_DM646X_VP_VERTINT2] = 7,
468 [IRQ_DM646X_VP_VERTINT3] = 7,
469 [IRQ_DM646X_VP_ERRINT] = 7,
470 [IRQ_DM646X_RESERVED_1] = 7,
471 [IRQ_DM646X_RESERVED_2] = 7,
472 [IRQ_DM646X_WDINT] = 7,
473 [IRQ_DM646X_CRGENINT0] = 7,
474 [IRQ_DM646X_CRGENINT1] = 7,
475 [IRQ_DM646X_TSIFINT0] = 7,
476 [IRQ_DM646X_TSIFINT1] = 7,
477 [IRQ_DM646X_VDCEINT] = 7,
478 [IRQ_DM646X_USBINT] = 7,
479 [IRQ_DM646X_USBDMAINT] = 7,
480 [IRQ_DM646X_PCIINT] = 7,
481 [IRQ_CCINT0] = 7, /* dma */
482 [IRQ_CCERRINT] = 7, /* dma */
483 [IRQ_TCERRINT0] = 7, /* dma */
484 [IRQ_TCERRINT] = 7, /* dma */
485 [IRQ_DM646X_TCERRINT2] = 7,
486 [IRQ_DM646X_TCERRINT3] = 7,
487 [IRQ_DM646X_IDE] = 7,
488 [IRQ_DM646X_HPIINT] = 7,
489 [IRQ_DM646X_EMACRXTHINT] = 7,
490 [IRQ_DM646X_EMACRXINT] = 7,
491 [IRQ_DM646X_EMACTXINT] = 7,
492 [IRQ_DM646X_EMACMISCINT] = 7,
493 [IRQ_DM646X_MCASP0TXINT] = 7,
494 [IRQ_DM646X_MCASP0RXINT] = 7,
495 [IRQ_AEMIFINT] = 7,
496 [IRQ_DM646X_RESERVED_3] = 7,
497 [IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */
498 [IRQ_TINT0_TINT34] = 7, /* clocksource */
499 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
500 [IRQ_TINT1_TINT34] = 7, /* system tick */
501 [IRQ_PWMINT0] = 7,
502 [IRQ_PWMINT1] = 7,
503 [IRQ_DM646X_VLQINT] = 7,
504 [IRQ_I2C] = 7,
505 [IRQ_UARTINT0] = 7,
506 [IRQ_UARTINT1] = 7,
507 [IRQ_DM646X_UARTINT2] = 7,
508 [IRQ_DM646X_SPINT0] = 7,
509 [IRQ_DM646X_SPINT1] = 7,
510 [IRQ_DM646X_DSP2ARMINT] = 7,
511 [IRQ_DM646X_RESERVED_4] = 7,
512 [IRQ_DM646X_PSCINT] = 7,
513 [IRQ_DM646X_GPIO0] = 7,
514 [IRQ_DM646X_GPIO1] = 7,
515 [IRQ_DM646X_GPIO2] = 7,
516 [IRQ_DM646X_GPIO3] = 7,
517 [IRQ_DM646X_GPIO4] = 7,
518 [IRQ_DM646X_GPIO5] = 7,
519 [IRQ_DM646X_GPIO6] = 7,
520 [IRQ_DM646X_GPIO7] = 7,
521 [IRQ_DM646X_GPIOBNK0] = 7,
522 [IRQ_DM646X_GPIOBNK1] = 7,
523 [IRQ_DM646X_GPIOBNK2] = 7,
524 [IRQ_DM646X_DDRINT] = 7,
525 [IRQ_DM646X_AEMIFINT] = 7,
526 [IRQ_COMMTX] = 7,
527 [IRQ_COMMRX] = 7,
528 [IRQ_EMUINT] = 7,
529};
530
e38d92fd
KH		 531/*----------------------------------------------------------------------*/
532
60902a2c 533/* Four Transfer Controllers on DM646x */
6cba4355 534static s8
60902a2c
SR		 535dm646x_queue_tc_mapping[][2] = {
536 /* {event queue no, TC no} */
537 {0, 0},
538 {1, 1},
539 {2, 2},
540 {3, 3},
541 {-1, -1},
542};
543
6cba4355 544static s8
60902a2c
SR		 545dm646x_queue_priority_mapping[][2] = {
546 /* {event queue no, Priority} */
547 {0, 4},
548 {1, 0},
549 {2, 5},
550 {3, 1},
551 {-1, -1},
552};
553
bc3ac9f3
SN		 554static struct edma_soc_info edma_cc0_info = {
555 .n_channel = 64,
556 .n_region = 6, /* 0-1, 4-7 */
557 .n_slot = 512,
558 .n_tc = 4,
559 .n_cc = 1,
560 .queue_tc_mapping = dm646x_queue_tc_mapping,
561 .queue_priority_mapping = dm646x_queue_priority_mapping,
f23fe857 562 .default_queue = EVENTQ_1,
bc3ac9f3
SN		 563};
564
565static struct edma_soc_info *dm646x_edma_info[EDMA_MAX_CC] = {
566 &edma_cc0_info,
e38d92fd
KH		 567};
568
569static struct resource edma_resources[] = {
570 {
60902a2c 571 .name = "edma_cc0",
e38d92fd
KH		 572 .start = 0x01c00000,
573 .end = 0x01c00000 + SZ_64K - 1,
574 .flags = IORESOURCE_MEM,
575 },
576 {
577 .name = "edma_tc0",
578 .start = 0x01c10000,
579 .end = 0x01c10000 + SZ_1K - 1,
580 .flags = IORESOURCE_MEM,
581 },
582 {
583 .name = "edma_tc1",
584 .start = 0x01c10400,
585 .end = 0x01c10400 + SZ_1K - 1,
586 .flags = IORESOURCE_MEM,
587 },
588 {
589 .name = "edma_tc2",
590 .start = 0x01c10800,
591 .end = 0x01c10800 + SZ_1K - 1,
592 .flags = IORESOURCE_MEM,
593 },
594 {
595 .name = "edma_tc3",
596 .start = 0x01c10c00,
597 .end = 0x01c10c00 + SZ_1K - 1,
598 .flags = IORESOURCE_MEM,
599 },
600 {
60902a2c 601 .name = "edma0",
e38d92fd
KH		 602 .start = IRQ_CCINT0,
603 .flags = IORESOURCE_IRQ,
604 },
605 {
60902a2c 606 .name = "edma0_err",
e38d92fd
KH		 607 .start = IRQ_CCERRINT,
608 .flags = IORESOURCE_IRQ,
609 },
610 /* not using TC*_ERR */
611};
612
613static struct platform_device dm646x_edma_device = {
614 .name = "edma",
60902a2c
SR		 615 .id = 0,
616 .dev.platform_data = dm646x_edma_info,
e38d92fd
KH		 617 .num_resources = ARRAY_SIZE(edma_resources),
618 .resource = edma_resources,
619};
620
25acf553
C		 621static struct resource dm646x_mcasp0_resources[] = {
622 {
623 .name = "mcasp0",
624 .start = DAVINCI_DM646X_MCASP0_REG_BASE,
625 .end = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
626 .flags = IORESOURCE_MEM,
627 },
628 /* first TX, then RX */
629 {
630 .start = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
631 .end = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
632 .flags = IORESOURCE_DMA,
633 },
634 {
635 .start = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
636 .end = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
637 .flags = IORESOURCE_DMA,
638 },
639};
640
641static struct resource dm646x_mcasp1_resources[] = {
642 {
643 .name = "mcasp1",
644 .start = DAVINCI_DM646X_MCASP1_REG_BASE,
645 .end = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
646 .flags = IORESOURCE_MEM,
647 },
648 /* DIT mode, only TX event */
649 {
650 .start = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
651 .end = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
652 .flags = IORESOURCE_DMA,
653 },
654 /* DIT mode, dummy entry */
655 {
656 .start = -1,
657 .end = -1,
658 .flags = IORESOURCE_DMA,
659 },
660};
661
662static struct platform_device dm646x_mcasp0_device = {
663 .name = "davinci-mcasp",
664 .id = 0,
665 .num_resources = ARRAY_SIZE(dm646x_mcasp0_resources),
666 .resource = dm646x_mcasp0_resources,
667};
668
669static struct platform_device dm646x_mcasp1_device = {
670 .name = "davinci-mcasp",
671 .id = 1,
672 .num_resources = ARRAY_SIZE(dm646x_mcasp1_resources),
673 .resource = dm646x_mcasp1_resources,
674};
675
676static struct platform_device dm646x_dit_device = {
677 .name = "spdif-dit",
678 .id = -1,
679};
680
85609c1c
MK		 681static u64 vpif_dma_mask = DMA_BIT_MASK(32);
682
683static struct resource vpif_resource[] = {
684 {
685 .start = DAVINCI_VPIF_BASE,
686 .end = DAVINCI_VPIF_BASE + 0x03ff,
687 .flags = IORESOURCE_MEM,
688 }
689};
690
691static struct platform_device vpif_dev = {
692 .name = "vpif",
693 .id = -1,
694 .dev = {
695 .dma_mask = &vpif_dma_mask,
696 .coherent_dma_mask = DMA_BIT_MASK(32),
697 },
698 .resource = vpif_resource,
699 .num_resources = ARRAY_SIZE(vpif_resource),
700};
701
702static struct resource vpif_display_resource[] = {
703 {
704 .start = IRQ_DM646X_VP_VERTINT2,
705 .end = IRQ_DM646X_VP_VERTINT2,
706 .flags = IORESOURCE_IRQ,
707 },
708 {
709 .start = IRQ_DM646X_VP_VERTINT3,
710 .end = IRQ_DM646X_VP_VERTINT3,
711 .flags = IORESOURCE_IRQ,
712 },
713};
714
715static struct platform_device vpif_display_dev = {
716 .name = "vpif_display",
717 .id = -1,
718 .dev = {
719 .dma_mask = &vpif_dma_mask,
720 .coherent_dma_mask = DMA_BIT_MASK(32),
721 },
722 .resource = vpif_display_resource,
723 .num_resources = ARRAY_SIZE(vpif_display_resource),
724};
725
726static struct resource vpif_capture_resource[] = {
727 {
728 .start = IRQ_DM646X_VP_VERTINT0,
729 .end = IRQ_DM646X_VP_VERTINT0,
730 .flags = IORESOURCE_IRQ,
731 },
732 {
733 .start = IRQ_DM646X_VP_VERTINT1,
734 .end = IRQ_DM646X_VP_VERTINT1,
735 .flags = IORESOURCE_IRQ,
736 },
737};
738
739static struct platform_device vpif_capture_dev = {
740 .name = "vpif_capture",
741 .id = -1,
742 .dev = {
743 .dma_mask = &vpif_dma_mask,
744 .coherent_dma_mask = DMA_BIT_MASK(32),
745 },
746 .resource = vpif_capture_resource,
747 .num_resources = ARRAY_SIZE(vpif_capture_resource),
748};
749
e38d92fd
KH		 750/*----------------------------------------------------------------------*/
751
79c3c0b7
MG		 752static struct map_desc dm646x_io_desc[] = {
753 {
754 .virtual = IO_VIRT,
755 .pfn = __phys_to_pfn(IO_PHYS),
756 .length = IO_SIZE,
757 .type = MT_DEVICE
758 },
759};
760
b9ab1279
MG		 761/* Contents of JTAG ID register used to identify exact cpu type */
762static struct davinci_id dm646x_ids[] = {
763 {
764 .variant = 0x0,
765 .part_no = 0xb770,
766 .manufacturer = 0x017,
767 .cpu_id = DAVINCI_CPU_ID_DM6467,
f63dd12d
HP		 768 .name = "dm6467_rev1.x",
769 },
770 {
771 .variant = 0x1,
772 .part_no = 0xb770,
773 .manufacturer = 0x017,
774 .cpu_id = DAVINCI_CPU_ID_DM6467,
775 .name = "dm6467_rev3.x",
b9ab1279
MG		 776 },
777};
778
e4c822c7 779static u32 dm646x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
d81d188c 780
f64691b3
MG		 781/*
782 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
783 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
784 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
785 * T1_TOP: Timer 1, top : <unused>
786 */
28552c2e 787static struct davinci_timer_info dm646x_timer_info = {
f64691b3
MG		 788 .timers = davinci_timer_instance,
789 .clockevent_id = T0_BOT,
790 .clocksource_id = T0_TOP,
791};
792
19955c3d 793static struct plat_serial8250_port dm646x_serial0_platform_data[] = {
65e866a9
MG		 794 {
795 .mapbase = DAVINCI_UART0_BASE,
796 .irq = IRQ_UARTINT0,
797 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
798 UPF_IOREMAP,
799 .iotype = UPIO_MEM32,
800 .regshift = 2,
801 },
19955c3d
MP		 802 {
803 .flags = 0,
804 }
805};
806static struct plat_serial8250_port dm646x_serial1_platform_data[] = {
65e866a9
MG		 807 {
808 .mapbase = DAVINCI_UART1_BASE,
809 .irq = IRQ_UARTINT1,
810 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
811 UPF_IOREMAP,
812 .iotype = UPIO_MEM32,
813 .regshift = 2,
814 },
19955c3d
MP		 815 {
816 .flags = 0,
817 }
818};
819static struct plat_serial8250_port dm646x_serial2_platform_data[] = {
65e866a9
MG		 820 {
821 .mapbase = DAVINCI_UART2_BASE,
822 .irq = IRQ_DM646X_UARTINT2,
823 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
824 UPF_IOREMAP,
825 .iotype = UPIO_MEM32,
826 .regshift = 2,
827 },
828 {
19955c3d
MP		 829 .flags = 0,
830 }
65e866a9
MG		 831};
832
fcf7157b 833struct platform_device dm646x_serial_device[] = {
19955c3d
MP		 834 {
835 .name = "serial8250",
836 .id = PLAT8250_DEV_PLATFORM,
837 .dev = {
838 .platform_data = dm646x_serial0_platform_data,
839 }
840 },
841 {
842 .name = "serial8250",
843 .id = PLAT8250_DEV_PLATFORM1,
844 .dev = {
845 .platform_data = dm646x_serial1_platform_data,
846 }
65e866a9 847 },
19955c3d
MP		 848 {
849 .name = "serial8250",
850 .id = PLAT8250_DEV_PLATFORM2,
851 .dev = {
852 .platform_data = dm646x_serial2_platform_data,
853 }
854 },
855 {
856 }
65e866a9
MG		 857};
858
79c3c0b7
MG		 859static struct davinci_soc_info davinci_soc_info_dm646x = {
860 .io_desc = dm646x_io_desc,
861 .io_desc_num = ARRAY_SIZE(dm646x_io_desc),
3347db83 862 .jtag_id_reg = 0x01c40028,
b9ab1279
MG		 863 .ids = dm646x_ids,
864 .ids_num = ARRAY_SIZE(dm646x_ids),
66e0c399 865 .cpu_clks = dm646x_clks,
d81d188c
MG		 866 .psc_bases = dm646x_psc_bases,
867 .psc_bases_num = ARRAY_SIZE(dm646x_psc_bases),
779b0d53 868 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
0e585952
MG		 869 .pinmux_pins = dm646x_pins,
870 .pinmux_pins_num = ARRAY_SIZE(dm646x_pins),
bd808947 871 .intc_base = DAVINCI_ARM_INTC_BASE,
673dd36f
MG		 872 .intc_type = DAVINCI_INTC_TYPE_AINTC,
873 .intc_irq_prios = dm646x_default_priorities,
874 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
f64691b3 875 .timer_info = &dm646x_timer_info,
686b634a 876 .gpio_type = GPIO_TYPE_DAVINCI,
b8d44293 877 .gpio_base = DAVINCI_GPIO_BASE,
a994955c
MG		 878 .gpio_num = 43, /* Only 33 usable */
879 .gpio_irq = IRQ_DM646X_GPIOBNK0,
972412b6 880 .emac_pdata = &dm646x_emac_pdata,
0d04eb47
DB		 881 .sram_dma = 0x10010000,
882 .sram_len = SZ_32K,
79c3c0b7
MG		 883};
884
25acf553
C		 885void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
886{
887 dm646x_mcasp0_device.dev.platform_data = pdata;
888 platform_device_register(&dm646x_mcasp0_device);
889}
890
891void __init dm646x_init_mcasp1(struct snd_platform_data *pdata)
892{
893 dm646x_mcasp1_device.dev.platform_data = pdata;
894 platform_device_register(&dm646x_mcasp1_device);
895 platform_device_register(&dm646x_dit_device);
896}
897
85609c1c
MK		 898void dm646x_setup_vpif(struct vpif_display_config *display_config,
899 struct vpif_capture_config *capture_config)
900{
901 unsigned int value;
85609c1c 902
5cfb19ac 903 value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
85609c1c 904 value &= ~VSCLKDIS_MASK;
5cfb19ac 905 __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
85609c1c 906
5cfb19ac 907 value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
85609c1c 908 value &= ~VDD3P3V_VID_MASK;
5cfb19ac 909 __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
85609c1c
MK		 910
911 davinci_cfg_reg(DM646X_STSOMUX_DISABLE);
912 davinci_cfg_reg(DM646X_STSIMUX_DISABLE);
913 davinci_cfg_reg(DM646X_PTSOMUX_DISABLE);
914 davinci_cfg_reg(DM646X_PTSIMUX_DISABLE);
915
916 vpif_display_dev.dev.platform_data = display_config;
917 vpif_capture_dev.dev.platform_data = capture_config;
918 platform_device_register(&vpif_dev);
919 platform_device_register(&vpif_display_dev);
920 platform_device_register(&vpif_capture_dev);
921}
922
cce3dddb
RS		 923int __init dm646x_init_edma(struct edma_rsv_info *rsv)
924{
925 edma_cc0_info.rsv = rsv;
926
927 return platform_device_register(&dm646x_edma_device);
928}
929
e38d92fd
KH		 930void __init dm646x_init(void)
931{
79c3c0b7 932 davinci_common_init(&davinci_soc_info_dm646x);
5cfb19ac 933 davinci_map_sysmod();
e38d92fd
KH		 934}
935
936static int __init dm646x_init_devices(void)
937{
938 if (!cpu_is_davinci_dm646x())
939 return 0;
940
d22960c8 941 platform_device_register(&dm646x_mdio_device);
972412b6 942 platform_device_register(&dm646x_emac_device);
d22960c8
CC		 943 clk_add_alias(NULL, dev_name(&dm646x_mdio_device.dev),
944 NULL, &dm646x_emac_device.dev);
945
e38d92fd
KH		 946 return 0;
947}
948postcore_initcall(dm646x_init_devices);
Linux kernel - Deliverables
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