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a4768d22 KH |
1 | /* |
2 | * EDMA3 support for DaVinci | |
3 | * | |
4 | * Copyright (C) 2006-2009 Texas Instruments. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | */ | |
20 | #include <linux/kernel.h> | |
a4768d22 KH |
21 | #include <linux/init.h> |
22 | #include <linux/module.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/platform_device.h> | |
a4768d22 | 25 | #include <linux/io.h> |
5a0e3ad6 | 26 | #include <linux/slab.h> |
a4768d22 | 27 | |
a4768d22 | 28 | #include <mach/edma.h> |
a4768d22 KH |
29 | |
30 | /* Offsets matching "struct edmacc_param" */ | |
31 | #define PARM_OPT 0x00 | |
32 | #define PARM_SRC 0x04 | |
33 | #define PARM_A_B_CNT 0x08 | |
34 | #define PARM_DST 0x0c | |
35 | #define PARM_SRC_DST_BIDX 0x10 | |
36 | #define PARM_LINK_BCNTRLD 0x14 | |
37 | #define PARM_SRC_DST_CIDX 0x18 | |
38 | #define PARM_CCNT 0x1c | |
39 | ||
40 | #define PARM_SIZE 0x20 | |
41 | ||
42 | /* Offsets for EDMA CC global channel registers and their shadows */ | |
43 | #define SH_ER 0x00 /* 64 bits */ | |
44 | #define SH_ECR 0x08 /* 64 bits */ | |
45 | #define SH_ESR 0x10 /* 64 bits */ | |
46 | #define SH_CER 0x18 /* 64 bits */ | |
47 | #define SH_EER 0x20 /* 64 bits */ | |
48 | #define SH_EECR 0x28 /* 64 bits */ | |
49 | #define SH_EESR 0x30 /* 64 bits */ | |
50 | #define SH_SER 0x38 /* 64 bits */ | |
51 | #define SH_SECR 0x40 /* 64 bits */ | |
52 | #define SH_IER 0x50 /* 64 bits */ | |
53 | #define SH_IECR 0x58 /* 64 bits */ | |
54 | #define SH_IESR 0x60 /* 64 bits */ | |
55 | #define SH_IPR 0x68 /* 64 bits */ | |
56 | #define SH_ICR 0x70 /* 64 bits */ | |
57 | #define SH_IEVAL 0x78 | |
58 | #define SH_QER 0x80 | |
59 | #define SH_QEER 0x84 | |
60 | #define SH_QEECR 0x88 | |
61 | #define SH_QEESR 0x8c | |
62 | #define SH_QSER 0x90 | |
63 | #define SH_QSECR 0x94 | |
64 | #define SH_SIZE 0x200 | |
65 | ||
66 | /* Offsets for EDMA CC global registers */ | |
67 | #define EDMA_REV 0x0000 | |
68 | #define EDMA_CCCFG 0x0004 | |
69 | #define EDMA_QCHMAP 0x0200 /* 8 registers */ | |
70 | #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */ | |
71 | #define EDMA_QDMAQNUM 0x0260 | |
72 | #define EDMA_QUETCMAP 0x0280 | |
73 | #define EDMA_QUEPRI 0x0284 | |
74 | #define EDMA_EMR 0x0300 /* 64 bits */ | |
75 | #define EDMA_EMCR 0x0308 /* 64 bits */ | |
76 | #define EDMA_QEMR 0x0310 | |
77 | #define EDMA_QEMCR 0x0314 | |
78 | #define EDMA_CCERR 0x0318 | |
79 | #define EDMA_CCERRCLR 0x031c | |
80 | #define EDMA_EEVAL 0x0320 | |
81 | #define EDMA_DRAE 0x0340 /* 4 x 64 bits*/ | |
82 | #define EDMA_QRAE 0x0380 /* 4 registers */ | |
83 | #define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */ | |
84 | #define EDMA_QSTAT 0x0600 /* 2 registers */ | |
85 | #define EDMA_QWMTHRA 0x0620 | |
86 | #define EDMA_QWMTHRB 0x0624 | |
87 | #define EDMA_CCSTAT 0x0640 | |
88 | ||
89 | #define EDMA_M 0x1000 /* global channel registers */ | |
90 | #define EDMA_ECR 0x1008 | |
91 | #define EDMA_ECRH 0x100C | |
92 | #define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */ | |
93 | #define EDMA_PARM 0x4000 /* 128 param entries */ | |
94 | ||
a4768d22 KH |
95 | #define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5)) |
96 | ||
60902a2c SR |
97 | #define EDMA_DCHMAP 0x0100 /* 64 registers */ |
98 | #define CHMAP_EXIST BIT(24) | |
99 | ||
a4768d22 KH |
100 | #define EDMA_MAX_DMACH 64 |
101 | #define EDMA_MAX_PARAMENTRY 512 | |
a4768d22 KH |
102 | |
103 | /*****************************************************************************/ | |
104 | ||
60902a2c | 105 | static void __iomem *edmacc_regs_base[EDMA_MAX_CC]; |
a4768d22 | 106 | |
60902a2c | 107 | static inline unsigned int edma_read(unsigned ctlr, int offset) |
a4768d22 | 108 | { |
60902a2c | 109 | return (unsigned int)__raw_readl(edmacc_regs_base[ctlr] + offset); |
a4768d22 KH |
110 | } |
111 | ||
60902a2c | 112 | static inline void edma_write(unsigned ctlr, int offset, int val) |
a4768d22 | 113 | { |
60902a2c | 114 | __raw_writel(val, edmacc_regs_base[ctlr] + offset); |
a4768d22 | 115 | } |
60902a2c SR |
116 | static inline void edma_modify(unsigned ctlr, int offset, unsigned and, |
117 | unsigned or) | |
a4768d22 | 118 | { |
60902a2c | 119 | unsigned val = edma_read(ctlr, offset); |
a4768d22 KH |
120 | val &= and; |
121 | val |= or; | |
60902a2c | 122 | edma_write(ctlr, offset, val); |
a4768d22 | 123 | } |
60902a2c | 124 | static inline void edma_and(unsigned ctlr, int offset, unsigned and) |
a4768d22 | 125 | { |
60902a2c | 126 | unsigned val = edma_read(ctlr, offset); |
a4768d22 | 127 | val &= and; |
60902a2c | 128 | edma_write(ctlr, offset, val); |
a4768d22 | 129 | } |
60902a2c | 130 | static inline void edma_or(unsigned ctlr, int offset, unsigned or) |
a4768d22 | 131 | { |
60902a2c | 132 | unsigned val = edma_read(ctlr, offset); |
a4768d22 | 133 | val |= or; |
60902a2c | 134 | edma_write(ctlr, offset, val); |
a4768d22 | 135 | } |
60902a2c | 136 | static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i) |
a4768d22 | 137 | { |
60902a2c | 138 | return edma_read(ctlr, offset + (i << 2)); |
a4768d22 | 139 | } |
60902a2c SR |
140 | static inline void edma_write_array(unsigned ctlr, int offset, int i, |
141 | unsigned val) | |
a4768d22 | 142 | { |
60902a2c | 143 | edma_write(ctlr, offset + (i << 2), val); |
a4768d22 | 144 | } |
60902a2c | 145 | static inline void edma_modify_array(unsigned ctlr, int offset, int i, |
a4768d22 KH |
146 | unsigned and, unsigned or) |
147 | { | |
60902a2c | 148 | edma_modify(ctlr, offset + (i << 2), and, or); |
a4768d22 | 149 | } |
60902a2c | 150 | static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or) |
a4768d22 | 151 | { |
60902a2c | 152 | edma_or(ctlr, offset + (i << 2), or); |
a4768d22 | 153 | } |
60902a2c SR |
154 | static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j, |
155 | unsigned or) | |
a4768d22 | 156 | { |
60902a2c | 157 | edma_or(ctlr, offset + ((i*2 + j) << 2), or); |
a4768d22 | 158 | } |
60902a2c SR |
159 | static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j, |
160 | unsigned val) | |
a4768d22 | 161 | { |
60902a2c | 162 | edma_write(ctlr, offset + ((i*2 + j) << 2), val); |
a4768d22 | 163 | } |
60902a2c | 164 | static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset) |
a4768d22 | 165 | { |
60902a2c | 166 | return edma_read(ctlr, EDMA_SHADOW0 + offset); |
a4768d22 | 167 | } |
60902a2c SR |
168 | static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset, |
169 | int i) | |
a4768d22 | 170 | { |
60902a2c | 171 | return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2)); |
a4768d22 | 172 | } |
60902a2c | 173 | static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val) |
a4768d22 | 174 | { |
60902a2c | 175 | edma_write(ctlr, EDMA_SHADOW0 + offset, val); |
a4768d22 | 176 | } |
60902a2c SR |
177 | static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i, |
178 | unsigned val) | |
a4768d22 | 179 | { |
60902a2c | 180 | edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val); |
a4768d22 | 181 | } |
60902a2c SR |
182 | static inline unsigned int edma_parm_read(unsigned ctlr, int offset, |
183 | int param_no) | |
a4768d22 | 184 | { |
60902a2c | 185 | return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5)); |
a4768d22 | 186 | } |
60902a2c SR |
187 | static inline void edma_parm_write(unsigned ctlr, int offset, int param_no, |
188 | unsigned val) | |
a4768d22 | 189 | { |
60902a2c | 190 | edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val); |
a4768d22 | 191 | } |
60902a2c | 192 | static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no, |
a4768d22 KH |
193 | unsigned and, unsigned or) |
194 | { | |
60902a2c | 195 | edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or); |
a4768d22 | 196 | } |
60902a2c SR |
197 | static inline void edma_parm_and(unsigned ctlr, int offset, int param_no, |
198 | unsigned and) | |
a4768d22 | 199 | { |
60902a2c | 200 | edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and); |
a4768d22 | 201 | } |
60902a2c SR |
202 | static inline void edma_parm_or(unsigned ctlr, int offset, int param_no, |
203 | unsigned or) | |
a4768d22 | 204 | { |
60902a2c | 205 | edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or); |
a4768d22 KH |
206 | } |
207 | ||
90bd4e6d RS |
208 | static inline void set_bits(int offset, int len, unsigned long *p) |
209 | { | |
210 | for (; len > 0; len--) | |
211 | set_bit(offset + (len - 1), p); | |
212 | } | |
213 | ||
214 | static inline void clear_bits(int offset, int len, unsigned long *p) | |
215 | { | |
216 | for (; len > 0; len--) | |
217 | clear_bit(offset + (len - 1), p); | |
218 | } | |
219 | ||
a4768d22 KH |
220 | /*****************************************************************************/ |
221 | ||
222 | /* actual number of DMA channels and slots on this silicon */ | |
60902a2c SR |
223 | struct edma { |
224 | /* how many dma resources of each type */ | |
225 | unsigned num_channels; | |
226 | unsigned num_region; | |
227 | unsigned num_slots; | |
228 | unsigned num_tc; | |
229 | unsigned num_cc; | |
a0f0202e | 230 | enum dma_event_q default_queue; |
60902a2c SR |
231 | |
232 | /* list of channels with no even trigger; terminated by "-1" */ | |
233 | const s8 *noevent; | |
234 | ||
235 | /* The edma_inuse bit for each PaRAM slot is clear unless the | |
236 | * channel is in use ... by ARM or DSP, for QDMA, or whatever. | |
237 | */ | |
238 | DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY); | |
a4768d22 | 239 | |
f900d552 SR |
240 | /* The edma_unused bit for each channel is clear unless |
241 | * it is not being used on this platform. It uses a bit | |
242 | * of SOC-specific initialization code. | |
60902a2c | 243 | */ |
f900d552 | 244 | DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH); |
a4768d22 | 245 | |
60902a2c SR |
246 | unsigned irq_res_start; |
247 | unsigned irq_res_end; | |
a4768d22 | 248 | |
60902a2c SR |
249 | struct dma_interrupt_data { |
250 | void (*callback)(unsigned channel, unsigned short ch_status, | |
251 | void *data); | |
252 | void *data; | |
253 | } intr_data[EDMA_MAX_DMACH]; | |
254 | }; | |
255 | ||
3f68b98a | 256 | static struct edma *edma_cc[EDMA_MAX_CC]; |
2d517508 | 257 | static int arch_num_cc; |
a4768d22 KH |
258 | |
259 | /* dummy param set used to (re)initialize parameter RAM slots */ | |
260 | static const struct edmacc_param dummy_paramset = { | |
261 | .link_bcntrld = 0xffff, | |
262 | .ccnt = 1, | |
263 | }; | |
264 | ||
a4768d22 KH |
265 | /*****************************************************************************/ |
266 | ||
60902a2c SR |
267 | static void map_dmach_queue(unsigned ctlr, unsigned ch_no, |
268 | enum dma_event_q queue_no) | |
a4768d22 KH |
269 | { |
270 | int bit = (ch_no & 0x7) * 4; | |
271 | ||
272 | /* default to low priority queue */ | |
273 | if (queue_no == EVENTQ_DEFAULT) | |
3f68b98a | 274 | queue_no = edma_cc[ctlr]->default_queue; |
a4768d22 KH |
275 | |
276 | queue_no &= 7; | |
60902a2c | 277 | edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3), |
a4768d22 KH |
278 | ~(0x7 << bit), queue_no << bit); |
279 | } | |
280 | ||
60902a2c | 281 | static void __init map_queue_tc(unsigned ctlr, int queue_no, int tc_no) |
a4768d22 KH |
282 | { |
283 | int bit = queue_no * 4; | |
60902a2c | 284 | edma_modify(ctlr, EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit)); |
a4768d22 KH |
285 | } |
286 | ||
60902a2c SR |
287 | static void __init assign_priority_to_queue(unsigned ctlr, int queue_no, |
288 | int priority) | |
a4768d22 KH |
289 | { |
290 | int bit = queue_no * 4; | |
60902a2c SR |
291 | edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit), |
292 | ((priority & 0x7) << bit)); | |
293 | } | |
294 | ||
295 | /** | |
296 | * map_dmach_param - Maps channel number to param entry number | |
297 | * | |
298 | * This maps the dma channel number to param entry numberter. In | |
299 | * other words using the DMA channel mapping registers a param entry | |
300 | * can be mapped to any channel | |
301 | * | |
302 | * Callers are responsible for ensuring the channel mapping logic is | |
303 | * included in that particular EDMA variant (Eg : dm646x) | |
304 | * | |
305 | */ | |
306 | static void __init map_dmach_param(unsigned ctlr) | |
307 | { | |
308 | int i; | |
309 | for (i = 0; i < EDMA_MAX_DMACH; i++) | |
310 | edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5)); | |
a4768d22 KH |
311 | } |
312 | ||
313 | static inline void | |
314 | setup_dma_interrupt(unsigned lch, | |
315 | void (*callback)(unsigned channel, u16 ch_status, void *data), | |
316 | void *data) | |
317 | { | |
60902a2c SR |
318 | unsigned ctlr; |
319 | ||
320 | ctlr = EDMA_CTLR(lch); | |
321 | lch = EDMA_CHAN_SLOT(lch); | |
322 | ||
243bc654 | 323 | if (!callback) |
60902a2c | 324 | edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5, |
d78a9494 | 325 | BIT(lch & 0x1f)); |
a4768d22 | 326 | |
3f68b98a SN |
327 | edma_cc[ctlr]->intr_data[lch].callback = callback; |
328 | edma_cc[ctlr]->intr_data[lch].data = data; | |
a4768d22 KH |
329 | |
330 | if (callback) { | |
60902a2c | 331 | edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5, |
d78a9494 | 332 | BIT(lch & 0x1f)); |
60902a2c | 333 | edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5, |
d78a9494 | 334 | BIT(lch & 0x1f)); |
a4768d22 KH |
335 | } |
336 | } | |
337 | ||
60902a2c SR |
338 | static int irq2ctlr(int irq) |
339 | { | |
3f68b98a | 340 | if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end) |
60902a2c | 341 | return 0; |
3f68b98a SN |
342 | else if (irq >= edma_cc[1]->irq_res_start && |
343 | irq <= edma_cc[1]->irq_res_end) | |
60902a2c SR |
344 | return 1; |
345 | ||
346 | return -1; | |
347 | } | |
348 | ||
a4768d22 KH |
349 | /****************************************************************************** |
350 | * | |
351 | * DMA interrupt handler | |
352 | * | |
353 | *****************************************************************************/ | |
354 | static irqreturn_t dma_irq_handler(int irq, void *data) | |
355 | { | |
356 | int i; | |
60902a2c | 357 | unsigned ctlr; |
a4768d22 KH |
358 | unsigned int cnt = 0; |
359 | ||
60902a2c SR |
360 | ctlr = irq2ctlr(irq); |
361 | ||
a4768d22 KH |
362 | dev_dbg(data, "dma_irq_handler\n"); |
363 | ||
a6374f53 SN |
364 | if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0) && |
365 | (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0)) | |
a4768d22 KH |
366 | return IRQ_NONE; |
367 | ||
368 | while (1) { | |
369 | int j; | |
a7e05065 AA |
370 | if (edma_shadow0_read_array(ctlr, SH_IPR, 0) & |
371 | edma_shadow0_read_array(ctlr, SH_IER, 0)) | |
a4768d22 | 372 | j = 0; |
a7e05065 AA |
373 | else if (edma_shadow0_read_array(ctlr, SH_IPR, 1) & |
374 | edma_shadow0_read_array(ctlr, SH_IER, 1)) | |
a4768d22 KH |
375 | j = 1; |
376 | else | |
377 | break; | |
378 | dev_dbg(data, "IPR%d %08x\n", j, | |
60902a2c | 379 | edma_shadow0_read_array(ctlr, SH_IPR, j)); |
a4768d22 KH |
380 | for (i = 0; i < 32; i++) { |
381 | int k = (j << 5) + i; | |
a7e05065 AA |
382 | if ((edma_shadow0_read_array(ctlr, SH_IPR, j) & BIT(i)) |
383 | && (edma_shadow0_read_array(ctlr, | |
384 | SH_IER, j) & BIT(i))) { | |
a4768d22 | 385 | /* Clear the corresponding IPR bits */ |
60902a2c | 386 | edma_shadow0_write_array(ctlr, SH_ICR, j, |
d78a9494 | 387 | BIT(i)); |
243bc654 | 388 | if (edma_cc[ctlr]->intr_data[k].callback) |
3f68b98a | 389 | edma_cc[ctlr]->intr_data[k].callback( |
60902a2c | 390 | k, DMA_COMPLETE, |
3f68b98a | 391 | edma_cc[ctlr]->intr_data[k]. |
60902a2c | 392 | data); |
a4768d22 KH |
393 | } |
394 | } | |
395 | cnt++; | |
396 | if (cnt > 10) | |
397 | break; | |
398 | } | |
60902a2c | 399 | edma_shadow0_write(ctlr, SH_IEVAL, 1); |
a4768d22 KH |
400 | return IRQ_HANDLED; |
401 | } | |
402 | ||
403 | /****************************************************************************** | |
404 | * | |
405 | * DMA error interrupt handler | |
406 | * | |
407 | *****************************************************************************/ | |
408 | static irqreturn_t dma_ccerr_handler(int irq, void *data) | |
409 | { | |
410 | int i; | |
60902a2c | 411 | unsigned ctlr; |
a4768d22 KH |
412 | unsigned int cnt = 0; |
413 | ||
60902a2c SR |
414 | ctlr = irq2ctlr(irq); |
415 | ||
a4768d22 KH |
416 | dev_dbg(data, "dma_ccerr_handler\n"); |
417 | ||
60902a2c SR |
418 | if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) && |
419 | (edma_read_array(ctlr, EDMA_EMR, 1) == 0) && | |
420 | (edma_read(ctlr, EDMA_QEMR) == 0) && | |
421 | (edma_read(ctlr, EDMA_CCERR) == 0)) | |
a4768d22 KH |
422 | return IRQ_NONE; |
423 | ||
424 | while (1) { | |
425 | int j = -1; | |
60902a2c | 426 | if (edma_read_array(ctlr, EDMA_EMR, 0)) |
a4768d22 | 427 | j = 0; |
60902a2c | 428 | else if (edma_read_array(ctlr, EDMA_EMR, 1)) |
a4768d22 KH |
429 | j = 1; |
430 | if (j >= 0) { | |
431 | dev_dbg(data, "EMR%d %08x\n", j, | |
60902a2c | 432 | edma_read_array(ctlr, EDMA_EMR, j)); |
a4768d22 KH |
433 | for (i = 0; i < 32; i++) { |
434 | int k = (j << 5) + i; | |
60902a2c | 435 | if (edma_read_array(ctlr, EDMA_EMR, j) & |
d78a9494 | 436 | BIT(i)) { |
a4768d22 | 437 | /* Clear the corresponding EMR bits */ |
60902a2c | 438 | edma_write_array(ctlr, EDMA_EMCR, j, |
d78a9494 | 439 | BIT(i)); |
a4768d22 | 440 | /* Clear any SER */ |
60902a2c | 441 | edma_shadow0_write_array(ctlr, SH_SECR, |
d78a9494 | 442 | j, BIT(i)); |
3f68b98a | 443 | if (edma_cc[ctlr]->intr_data[k]. |
60902a2c | 444 | callback) { |
3f68b98a | 445 | edma_cc[ctlr]->intr_data[k]. |
60902a2c SR |
446 | callback(k, |
447 | DMA_CC_ERROR, | |
3f68b98a | 448 | edma_cc[ctlr]->intr_data |
60902a2c | 449 | [k].data); |
a4768d22 KH |
450 | } |
451 | } | |
452 | } | |
60902a2c | 453 | } else if (edma_read(ctlr, EDMA_QEMR)) { |
a4768d22 | 454 | dev_dbg(data, "QEMR %02x\n", |
60902a2c | 455 | edma_read(ctlr, EDMA_QEMR)); |
a4768d22 | 456 | for (i = 0; i < 8; i++) { |
d78a9494 | 457 | if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) { |
a4768d22 | 458 | /* Clear the corresponding IPR bits */ |
d78a9494 | 459 | edma_write(ctlr, EDMA_QEMCR, BIT(i)); |
60902a2c | 460 | edma_shadow0_write(ctlr, SH_QSECR, |
d78a9494 | 461 | BIT(i)); |
a4768d22 KH |
462 | |
463 | /* NOTE: not reported!! */ | |
464 | } | |
465 | } | |
60902a2c | 466 | } else if (edma_read(ctlr, EDMA_CCERR)) { |
a4768d22 | 467 | dev_dbg(data, "CCERR %08x\n", |
60902a2c | 468 | edma_read(ctlr, EDMA_CCERR)); |
a4768d22 KH |
469 | /* FIXME: CCERR.BIT(16) ignored! much better |
470 | * to just write CCERRCLR with CCERR value... | |
471 | */ | |
472 | for (i = 0; i < 8; i++) { | |
d78a9494 | 473 | if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) { |
a4768d22 | 474 | /* Clear the corresponding IPR bits */ |
d78a9494 | 475 | edma_write(ctlr, EDMA_CCERRCLR, BIT(i)); |
a4768d22 KH |
476 | |
477 | /* NOTE: not reported!! */ | |
478 | } | |
479 | } | |
480 | } | |
a6374f53 SN |
481 | if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) && |
482 | (edma_read_array(ctlr, EDMA_EMR, 1) == 0) && | |
483 | (edma_read(ctlr, EDMA_QEMR) == 0) && | |
484 | (edma_read(ctlr, EDMA_CCERR) == 0)) | |
a4768d22 | 485 | break; |
a4768d22 KH |
486 | cnt++; |
487 | if (cnt > 10) | |
488 | break; | |
489 | } | |
60902a2c | 490 | edma_write(ctlr, EDMA_EEVAL, 1); |
a4768d22 KH |
491 | return IRQ_HANDLED; |
492 | } | |
493 | ||
494 | /****************************************************************************** | |
495 | * | |
496 | * Transfer controller error interrupt handlers | |
497 | * | |
498 | *****************************************************************************/ | |
499 | ||
500 | #define tc_errs_handled false /* disabled as long as they're NOPs */ | |
501 | ||
502 | static irqreturn_t dma_tc0err_handler(int irq, void *data) | |
503 | { | |
504 | dev_dbg(data, "dma_tc0err_handler\n"); | |
505 | return IRQ_HANDLED; | |
506 | } | |
507 | ||
508 | static irqreturn_t dma_tc1err_handler(int irq, void *data) | |
509 | { | |
510 | dev_dbg(data, "dma_tc1err_handler\n"); | |
511 | return IRQ_HANDLED; | |
512 | } | |
513 | ||
134ce221 SP |
514 | static int reserve_contiguous_slots(int ctlr, unsigned int id, |
515 | unsigned int num_slots, | |
516 | unsigned int start_slot) | |
213765d7 SP |
517 | { |
518 | int i, j; | |
134ce221 SP |
519 | unsigned int count = num_slots; |
520 | int stop_slot = start_slot; | |
cc93fc3f | 521 | DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY); |
213765d7 | 522 | |
3f68b98a | 523 | for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) { |
213765d7 | 524 | j = EDMA_CHAN_SLOT(i); |
3f68b98a | 525 | if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) { |
cc93fc3f | 526 | /* Record our current beginning slot */ |
134ce221 SP |
527 | if (count == num_slots) |
528 | stop_slot = i; | |
cc93fc3f | 529 | |
213765d7 | 530 | count--; |
cc93fc3f SP |
531 | set_bit(j, tmp_inuse); |
532 | ||
213765d7 SP |
533 | if (count == 0) |
534 | break; | |
cc93fc3f SP |
535 | } else { |
536 | clear_bit(j, tmp_inuse); | |
537 | ||
538 | if (id == EDMA_CONT_PARAMS_FIXED_EXACT) { | |
134ce221 | 539 | stop_slot = i; |
cc93fc3f | 540 | break; |
243bc654 | 541 | } else { |
134ce221 | 542 | count = num_slots; |
243bc654 | 543 | } |
cc93fc3f | 544 | } |
213765d7 SP |
545 | } |
546 | ||
547 | /* | |
548 | * We have to clear any bits that we set | |
134ce221 SP |
549 | * if we run out parameter RAM slots, i.e we do find a set |
550 | * of contiguous parameter RAM slots but do not find the exact number | |
551 | * requested as we may reach the total number of parameter RAM slots | |
213765d7 | 552 | */ |
3f68b98a | 553 | if (i == edma_cc[ctlr]->num_slots) |
134ce221 | 554 | stop_slot = i; |
cc93fc3f | 555 | |
134ce221 | 556 | for (j = start_slot; j < stop_slot; j++) |
cc93fc3f | 557 | if (test_bit(j, tmp_inuse)) |
3f68b98a | 558 | clear_bit(j, edma_cc[ctlr]->edma_inuse); |
213765d7 | 559 | |
cc93fc3f | 560 | if (count) |
213765d7 | 561 | return -EBUSY; |
213765d7 | 562 | |
134ce221 | 563 | for (j = i - num_slots + 1; j <= i; ++j) |
213765d7 SP |
564 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j), |
565 | &dummy_paramset, PARM_SIZE); | |
566 | ||
134ce221 | 567 | return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1); |
213765d7 SP |
568 | } |
569 | ||
f900d552 SR |
570 | static int prepare_unused_channel_list(struct device *dev, void *data) |
571 | { | |
572 | struct platform_device *pdev = to_platform_device(dev); | |
573 | int i, ctlr; | |
574 | ||
575 | for (i = 0; i < pdev->num_resources; i++) { | |
576 | if ((pdev->resource[i].flags & IORESOURCE_DMA) && | |
577 | (int)pdev->resource[i].start >= 0) { | |
578 | ctlr = EDMA_CTLR(pdev->resource[i].start); | |
579 | clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start), | |
3f68b98a | 580 | edma_cc[ctlr]->edma_unused); |
f900d552 SR |
581 | } |
582 | } | |
583 | ||
584 | return 0; | |
585 | } | |
586 | ||
a4768d22 KH |
587 | /*-----------------------------------------------------------------------*/ |
588 | ||
f900d552 SR |
589 | static bool unused_chan_list_done; |
590 | ||
a4768d22 KH |
591 | /* Resource alloc/free: dma channels, parameter RAM slots */ |
592 | ||
593 | /** | |
594 | * edma_alloc_channel - allocate DMA channel and paired parameter RAM | |
595 | * @channel: specific channel to allocate; negative for "any unmapped channel" | |
596 | * @callback: optional; to be issued on DMA completion or errors | |
597 | * @data: passed to callback | |
598 | * @eventq_no: an EVENTQ_* constant, used to choose which Transfer | |
599 | * Controller (TC) executes requests using this channel. Use | |
600 | * EVENTQ_DEFAULT unless you really need a high priority queue. | |
601 | * | |
602 | * This allocates a DMA channel and its associated parameter RAM slot. | |
603 | * The parameter RAM is initialized to hold a dummy transfer. | |
604 | * | |
605 | * Normal use is to pass a specific channel number as @channel, to make | |
606 | * use of hardware events mapped to that channel. When the channel will | |
607 | * be used only for software triggering or event chaining, channels not | |
608 | * mapped to hardware events (or mapped to unused events) are preferable. | |
609 | * | |
610 | * DMA transfers start from a channel using edma_start(), or by | |
611 | * chaining. When the transfer described in that channel's parameter RAM | |
612 | * slot completes, that slot's data may be reloaded through a link. | |
613 | * | |
614 | * DMA errors are only reported to the @callback associated with the | |
615 | * channel driving that transfer, but transfer completion callbacks can | |
616 | * be sent to another channel under control of the TCC field in | |
617 | * the option word of the transfer's parameter RAM set. Drivers must not | |
618 | * use DMA transfer completion callbacks for channels they did not allocate. | |
619 | * (The same applies to TCC codes used in transfer chaining.) | |
620 | * | |
621 | * Returns the number of the channel, else negative errno. | |
622 | */ | |
623 | int edma_alloc_channel(int channel, | |
624 | void (*callback)(unsigned channel, u16 ch_status, void *data), | |
625 | void *data, | |
626 | enum dma_event_q eventq_no) | |
627 | { | |
447f18f1 | 628 | unsigned i, done = 0, ctlr = 0; |
f900d552 SR |
629 | int ret = 0; |
630 | ||
631 | if (!unused_chan_list_done) { | |
632 | /* | |
633 | * Scan all the platform devices to find out the EDMA channels | |
634 | * used and clear them in the unused list, making the rest | |
635 | * available for ARM usage. | |
636 | */ | |
637 | ret = bus_for_each_dev(&platform_bus_type, NULL, NULL, | |
638 | prepare_unused_channel_list); | |
639 | if (ret < 0) | |
640 | return ret; | |
641 | ||
642 | unused_chan_list_done = true; | |
643 | } | |
60902a2c SR |
644 | |
645 | if (channel >= 0) { | |
646 | ctlr = EDMA_CTLR(channel); | |
647 | channel = EDMA_CHAN_SLOT(channel); | |
648 | } | |
649 | ||
a4768d22 | 650 | if (channel < 0) { |
2d517508 | 651 | for (i = 0; i < arch_num_cc; i++) { |
60902a2c SR |
652 | channel = 0; |
653 | for (;;) { | |
3f68b98a SN |
654 | channel = find_next_bit(edma_cc[i]->edma_unused, |
655 | edma_cc[i]->num_channels, | |
60902a2c | 656 | channel); |
3f68b98a | 657 | if (channel == edma_cc[i]->num_channels) |
447f18f1 | 658 | break; |
60902a2c | 659 | if (!test_and_set_bit(channel, |
3f68b98a | 660 | edma_cc[i]->edma_inuse)) { |
60902a2c SR |
661 | done = 1; |
662 | ctlr = i; | |
663 | break; | |
664 | } | |
665 | channel++; | |
666 | } | |
667 | if (done) | |
a4768d22 | 668 | break; |
a4768d22 | 669 | } |
447f18f1 SR |
670 | if (!done) |
671 | return -ENOMEM; | |
3f68b98a | 672 | } else if (channel >= edma_cc[ctlr]->num_channels) { |
a4768d22 | 673 | return -EINVAL; |
3f68b98a | 674 | } else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) { |
a4768d22 KH |
675 | return -EBUSY; |
676 | } | |
677 | ||
678 | /* ensure access through shadow region 0 */ | |
d78a9494 | 679 | edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f)); |
a4768d22 KH |
680 | |
681 | /* ensure no events are pending */ | |
60902a2c SR |
682 | edma_stop(EDMA_CTLR_CHAN(ctlr, channel)); |
683 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel), | |
a4768d22 KH |
684 | &dummy_paramset, PARM_SIZE); |
685 | ||
686 | if (callback) | |
60902a2c SR |
687 | setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel), |
688 | callback, data); | |
a4768d22 | 689 | |
60902a2c | 690 | map_dmach_queue(ctlr, channel, eventq_no); |
a4768d22 | 691 | |
0e6cb8d2 | 692 | return EDMA_CTLR_CHAN(ctlr, channel); |
a4768d22 KH |
693 | } |
694 | EXPORT_SYMBOL(edma_alloc_channel); | |
695 | ||
696 | ||
697 | /** | |
698 | * edma_free_channel - deallocate DMA channel | |
699 | * @channel: dma channel returned from edma_alloc_channel() | |
700 | * | |
701 | * This deallocates the DMA channel and associated parameter RAM slot | |
702 | * allocated by edma_alloc_channel(). | |
703 | * | |
704 | * Callers are responsible for ensuring the channel is inactive, and | |
705 | * will not be reactivated by linking, chaining, or software calls to | |
706 | * edma_start(). | |
707 | */ | |
708 | void edma_free_channel(unsigned channel) | |
709 | { | |
60902a2c SR |
710 | unsigned ctlr; |
711 | ||
712 | ctlr = EDMA_CTLR(channel); | |
713 | channel = EDMA_CHAN_SLOT(channel); | |
714 | ||
3f68b98a | 715 | if (channel >= edma_cc[ctlr]->num_channels) |
a4768d22 KH |
716 | return; |
717 | ||
718 | setup_dma_interrupt(channel, NULL, NULL); | |
719 | /* REVISIT should probably take out of shadow region 0 */ | |
720 | ||
60902a2c | 721 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel), |
a4768d22 | 722 | &dummy_paramset, PARM_SIZE); |
3f68b98a | 723 | clear_bit(channel, edma_cc[ctlr]->edma_inuse); |
a4768d22 KH |
724 | } |
725 | EXPORT_SYMBOL(edma_free_channel); | |
726 | ||
727 | /** | |
728 | * edma_alloc_slot - allocate DMA parameter RAM | |
729 | * @slot: specific slot to allocate; negative for "any unused slot" | |
730 | * | |
731 | * This allocates a parameter RAM slot, initializing it to hold a | |
732 | * dummy transfer. Slots allocated using this routine have not been | |
733 | * mapped to a hardware DMA channel, and will normally be used by | |
734 | * linking to them from a slot associated with a DMA channel. | |
735 | * | |
736 | * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific | |
737 | * slots may be allocated on behalf of DSP firmware. | |
738 | * | |
739 | * Returns the number of the slot, else negative errno. | |
740 | */ | |
60902a2c | 741 | int edma_alloc_slot(unsigned ctlr, int slot) |
a4768d22 | 742 | { |
60902a2c SR |
743 | if (slot >= 0) |
744 | slot = EDMA_CHAN_SLOT(slot); | |
745 | ||
a4768d22 | 746 | if (slot < 0) { |
3f68b98a | 747 | slot = edma_cc[ctlr]->num_channels; |
a4768d22 | 748 | for (;;) { |
3f68b98a SN |
749 | slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse, |
750 | edma_cc[ctlr]->num_slots, slot); | |
751 | if (slot == edma_cc[ctlr]->num_slots) | |
a4768d22 | 752 | return -ENOMEM; |
3f68b98a | 753 | if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) |
a4768d22 KH |
754 | break; |
755 | } | |
3f68b98a SN |
756 | } else if (slot < edma_cc[ctlr]->num_channels || |
757 | slot >= edma_cc[ctlr]->num_slots) { | |
a4768d22 | 758 | return -EINVAL; |
3f68b98a | 759 | } else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) { |
a4768d22 KH |
760 | return -EBUSY; |
761 | } | |
762 | ||
60902a2c | 763 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), |
a4768d22 KH |
764 | &dummy_paramset, PARM_SIZE); |
765 | ||
60902a2c | 766 | return EDMA_CTLR_CHAN(ctlr, slot); |
a4768d22 KH |
767 | } |
768 | EXPORT_SYMBOL(edma_alloc_slot); | |
769 | ||
770 | /** | |
771 | * edma_free_slot - deallocate DMA parameter RAM | |
772 | * @slot: parameter RAM slot returned from edma_alloc_slot() | |
773 | * | |
774 | * This deallocates the parameter RAM slot allocated by edma_alloc_slot(). | |
775 | * Callers are responsible for ensuring the slot is inactive, and will | |
776 | * not be activated. | |
777 | */ | |
778 | void edma_free_slot(unsigned slot) | |
779 | { | |
60902a2c SR |
780 | unsigned ctlr; |
781 | ||
782 | ctlr = EDMA_CTLR(slot); | |
783 | slot = EDMA_CHAN_SLOT(slot); | |
784 | ||
3f68b98a SN |
785 | if (slot < edma_cc[ctlr]->num_channels || |
786 | slot >= edma_cc[ctlr]->num_slots) | |
a4768d22 KH |
787 | return; |
788 | ||
60902a2c | 789 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), |
a4768d22 | 790 | &dummy_paramset, PARM_SIZE); |
3f68b98a | 791 | clear_bit(slot, edma_cc[ctlr]->edma_inuse); |
a4768d22 KH |
792 | } |
793 | EXPORT_SYMBOL(edma_free_slot); | |
794 | ||
213765d7 SP |
795 | |
796 | /** | |
797 | * edma_alloc_cont_slots- alloc contiguous parameter RAM slots | |
798 | * The API will return the starting point of a set of | |
134ce221 | 799 | * contiguous parameter RAM slots that have been requested |
213765d7 SP |
800 | * |
801 | * @id: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT | |
802 | * or EDMA_CONT_PARAMS_FIXED_NOT_EXACT | |
134ce221 SP |
803 | * @count: number of contiguous Paramter RAM slots |
804 | * @slot - the start value of Parameter RAM slot that should be passed if id | |
213765d7 SP |
805 | * is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT |
806 | * | |
807 | * If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of | |
134ce221 SP |
808 | * contiguous Parameter RAM slots from parameter RAM 64 in the case of |
809 | * DaVinci SOCs and 32 in the case of DA8xx SOCs. | |
213765d7 SP |
810 | * |
811 | * If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a | |
134ce221 | 812 | * set of contiguous parameter RAM slots from the "slot" that is passed as an |
213765d7 SP |
813 | * argument to the API. |
814 | * | |
815 | * If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries | |
134ce221 | 816 | * starts looking for a set of contiguous parameter RAMs from the "slot" |
213765d7 | 817 | * that is passed as an argument to the API. On failure the API will try to |
134ce221 SP |
818 | * find a set of contiguous Parameter RAM slots from the remaining Parameter |
819 | * RAM slots | |
213765d7 SP |
820 | */ |
821 | int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count) | |
822 | { | |
823 | /* | |
824 | * The start slot requested should be greater than | |
825 | * the number of channels and lesser than the total number | |
826 | * of slots | |
827 | */ | |
6b0cf4e9 | 828 | if ((id != EDMA_CONT_PARAMS_ANY) && |
3f68b98a SN |
829 | (slot < edma_cc[ctlr]->num_channels || |
830 | slot >= edma_cc[ctlr]->num_slots)) | |
213765d7 SP |
831 | return -EINVAL; |
832 | ||
833 | /* | |
134ce221 | 834 | * The number of parameter RAM slots requested cannot be less than 1 |
213765d7 SP |
835 | * and cannot be more than the number of slots minus the number of |
836 | * channels | |
837 | */ | |
838 | if (count < 1 || count > | |
3f68b98a | 839 | (edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels)) |
213765d7 SP |
840 | return -EINVAL; |
841 | ||
842 | switch (id) { | |
843 | case EDMA_CONT_PARAMS_ANY: | |
134ce221 | 844 | return reserve_contiguous_slots(ctlr, id, count, |
3f68b98a | 845 | edma_cc[ctlr]->num_channels); |
213765d7 SP |
846 | case EDMA_CONT_PARAMS_FIXED_EXACT: |
847 | case EDMA_CONT_PARAMS_FIXED_NOT_EXACT: | |
134ce221 | 848 | return reserve_contiguous_slots(ctlr, id, count, slot); |
213765d7 SP |
849 | default: |
850 | return -EINVAL; | |
851 | } | |
852 | ||
853 | } | |
854 | EXPORT_SYMBOL(edma_alloc_cont_slots); | |
855 | ||
856 | /** | |
134ce221 SP |
857 | * edma_free_cont_slots - deallocate DMA parameter RAM slots |
858 | * @slot: first parameter RAM of a set of parameter RAM slots to be freed | |
859 | * @count: the number of contiguous parameter RAM slots to be freed | |
213765d7 SP |
860 | * |
861 | * This deallocates the parameter RAM slots allocated by | |
862 | * edma_alloc_cont_slots. | |
863 | * Callers/applications need to keep track of sets of contiguous | |
134ce221 | 864 | * parameter RAM slots that have been allocated using the edma_alloc_cont_slots |
213765d7 SP |
865 | * API. |
866 | * Callers are responsible for ensuring the slots are inactive, and will | |
867 | * not be activated. | |
868 | */ | |
869 | int edma_free_cont_slots(unsigned slot, int count) | |
870 | { | |
51c99e04 | 871 | unsigned ctlr, slot_to_free; |
213765d7 SP |
872 | int i; |
873 | ||
874 | ctlr = EDMA_CTLR(slot); | |
875 | slot = EDMA_CHAN_SLOT(slot); | |
876 | ||
3f68b98a SN |
877 | if (slot < edma_cc[ctlr]->num_channels || |
878 | slot >= edma_cc[ctlr]->num_slots || | |
213765d7 SP |
879 | count < 1) |
880 | return -EINVAL; | |
881 | ||
882 | for (i = slot; i < slot + count; ++i) { | |
883 | ctlr = EDMA_CTLR(i); | |
51c99e04 | 884 | slot_to_free = EDMA_CHAN_SLOT(i); |
213765d7 | 885 | |
51c99e04 | 886 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free), |
213765d7 | 887 | &dummy_paramset, PARM_SIZE); |
3f68b98a | 888 | clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse); |
213765d7 SP |
889 | } |
890 | ||
891 | return 0; | |
892 | } | |
893 | EXPORT_SYMBOL(edma_free_cont_slots); | |
894 | ||
a4768d22 KH |
895 | /*-----------------------------------------------------------------------*/ |
896 | ||
897 | /* Parameter RAM operations (i) -- read/write partial slots */ | |
898 | ||
899 | /** | |
900 | * edma_set_src - set initial DMA source address in parameter RAM slot | |
901 | * @slot: parameter RAM slot being configured | |
902 | * @src_port: physical address of source (memory, controller FIFO, etc) | |
903 | * @addressMode: INCR, except in very rare cases | |
904 | * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the | |
905 | * width to use when addressing the fifo (e.g. W8BIT, W32BIT) | |
906 | * | |
907 | * Note that the source address is modified during the DMA transfer | |
908 | * according to edma_set_src_index(). | |
909 | */ | |
910 | void edma_set_src(unsigned slot, dma_addr_t src_port, | |
911 | enum address_mode mode, enum fifo_width width) | |
912 | { | |
60902a2c SR |
913 | unsigned ctlr; |
914 | ||
915 | ctlr = EDMA_CTLR(slot); | |
916 | slot = EDMA_CHAN_SLOT(slot); | |
917 | ||
3f68b98a | 918 | if (slot < edma_cc[ctlr]->num_slots) { |
60902a2c | 919 | unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); |
a4768d22 KH |
920 | |
921 | if (mode) { | |
922 | /* set SAM and program FWID */ | |
923 | i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8)); | |
924 | } else { | |
925 | /* clear SAM */ | |
926 | i &= ~SAM; | |
927 | } | |
60902a2c | 928 | edma_parm_write(ctlr, PARM_OPT, slot, i); |
a4768d22 KH |
929 | |
930 | /* set the source port address | |
931 | in source register of param structure */ | |
60902a2c | 932 | edma_parm_write(ctlr, PARM_SRC, slot, src_port); |
a4768d22 KH |
933 | } |
934 | } | |
935 | EXPORT_SYMBOL(edma_set_src); | |
936 | ||
937 | /** | |
938 | * edma_set_dest - set initial DMA destination address in parameter RAM slot | |
939 | * @slot: parameter RAM slot being configured | |
940 | * @dest_port: physical address of destination (memory, controller FIFO, etc) | |
941 | * @addressMode: INCR, except in very rare cases | |
942 | * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the | |
943 | * width to use when addressing the fifo (e.g. W8BIT, W32BIT) | |
944 | * | |
945 | * Note that the destination address is modified during the DMA transfer | |
946 | * according to edma_set_dest_index(). | |
947 | */ | |
948 | void edma_set_dest(unsigned slot, dma_addr_t dest_port, | |
949 | enum address_mode mode, enum fifo_width width) | |
950 | { | |
60902a2c SR |
951 | unsigned ctlr; |
952 | ||
953 | ctlr = EDMA_CTLR(slot); | |
954 | slot = EDMA_CHAN_SLOT(slot); | |
955 | ||
3f68b98a | 956 | if (slot < edma_cc[ctlr]->num_slots) { |
60902a2c | 957 | unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); |
a4768d22 KH |
958 | |
959 | if (mode) { | |
960 | /* set DAM and program FWID */ | |
961 | i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8)); | |
962 | } else { | |
963 | /* clear DAM */ | |
964 | i &= ~DAM; | |
965 | } | |
60902a2c | 966 | edma_parm_write(ctlr, PARM_OPT, slot, i); |
a4768d22 KH |
967 | /* set the destination port address |
968 | in dest register of param structure */ | |
60902a2c | 969 | edma_parm_write(ctlr, PARM_DST, slot, dest_port); |
a4768d22 KH |
970 | } |
971 | } | |
972 | EXPORT_SYMBOL(edma_set_dest); | |
973 | ||
974 | /** | |
975 | * edma_get_position - returns the current transfer points | |
976 | * @slot: parameter RAM slot being examined | |
977 | * @src: pointer to source port position | |
978 | * @dst: pointer to destination port position | |
979 | * | |
980 | * Returns current source and destination addresses for a particular | |
981 | * parameter RAM slot. Its channel should not be active when this is called. | |
982 | */ | |
983 | void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst) | |
984 | { | |
985 | struct edmacc_param temp; | |
60902a2c SR |
986 | unsigned ctlr; |
987 | ||
988 | ctlr = EDMA_CTLR(slot); | |
989 | slot = EDMA_CHAN_SLOT(slot); | |
a4768d22 | 990 | |
60902a2c | 991 | edma_read_slot(EDMA_CTLR_CHAN(ctlr, slot), &temp); |
a4768d22 KH |
992 | if (src != NULL) |
993 | *src = temp.src; | |
994 | if (dst != NULL) | |
995 | *dst = temp.dst; | |
996 | } | |
997 | EXPORT_SYMBOL(edma_get_position); | |
998 | ||
999 | /** | |
1000 | * edma_set_src_index - configure DMA source address indexing | |
1001 | * @slot: parameter RAM slot being configured | |
1002 | * @src_bidx: byte offset between source arrays in a frame | |
1003 | * @src_cidx: byte offset between source frames in a block | |
1004 | * | |
1005 | * Offsets are specified to support either contiguous or discontiguous | |
1006 | * memory transfers, or repeated access to a hardware register, as needed. | |
1007 | * When accessing hardware registers, both offsets are normally zero. | |
1008 | */ | |
1009 | void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx) | |
1010 | { | |
60902a2c SR |
1011 | unsigned ctlr; |
1012 | ||
1013 | ctlr = EDMA_CTLR(slot); | |
1014 | slot = EDMA_CHAN_SLOT(slot); | |
1015 | ||
3f68b98a | 1016 | if (slot < edma_cc[ctlr]->num_slots) { |
60902a2c | 1017 | edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, |
a4768d22 | 1018 | 0xffff0000, src_bidx); |
60902a2c | 1019 | edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, |
a4768d22 KH |
1020 | 0xffff0000, src_cidx); |
1021 | } | |
1022 | } | |
1023 | EXPORT_SYMBOL(edma_set_src_index); | |
1024 | ||
1025 | /** | |
1026 | * edma_set_dest_index - configure DMA destination address indexing | |
1027 | * @slot: parameter RAM slot being configured | |
1028 | * @dest_bidx: byte offset between destination arrays in a frame | |
1029 | * @dest_cidx: byte offset between destination frames in a block | |
1030 | * | |
1031 | * Offsets are specified to support either contiguous or discontiguous | |
1032 | * memory transfers, or repeated access to a hardware register, as needed. | |
1033 | * When accessing hardware registers, both offsets are normally zero. | |
1034 | */ | |
1035 | void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx) | |
1036 | { | |
60902a2c SR |
1037 | unsigned ctlr; |
1038 | ||
1039 | ctlr = EDMA_CTLR(slot); | |
1040 | slot = EDMA_CHAN_SLOT(slot); | |
1041 | ||
3f68b98a | 1042 | if (slot < edma_cc[ctlr]->num_slots) { |
60902a2c | 1043 | edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, |
a4768d22 | 1044 | 0x0000ffff, dest_bidx << 16); |
60902a2c | 1045 | edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, |
a4768d22 KH |
1046 | 0x0000ffff, dest_cidx << 16); |
1047 | } | |
1048 | } | |
1049 | EXPORT_SYMBOL(edma_set_dest_index); | |
1050 | ||
1051 | /** | |
1052 | * edma_set_transfer_params - configure DMA transfer parameters | |
1053 | * @slot: parameter RAM slot being configured | |
1054 | * @acnt: how many bytes per array (at least one) | |
1055 | * @bcnt: how many arrays per frame (at least one) | |
1056 | * @ccnt: how many frames per block (at least one) | |
1057 | * @bcnt_rld: used only for A-Synchronized transfers; this specifies | |
1058 | * the value to reload into bcnt when it decrements to zero | |
1059 | * @sync_mode: ASYNC or ABSYNC | |
1060 | * | |
1061 | * See the EDMA3 documentation to understand how to configure and link | |
1062 | * transfers using the fields in PaRAM slots. If you are not doing it | |
1063 | * all at once with edma_write_slot(), you will use this routine | |
1064 | * plus two calls each for source and destination, setting the initial | |
1065 | * address and saying how to index that address. | |
1066 | * | |
1067 | * An example of an A-Synchronized transfer is a serial link using a | |
1068 | * single word shift register. In that case, @acnt would be equal to | |
1069 | * that word size; the serial controller issues a DMA synchronization | |
1070 | * event to transfer each word, and memory access by the DMA transfer | |
1071 | * controller will be word-at-a-time. | |
1072 | * | |
1073 | * An example of an AB-Synchronized transfer is a device using a FIFO. | |
1074 | * In that case, @acnt equals the FIFO width and @bcnt equals its depth. | |
1075 | * The controller with the FIFO issues DMA synchronization events when | |
1076 | * the FIFO threshold is reached, and the DMA transfer controller will | |
1077 | * transfer one frame to (or from) the FIFO. It will probably use | |
1078 | * efficient burst modes to access memory. | |
1079 | */ | |
1080 | void edma_set_transfer_params(unsigned slot, | |
1081 | u16 acnt, u16 bcnt, u16 ccnt, | |
1082 | u16 bcnt_rld, enum sync_dimension sync_mode) | |
1083 | { | |
60902a2c SR |
1084 | unsigned ctlr; |
1085 | ||
1086 | ctlr = EDMA_CTLR(slot); | |
1087 | slot = EDMA_CHAN_SLOT(slot); | |
1088 | ||
3f68b98a | 1089 | if (slot < edma_cc[ctlr]->num_slots) { |
60902a2c | 1090 | edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot, |
a4768d22 KH |
1091 | 0x0000ffff, bcnt_rld << 16); |
1092 | if (sync_mode == ASYNC) | |
60902a2c | 1093 | edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM); |
a4768d22 | 1094 | else |
60902a2c | 1095 | edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM); |
a4768d22 | 1096 | /* Set the acount, bcount, ccount registers */ |
60902a2c SR |
1097 | edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt); |
1098 | edma_parm_write(ctlr, PARM_CCNT, slot, ccnt); | |
a4768d22 KH |
1099 | } |
1100 | } | |
1101 | EXPORT_SYMBOL(edma_set_transfer_params); | |
1102 | ||
1103 | /** | |
1104 | * edma_link - link one parameter RAM slot to another | |
1105 | * @from: parameter RAM slot originating the link | |
1106 | * @to: parameter RAM slot which is the link target | |
1107 | * | |
1108 | * The originating slot should not be part of any active DMA transfer. | |
1109 | */ | |
1110 | void edma_link(unsigned from, unsigned to) | |
1111 | { | |
60902a2c SR |
1112 | unsigned ctlr_from, ctlr_to; |
1113 | ||
1114 | ctlr_from = EDMA_CTLR(from); | |
1115 | from = EDMA_CHAN_SLOT(from); | |
1116 | ctlr_to = EDMA_CTLR(to); | |
1117 | to = EDMA_CHAN_SLOT(to); | |
1118 | ||
3f68b98a | 1119 | if (from >= edma_cc[ctlr_from]->num_slots) |
a4768d22 | 1120 | return; |
3f68b98a | 1121 | if (to >= edma_cc[ctlr_to]->num_slots) |
a4768d22 | 1122 | return; |
60902a2c SR |
1123 | edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000, |
1124 | PARM_OFFSET(to)); | |
a4768d22 KH |
1125 | } |
1126 | EXPORT_SYMBOL(edma_link); | |
1127 | ||
1128 | /** | |
1129 | * edma_unlink - cut link from one parameter RAM slot | |
1130 | * @from: parameter RAM slot originating the link | |
1131 | * | |
1132 | * The originating slot should not be part of any active DMA transfer. | |
1133 | * Its link is set to 0xffff. | |
1134 | */ | |
1135 | void edma_unlink(unsigned from) | |
1136 | { | |
60902a2c SR |
1137 | unsigned ctlr; |
1138 | ||
1139 | ctlr = EDMA_CTLR(from); | |
1140 | from = EDMA_CHAN_SLOT(from); | |
1141 | ||
3f68b98a | 1142 | if (from >= edma_cc[ctlr]->num_slots) |
a4768d22 | 1143 | return; |
60902a2c | 1144 | edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff); |
a4768d22 KH |
1145 | } |
1146 | EXPORT_SYMBOL(edma_unlink); | |
1147 | ||
1148 | /*-----------------------------------------------------------------------*/ | |
1149 | ||
1150 | /* Parameter RAM operations (ii) -- read/write whole parameter sets */ | |
1151 | ||
1152 | /** | |
1153 | * edma_write_slot - write parameter RAM data for slot | |
1154 | * @slot: number of parameter RAM slot being modified | |
1155 | * @param: data to be written into parameter RAM slot | |
1156 | * | |
1157 | * Use this to assign all parameters of a transfer at once. This | |
1158 | * allows more efficient setup of transfers than issuing multiple | |
1159 | * calls to set up those parameters in small pieces, and provides | |
1160 | * complete control over all transfer options. | |
1161 | */ | |
1162 | void edma_write_slot(unsigned slot, const struct edmacc_param *param) | |
1163 | { | |
60902a2c SR |
1164 | unsigned ctlr; |
1165 | ||
1166 | ctlr = EDMA_CTLR(slot); | |
1167 | slot = EDMA_CHAN_SLOT(slot); | |
1168 | ||
3f68b98a | 1169 | if (slot >= edma_cc[ctlr]->num_slots) |
a4768d22 | 1170 | return; |
60902a2c SR |
1171 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param, |
1172 | PARM_SIZE); | |
a4768d22 KH |
1173 | } |
1174 | EXPORT_SYMBOL(edma_write_slot); | |
1175 | ||
1176 | /** | |
1177 | * edma_read_slot - read parameter RAM data from slot | |
1178 | * @slot: number of parameter RAM slot being copied | |
1179 | * @param: where to store copy of parameter RAM data | |
1180 | * | |
1181 | * Use this to read data from a parameter RAM slot, perhaps to | |
1182 | * save them as a template for later reuse. | |
1183 | */ | |
1184 | void edma_read_slot(unsigned slot, struct edmacc_param *param) | |
1185 | { | |
60902a2c SR |
1186 | unsigned ctlr; |
1187 | ||
1188 | ctlr = EDMA_CTLR(slot); | |
1189 | slot = EDMA_CHAN_SLOT(slot); | |
1190 | ||
3f68b98a | 1191 | if (slot >= edma_cc[ctlr]->num_slots) |
a4768d22 | 1192 | return; |
60902a2c SR |
1193 | memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot), |
1194 | PARM_SIZE); | |
a4768d22 KH |
1195 | } |
1196 | EXPORT_SYMBOL(edma_read_slot); | |
1197 | ||
1198 | /*-----------------------------------------------------------------------*/ | |
1199 | ||
1200 | /* Various EDMA channel control operations */ | |
1201 | ||
1202 | /** | |
1203 | * edma_pause - pause dma on a channel | |
1204 | * @channel: on which edma_start() has been called | |
1205 | * | |
1206 | * This temporarily disables EDMA hardware events on the specified channel, | |
1207 | * preventing them from triggering new transfers on its behalf | |
1208 | */ | |
1209 | void edma_pause(unsigned channel) | |
1210 | { | |
60902a2c SR |
1211 | unsigned ctlr; |
1212 | ||
1213 | ctlr = EDMA_CTLR(channel); | |
1214 | channel = EDMA_CHAN_SLOT(channel); | |
1215 | ||
3f68b98a | 1216 | if (channel < edma_cc[ctlr]->num_channels) { |
d78a9494 | 1217 | unsigned int mask = BIT(channel & 0x1f); |
a4768d22 | 1218 | |
60902a2c | 1219 | edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask); |
a4768d22 KH |
1220 | } |
1221 | } | |
1222 | EXPORT_SYMBOL(edma_pause); | |
1223 | ||
1224 | /** | |
1225 | * edma_resume - resumes dma on a paused channel | |
1226 | * @channel: on which edma_pause() has been called | |
1227 | * | |
1228 | * This re-enables EDMA hardware events on the specified channel. | |
1229 | */ | |
1230 | void edma_resume(unsigned channel) | |
1231 | { | |
60902a2c SR |
1232 | unsigned ctlr; |
1233 | ||
1234 | ctlr = EDMA_CTLR(channel); | |
1235 | channel = EDMA_CHAN_SLOT(channel); | |
1236 | ||
3f68b98a | 1237 | if (channel < edma_cc[ctlr]->num_channels) { |
d78a9494 | 1238 | unsigned int mask = BIT(channel & 0x1f); |
a4768d22 | 1239 | |
60902a2c | 1240 | edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask); |
a4768d22 KH |
1241 | } |
1242 | } | |
1243 | EXPORT_SYMBOL(edma_resume); | |
1244 | ||
1245 | /** | |
1246 | * edma_start - start dma on a channel | |
1247 | * @channel: channel being activated | |
1248 | * | |
1249 | * Channels with event associations will be triggered by their hardware | |
1250 | * events, and channels without such associations will be triggered by | |
1251 | * software. (At this writing there is no interface for using software | |
1252 | * triggers except with channels that don't support hardware triggers.) | |
1253 | * | |
1254 | * Returns zero on success, else negative errno. | |
1255 | */ | |
1256 | int edma_start(unsigned channel) | |
1257 | { | |
60902a2c SR |
1258 | unsigned ctlr; |
1259 | ||
1260 | ctlr = EDMA_CTLR(channel); | |
1261 | channel = EDMA_CHAN_SLOT(channel); | |
1262 | ||
3f68b98a | 1263 | if (channel < edma_cc[ctlr]->num_channels) { |
a4768d22 | 1264 | int j = channel >> 5; |
d78a9494 | 1265 | unsigned int mask = BIT(channel & 0x1f); |
a4768d22 KH |
1266 | |
1267 | /* EDMA channels without event association */ | |
3f68b98a | 1268 | if (test_bit(channel, edma_cc[ctlr]->edma_unused)) { |
a4768d22 | 1269 | pr_debug("EDMA: ESR%d %08x\n", j, |
60902a2c SR |
1270 | edma_shadow0_read_array(ctlr, SH_ESR, j)); |
1271 | edma_shadow0_write_array(ctlr, SH_ESR, j, mask); | |
a4768d22 KH |
1272 | return 0; |
1273 | } | |
1274 | ||
1275 | /* EDMA channel with event association */ | |
1276 | pr_debug("EDMA: ER%d %08x\n", j, | |
60902a2c | 1277 | edma_shadow0_read_array(ctlr, SH_ER, j)); |
bb17ef10 BN |
1278 | /* Clear any pending event or error */ |
1279 | edma_write_array(ctlr, EDMA_ECR, j, mask); | |
60902a2c | 1280 | edma_write_array(ctlr, EDMA_EMCR, j, mask); |
a4768d22 | 1281 | /* Clear any SER */ |
60902a2c SR |
1282 | edma_shadow0_write_array(ctlr, SH_SECR, j, mask); |
1283 | edma_shadow0_write_array(ctlr, SH_EESR, j, mask); | |
a4768d22 | 1284 | pr_debug("EDMA: EER%d %08x\n", j, |
60902a2c | 1285 | edma_shadow0_read_array(ctlr, SH_EER, j)); |
a4768d22 KH |
1286 | return 0; |
1287 | } | |
1288 | ||
1289 | return -EINVAL; | |
1290 | } | |
1291 | EXPORT_SYMBOL(edma_start); | |
1292 | ||
1293 | /** | |
1294 | * edma_stop - stops dma on the channel passed | |
1295 | * @channel: channel being deactivated | |
1296 | * | |
1297 | * When @lch is a channel, any active transfer is paused and | |
1298 | * all pending hardware events are cleared. The current transfer | |
1299 | * may not be resumed, and the channel's Parameter RAM should be | |
1300 | * reinitialized before being reused. | |
1301 | */ | |
1302 | void edma_stop(unsigned channel) | |
1303 | { | |
60902a2c SR |
1304 | unsigned ctlr; |
1305 | ||
1306 | ctlr = EDMA_CTLR(channel); | |
1307 | channel = EDMA_CHAN_SLOT(channel); | |
1308 | ||
3f68b98a | 1309 | if (channel < edma_cc[ctlr]->num_channels) { |
a4768d22 | 1310 | int j = channel >> 5; |
d78a9494 | 1311 | unsigned int mask = BIT(channel & 0x1f); |
a4768d22 | 1312 | |
60902a2c SR |
1313 | edma_shadow0_write_array(ctlr, SH_EECR, j, mask); |
1314 | edma_shadow0_write_array(ctlr, SH_ECR, j, mask); | |
1315 | edma_shadow0_write_array(ctlr, SH_SECR, j, mask); | |
1316 | edma_write_array(ctlr, EDMA_EMCR, j, mask); | |
a4768d22 KH |
1317 | |
1318 | pr_debug("EDMA: EER%d %08x\n", j, | |
60902a2c | 1319 | edma_shadow0_read_array(ctlr, SH_EER, j)); |
a4768d22 KH |
1320 | |
1321 | /* REVISIT: consider guarding against inappropriate event | |
1322 | * chaining by overwriting with dummy_paramset. | |
1323 | */ | |
1324 | } | |
1325 | } | |
1326 | EXPORT_SYMBOL(edma_stop); | |
1327 | ||
1328 | /****************************************************************************** | |
1329 | * | |
1330 | * It cleans ParamEntry qand bring back EDMA to initial state if media has | |
1331 | * been removed before EDMA has finished.It is usedful for removable media. | |
1332 | * Arguments: | |
1333 | * ch_no - channel no | |
1334 | * | |
1335 | * Return: zero on success, or corresponding error no on failure | |
1336 | * | |
1337 | * FIXME this should not be needed ... edma_stop() should suffice. | |
1338 | * | |
1339 | *****************************************************************************/ | |
1340 | ||
1341 | void edma_clean_channel(unsigned channel) | |
1342 | { | |
60902a2c SR |
1343 | unsigned ctlr; |
1344 | ||
1345 | ctlr = EDMA_CTLR(channel); | |
1346 | channel = EDMA_CHAN_SLOT(channel); | |
1347 | ||
3f68b98a | 1348 | if (channel < edma_cc[ctlr]->num_channels) { |
a4768d22 | 1349 | int j = (channel >> 5); |
d78a9494 | 1350 | unsigned int mask = BIT(channel & 0x1f); |
a4768d22 KH |
1351 | |
1352 | pr_debug("EDMA: EMR%d %08x\n", j, | |
60902a2c SR |
1353 | edma_read_array(ctlr, EDMA_EMR, j)); |
1354 | edma_shadow0_write_array(ctlr, SH_ECR, j, mask); | |
a4768d22 | 1355 | /* Clear the corresponding EMR bits */ |
60902a2c | 1356 | edma_write_array(ctlr, EDMA_EMCR, j, mask); |
a4768d22 | 1357 | /* Clear any SER */ |
60902a2c | 1358 | edma_shadow0_write_array(ctlr, SH_SECR, j, mask); |
d78a9494 | 1359 | edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0)); |
a4768d22 KH |
1360 | } |
1361 | } | |
1362 | EXPORT_SYMBOL(edma_clean_channel); | |
1363 | ||
1364 | /* | |
1365 | * edma_clear_event - clear an outstanding event on the DMA channel | |
1366 | * Arguments: | |
1367 | * channel - channel number | |
1368 | */ | |
1369 | void edma_clear_event(unsigned channel) | |
1370 | { | |
60902a2c SR |
1371 | unsigned ctlr; |
1372 | ||
1373 | ctlr = EDMA_CTLR(channel); | |
1374 | channel = EDMA_CHAN_SLOT(channel); | |
1375 | ||
3f68b98a | 1376 | if (channel >= edma_cc[ctlr]->num_channels) |
a4768d22 KH |
1377 | return; |
1378 | if (channel < 32) | |
d78a9494 | 1379 | edma_write(ctlr, EDMA_ECR, BIT(channel)); |
a4768d22 | 1380 | else |
d78a9494 | 1381 | edma_write(ctlr, EDMA_ECRH, BIT(channel - 32)); |
a4768d22 KH |
1382 | } |
1383 | EXPORT_SYMBOL(edma_clear_event); | |
1384 | ||
1385 | /*-----------------------------------------------------------------------*/ | |
1386 | ||
1387 | static int __init edma_probe(struct platform_device *pdev) | |
1388 | { | |
bc3ac9f3 | 1389 | struct edma_soc_info **info = pdev->dev.platform_data; |
60902a2c SR |
1390 | const s8 (*queue_priority_mapping)[2]; |
1391 | const s8 (*queue_tc_mapping)[2]; | |
90bd4e6d | 1392 | int i, j, off, ln, found = 0; |
60902a2c | 1393 | int status = -1; |
90bd4e6d RS |
1394 | const s16 (*rsv_chans)[2]; |
1395 | const s16 (*rsv_slots)[2]; | |
60902a2c SR |
1396 | int irq[EDMA_MAX_CC] = {0, 0}; |
1397 | int err_irq[EDMA_MAX_CC] = {0, 0}; | |
1398 | struct resource *r[EDMA_MAX_CC] = {NULL}; | |
1399 | resource_size_t len[EDMA_MAX_CC]; | |
1400 | char res_name[10]; | |
1401 | char irq_name[10]; | |
a4768d22 KH |
1402 | |
1403 | if (!info) | |
1404 | return -ENODEV; | |
1405 | ||
60902a2c SR |
1406 | for (j = 0; j < EDMA_MAX_CC; j++) { |
1407 | sprintf(res_name, "edma_cc%d", j); | |
1408 | r[j] = platform_get_resource_byname(pdev, IORESOURCE_MEM, | |
1409 | res_name); | |
bc3ac9f3 | 1410 | if (!r[j] || !info[j]) { |
60902a2c SR |
1411 | if (found) |
1412 | break; | |
1413 | else | |
1414 | return -ENODEV; | |
243bc654 | 1415 | } else { |
60902a2c | 1416 | found = 1; |
243bc654 | 1417 | } |
60902a2c SR |
1418 | |
1419 | len[j] = resource_size(r[j]); | |
1420 | ||
1421 | r[j] = request_mem_region(r[j]->start, len[j], | |
1422 | dev_name(&pdev->dev)); | |
1423 | if (!r[j]) { | |
1424 | status = -EBUSY; | |
1425 | goto fail1; | |
1426 | } | |
a4768d22 | 1427 | |
60902a2c SR |
1428 | edmacc_regs_base[j] = ioremap(r[j]->start, len[j]); |
1429 | if (!edmacc_regs_base[j]) { | |
1430 | status = -EBUSY; | |
1431 | goto fail1; | |
1432 | } | |
a4768d22 | 1433 | |
3f68b98a SN |
1434 | edma_cc[j] = kmalloc(sizeof(struct edma), GFP_KERNEL); |
1435 | if (!edma_cc[j]) { | |
60902a2c SR |
1436 | status = -ENOMEM; |
1437 | goto fail1; | |
1438 | } | |
3f68b98a | 1439 | memset(edma_cc[j], 0, sizeof(struct edma)); |
60902a2c | 1440 | |
bc3ac9f3 | 1441 | edma_cc[j]->num_channels = min_t(unsigned, info[j]->n_channel, |
60902a2c | 1442 | EDMA_MAX_DMACH); |
bc3ac9f3 | 1443 | edma_cc[j]->num_slots = min_t(unsigned, info[j]->n_slot, |
60902a2c | 1444 | EDMA_MAX_PARAMENTRY); |
bc3ac9f3 SN |
1445 | edma_cc[j]->num_cc = min_t(unsigned, info[j]->n_cc, |
1446 | EDMA_MAX_CC); | |
60902a2c | 1447 | |
bc3ac9f3 | 1448 | edma_cc[j]->default_queue = info[j]->default_queue; |
3f68b98a SN |
1449 | if (!edma_cc[j]->default_queue) |
1450 | edma_cc[j]->default_queue = EVENTQ_1; | |
a0f0202e | 1451 | |
60902a2c SR |
1452 | dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n", |
1453 | edmacc_regs_base[j]); | |
1454 | ||
3f68b98a | 1455 | for (i = 0; i < edma_cc[j]->num_slots; i++) |
60902a2c SR |
1456 | memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i), |
1457 | &dummy_paramset, PARM_SIZE); | |
1458 | ||
f900d552 | 1459 | /* Mark all channels as unused */ |
3f68b98a SN |
1460 | memset(edma_cc[j]->edma_unused, 0xff, |
1461 | sizeof(edma_cc[j]->edma_unused)); | |
a4768d22 | 1462 | |
90bd4e6d RS |
1463 | if (info[j]->rsv) { |
1464 | ||
1465 | /* Clear the reserved channels in unused list */ | |
1466 | rsv_chans = info[j]->rsv->rsv_chans; | |
1467 | if (rsv_chans) { | |
1468 | for (i = 0; rsv_chans[i][0] != -1; i++) { | |
1469 | off = rsv_chans[i][0]; | |
1470 | ln = rsv_chans[i][1]; | |
1471 | clear_bits(off, ln, | |
1472 | edma_cc[j]->edma_unused); | |
1473 | } | |
1474 | } | |
1475 | ||
1476 | /* Set the reserved slots in inuse list */ | |
1477 | rsv_slots = info[j]->rsv->rsv_slots; | |
1478 | if (rsv_slots) { | |
1479 | for (i = 0; rsv_slots[i][0] != -1; i++) { | |
1480 | off = rsv_slots[i][0]; | |
1481 | ln = rsv_slots[i][1]; | |
1482 | set_bits(off, ln, | |
1483 | edma_cc[j]->edma_inuse); | |
1484 | } | |
1485 | } | |
1486 | } | |
1487 | ||
60902a2c SR |
1488 | sprintf(irq_name, "edma%d", j); |
1489 | irq[j] = platform_get_irq_byname(pdev, irq_name); | |
3f68b98a | 1490 | edma_cc[j]->irq_res_start = irq[j]; |
60902a2c SR |
1491 | status = request_irq(irq[j], dma_irq_handler, 0, "edma", |
1492 | &pdev->dev); | |
1493 | if (status < 0) { | |
1494 | dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n", | |
1495 | irq[j], status); | |
1496 | goto fail; | |
1497 | } | |
a4768d22 | 1498 | |
60902a2c SR |
1499 | sprintf(irq_name, "edma%d_err", j); |
1500 | err_irq[j] = platform_get_irq_byname(pdev, irq_name); | |
3f68b98a | 1501 | edma_cc[j]->irq_res_end = err_irq[j]; |
60902a2c SR |
1502 | status = request_irq(err_irq[j], dma_ccerr_handler, 0, |
1503 | "edma_error", &pdev->dev); | |
1504 | if (status < 0) { | |
1505 | dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n", | |
1506 | err_irq[j], status); | |
1507 | goto fail; | |
1508 | } | |
a4768d22 | 1509 | |
60902a2c SR |
1510 | /* Everything lives on transfer controller 1 until otherwise |
1511 | * specified. This way, long transfers on the low priority queue | |
1512 | * started by the codec engine will not cause audio defects. | |
1513 | */ | |
3f68b98a | 1514 | for (i = 0; i < edma_cc[j]->num_channels; i++) |
60902a2c | 1515 | map_dmach_queue(j, i, EVENTQ_1); |
a4768d22 | 1516 | |
bc3ac9f3 SN |
1517 | queue_tc_mapping = info[j]->queue_tc_mapping; |
1518 | queue_priority_mapping = info[j]->queue_priority_mapping; | |
a4768d22 | 1519 | |
60902a2c SR |
1520 | /* Event queue to TC mapping */ |
1521 | for (i = 0; queue_tc_mapping[i][0] != -1; i++) | |
1522 | map_queue_tc(j, queue_tc_mapping[i][0], | |
1523 | queue_tc_mapping[i][1]); | |
a4768d22 | 1524 | |
60902a2c SR |
1525 | /* Event queue priority mapping */ |
1526 | for (i = 0; queue_priority_mapping[i][0] != -1; i++) | |
1527 | assign_priority_to_queue(j, | |
1528 | queue_priority_mapping[i][0], | |
1529 | queue_priority_mapping[i][1]); | |
1530 | ||
1531 | /* Map the channel to param entry if channel mapping logic | |
1532 | * exist | |
1533 | */ | |
1534 | if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST) | |
1535 | map_dmach_param(j); | |
a4768d22 | 1536 | |
bc3ac9f3 | 1537 | for (i = 0; i < info[j]->n_region; i++) { |
60902a2c SR |
1538 | edma_write_array2(j, EDMA_DRAE, i, 0, 0x0); |
1539 | edma_write_array2(j, EDMA_DRAE, i, 1, 0x0); | |
1540 | edma_write_array(j, EDMA_QRAE, i, 0x0); | |
1541 | } | |
2d517508 | 1542 | arch_num_cc++; |
a4768d22 KH |
1543 | } |
1544 | ||
1545 | if (tc_errs_handled) { | |
1546 | status = request_irq(IRQ_TCERRINT0, dma_tc0err_handler, 0, | |
1547 | "edma_tc0", &pdev->dev); | |
1548 | if (status < 0) { | |
1549 | dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n", | |
1550 | IRQ_TCERRINT0, status); | |
1551 | return status; | |
1552 | } | |
1553 | status = request_irq(IRQ_TCERRINT, dma_tc1err_handler, 0, | |
1554 | "edma_tc1", &pdev->dev); | |
1555 | if (status < 0) { | |
1556 | dev_dbg(&pdev->dev, "request_irq %d --> %d\n", | |
1557 | IRQ_TCERRINT, status); | |
1558 | return status; | |
1559 | } | |
1560 | } | |
1561 | ||
a4768d22 KH |
1562 | return 0; |
1563 | ||
1564 | fail: | |
60902a2c SR |
1565 | for (i = 0; i < EDMA_MAX_CC; i++) { |
1566 | if (err_irq[i]) | |
1567 | free_irq(err_irq[i], &pdev->dev); | |
1568 | if (irq[i]) | |
1569 | free_irq(irq[i], &pdev->dev); | |
1570 | } | |
a4768d22 | 1571 | fail1: |
60902a2c SR |
1572 | for (i = 0; i < EDMA_MAX_CC; i++) { |
1573 | if (r[i]) | |
1574 | release_mem_region(r[i]->start, len[i]); | |
1575 | if (edmacc_regs_base[i]) | |
1576 | iounmap(edmacc_regs_base[i]); | |
3f68b98a | 1577 | kfree(edma_cc[i]); |
60902a2c | 1578 | } |
a4768d22 KH |
1579 | return status; |
1580 | } | |
1581 | ||
1582 | ||
1583 | static struct platform_driver edma_driver = { | |
1584 | .driver.name = "edma", | |
1585 | }; | |
1586 | ||
1587 | static int __init edma_init(void) | |
1588 | { | |
1589 | return platform_driver_probe(&edma_driver, edma_probe); | |
1590 | } | |
1591 | arch_initcall(edma_init); | |
1592 |