Commit | Line | Data |
---|---|---|
a4768d22 KH |
1 | /* |
2 | * EDMA3 support for DaVinci | |
3 | * | |
4 | * Copyright (C) 2006-2009 Texas Instruments. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | */ | |
20 | #include <linux/kernel.h> | |
a4768d22 KH |
21 | #include <linux/init.h> |
22 | #include <linux/module.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/platform_device.h> | |
a4768d22 | 25 | #include <linux/io.h> |
5a0e3ad6 | 26 | #include <linux/slab.h> |
a4768d22 | 27 | |
a4768d22 | 28 | #include <mach/edma.h> |
a4768d22 KH |
29 | |
30 | /* Offsets matching "struct edmacc_param" */ | |
31 | #define PARM_OPT 0x00 | |
32 | #define PARM_SRC 0x04 | |
33 | #define PARM_A_B_CNT 0x08 | |
34 | #define PARM_DST 0x0c | |
35 | #define PARM_SRC_DST_BIDX 0x10 | |
36 | #define PARM_LINK_BCNTRLD 0x14 | |
37 | #define PARM_SRC_DST_CIDX 0x18 | |
38 | #define PARM_CCNT 0x1c | |
39 | ||
40 | #define PARM_SIZE 0x20 | |
41 | ||
42 | /* Offsets for EDMA CC global channel registers and their shadows */ | |
43 | #define SH_ER 0x00 /* 64 bits */ | |
44 | #define SH_ECR 0x08 /* 64 bits */ | |
45 | #define SH_ESR 0x10 /* 64 bits */ | |
46 | #define SH_CER 0x18 /* 64 bits */ | |
47 | #define SH_EER 0x20 /* 64 bits */ | |
48 | #define SH_EECR 0x28 /* 64 bits */ | |
49 | #define SH_EESR 0x30 /* 64 bits */ | |
50 | #define SH_SER 0x38 /* 64 bits */ | |
51 | #define SH_SECR 0x40 /* 64 bits */ | |
52 | #define SH_IER 0x50 /* 64 bits */ | |
53 | #define SH_IECR 0x58 /* 64 bits */ | |
54 | #define SH_IESR 0x60 /* 64 bits */ | |
55 | #define SH_IPR 0x68 /* 64 bits */ | |
56 | #define SH_ICR 0x70 /* 64 bits */ | |
57 | #define SH_IEVAL 0x78 | |
58 | #define SH_QER 0x80 | |
59 | #define SH_QEER 0x84 | |
60 | #define SH_QEECR 0x88 | |
61 | #define SH_QEESR 0x8c | |
62 | #define SH_QSER 0x90 | |
63 | #define SH_QSECR 0x94 | |
64 | #define SH_SIZE 0x200 | |
65 | ||
66 | /* Offsets for EDMA CC global registers */ | |
67 | #define EDMA_REV 0x0000 | |
68 | #define EDMA_CCCFG 0x0004 | |
69 | #define EDMA_QCHMAP 0x0200 /* 8 registers */ | |
70 | #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */ | |
71 | #define EDMA_QDMAQNUM 0x0260 | |
72 | #define EDMA_QUETCMAP 0x0280 | |
73 | #define EDMA_QUEPRI 0x0284 | |
74 | #define EDMA_EMR 0x0300 /* 64 bits */ | |
75 | #define EDMA_EMCR 0x0308 /* 64 bits */ | |
76 | #define EDMA_QEMR 0x0310 | |
77 | #define EDMA_QEMCR 0x0314 | |
78 | #define EDMA_CCERR 0x0318 | |
79 | #define EDMA_CCERRCLR 0x031c | |
80 | #define EDMA_EEVAL 0x0320 | |
81 | #define EDMA_DRAE 0x0340 /* 4 x 64 bits*/ | |
82 | #define EDMA_QRAE 0x0380 /* 4 registers */ | |
83 | #define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */ | |
84 | #define EDMA_QSTAT 0x0600 /* 2 registers */ | |
85 | #define EDMA_QWMTHRA 0x0620 | |
86 | #define EDMA_QWMTHRB 0x0624 | |
87 | #define EDMA_CCSTAT 0x0640 | |
88 | ||
89 | #define EDMA_M 0x1000 /* global channel registers */ | |
90 | #define EDMA_ECR 0x1008 | |
91 | #define EDMA_ECRH 0x100C | |
92 | #define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */ | |
93 | #define EDMA_PARM 0x4000 /* 128 param entries */ | |
94 | ||
a4768d22 KH |
95 | #define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5)) |
96 | ||
60902a2c SR |
97 | #define EDMA_DCHMAP 0x0100 /* 64 registers */ |
98 | #define CHMAP_EXIST BIT(24) | |
99 | ||
a4768d22 KH |
100 | #define EDMA_MAX_DMACH 64 |
101 | #define EDMA_MAX_PARAMENTRY 512 | |
60902a2c | 102 | #define EDMA_MAX_CC 2 |
a4768d22 KH |
103 | |
104 | ||
105 | /*****************************************************************************/ | |
106 | ||
60902a2c | 107 | static void __iomem *edmacc_regs_base[EDMA_MAX_CC]; |
a4768d22 | 108 | |
60902a2c | 109 | static inline unsigned int edma_read(unsigned ctlr, int offset) |
a4768d22 | 110 | { |
60902a2c | 111 | return (unsigned int)__raw_readl(edmacc_regs_base[ctlr] + offset); |
a4768d22 KH |
112 | } |
113 | ||
60902a2c | 114 | static inline void edma_write(unsigned ctlr, int offset, int val) |
a4768d22 | 115 | { |
60902a2c | 116 | __raw_writel(val, edmacc_regs_base[ctlr] + offset); |
a4768d22 | 117 | } |
60902a2c SR |
118 | static inline void edma_modify(unsigned ctlr, int offset, unsigned and, |
119 | unsigned or) | |
a4768d22 | 120 | { |
60902a2c | 121 | unsigned val = edma_read(ctlr, offset); |
a4768d22 KH |
122 | val &= and; |
123 | val |= or; | |
60902a2c | 124 | edma_write(ctlr, offset, val); |
a4768d22 | 125 | } |
60902a2c | 126 | static inline void edma_and(unsigned ctlr, int offset, unsigned and) |
a4768d22 | 127 | { |
60902a2c | 128 | unsigned val = edma_read(ctlr, offset); |
a4768d22 | 129 | val &= and; |
60902a2c | 130 | edma_write(ctlr, offset, val); |
a4768d22 | 131 | } |
60902a2c | 132 | static inline void edma_or(unsigned ctlr, int offset, unsigned or) |
a4768d22 | 133 | { |
60902a2c | 134 | unsigned val = edma_read(ctlr, offset); |
a4768d22 | 135 | val |= or; |
60902a2c | 136 | edma_write(ctlr, offset, val); |
a4768d22 | 137 | } |
60902a2c | 138 | static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i) |
a4768d22 | 139 | { |
60902a2c | 140 | return edma_read(ctlr, offset + (i << 2)); |
a4768d22 | 141 | } |
60902a2c SR |
142 | static inline void edma_write_array(unsigned ctlr, int offset, int i, |
143 | unsigned val) | |
a4768d22 | 144 | { |
60902a2c | 145 | edma_write(ctlr, offset + (i << 2), val); |
a4768d22 | 146 | } |
60902a2c | 147 | static inline void edma_modify_array(unsigned ctlr, int offset, int i, |
a4768d22 KH |
148 | unsigned and, unsigned or) |
149 | { | |
60902a2c | 150 | edma_modify(ctlr, offset + (i << 2), and, or); |
a4768d22 | 151 | } |
60902a2c | 152 | static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or) |
a4768d22 | 153 | { |
60902a2c | 154 | edma_or(ctlr, offset + (i << 2), or); |
a4768d22 | 155 | } |
60902a2c SR |
156 | static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j, |
157 | unsigned or) | |
a4768d22 | 158 | { |
60902a2c | 159 | edma_or(ctlr, offset + ((i*2 + j) << 2), or); |
a4768d22 | 160 | } |
60902a2c SR |
161 | static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j, |
162 | unsigned val) | |
a4768d22 | 163 | { |
60902a2c | 164 | edma_write(ctlr, offset + ((i*2 + j) << 2), val); |
a4768d22 | 165 | } |
60902a2c | 166 | static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset) |
a4768d22 | 167 | { |
60902a2c | 168 | return edma_read(ctlr, EDMA_SHADOW0 + offset); |
a4768d22 | 169 | } |
60902a2c SR |
170 | static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset, |
171 | int i) | |
a4768d22 | 172 | { |
60902a2c | 173 | return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2)); |
a4768d22 | 174 | } |
60902a2c | 175 | static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val) |
a4768d22 | 176 | { |
60902a2c | 177 | edma_write(ctlr, EDMA_SHADOW0 + offset, val); |
a4768d22 | 178 | } |
60902a2c SR |
179 | static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i, |
180 | unsigned val) | |
a4768d22 | 181 | { |
60902a2c | 182 | edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val); |
a4768d22 | 183 | } |
60902a2c SR |
184 | static inline unsigned int edma_parm_read(unsigned ctlr, int offset, |
185 | int param_no) | |
a4768d22 | 186 | { |
60902a2c | 187 | return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5)); |
a4768d22 | 188 | } |
60902a2c SR |
189 | static inline void edma_parm_write(unsigned ctlr, int offset, int param_no, |
190 | unsigned val) | |
a4768d22 | 191 | { |
60902a2c | 192 | edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val); |
a4768d22 | 193 | } |
60902a2c | 194 | static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no, |
a4768d22 KH |
195 | unsigned and, unsigned or) |
196 | { | |
60902a2c | 197 | edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or); |
a4768d22 | 198 | } |
60902a2c SR |
199 | static inline void edma_parm_and(unsigned ctlr, int offset, int param_no, |
200 | unsigned and) | |
a4768d22 | 201 | { |
60902a2c | 202 | edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and); |
a4768d22 | 203 | } |
60902a2c SR |
204 | static inline void edma_parm_or(unsigned ctlr, int offset, int param_no, |
205 | unsigned or) | |
a4768d22 | 206 | { |
60902a2c | 207 | edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or); |
a4768d22 KH |
208 | } |
209 | ||
210 | /*****************************************************************************/ | |
211 | ||
212 | /* actual number of DMA channels and slots on this silicon */ | |
60902a2c SR |
213 | struct edma { |
214 | /* how many dma resources of each type */ | |
215 | unsigned num_channels; | |
216 | unsigned num_region; | |
217 | unsigned num_slots; | |
218 | unsigned num_tc; | |
219 | unsigned num_cc; | |
a0f0202e | 220 | enum dma_event_q default_queue; |
60902a2c SR |
221 | |
222 | /* list of channels with no even trigger; terminated by "-1" */ | |
223 | const s8 *noevent; | |
224 | ||
225 | /* The edma_inuse bit for each PaRAM slot is clear unless the | |
226 | * channel is in use ... by ARM or DSP, for QDMA, or whatever. | |
227 | */ | |
228 | DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY); | |
a4768d22 | 229 | |
f900d552 SR |
230 | /* The edma_unused bit for each channel is clear unless |
231 | * it is not being used on this platform. It uses a bit | |
232 | * of SOC-specific initialization code. | |
60902a2c | 233 | */ |
f900d552 | 234 | DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH); |
a4768d22 | 235 | |
60902a2c SR |
236 | unsigned irq_res_start; |
237 | unsigned irq_res_end; | |
a4768d22 | 238 | |
60902a2c SR |
239 | struct dma_interrupt_data { |
240 | void (*callback)(unsigned channel, unsigned short ch_status, | |
241 | void *data); | |
242 | void *data; | |
243 | } intr_data[EDMA_MAX_DMACH]; | |
244 | }; | |
245 | ||
246 | static struct edma *edma_info[EDMA_MAX_CC]; | |
2d517508 | 247 | static int arch_num_cc; |
a4768d22 KH |
248 | |
249 | /* dummy param set used to (re)initialize parameter RAM slots */ | |
250 | static const struct edmacc_param dummy_paramset = { | |
251 | .link_bcntrld = 0xffff, | |
252 | .ccnt = 1, | |
253 | }; | |
254 | ||
a4768d22 KH |
255 | /*****************************************************************************/ |
256 | ||
60902a2c SR |
257 | static void map_dmach_queue(unsigned ctlr, unsigned ch_no, |
258 | enum dma_event_q queue_no) | |
a4768d22 KH |
259 | { |
260 | int bit = (ch_no & 0x7) * 4; | |
261 | ||
262 | /* default to low priority queue */ | |
263 | if (queue_no == EVENTQ_DEFAULT) | |
a0f0202e | 264 | queue_no = edma_info[ctlr]->default_queue; |
a4768d22 KH |
265 | |
266 | queue_no &= 7; | |
60902a2c | 267 | edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3), |
a4768d22 KH |
268 | ~(0x7 << bit), queue_no << bit); |
269 | } | |
270 | ||
60902a2c | 271 | static void __init map_queue_tc(unsigned ctlr, int queue_no, int tc_no) |
a4768d22 KH |
272 | { |
273 | int bit = queue_no * 4; | |
60902a2c | 274 | edma_modify(ctlr, EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit)); |
a4768d22 KH |
275 | } |
276 | ||
60902a2c SR |
277 | static void __init assign_priority_to_queue(unsigned ctlr, int queue_no, |
278 | int priority) | |
a4768d22 KH |
279 | { |
280 | int bit = queue_no * 4; | |
60902a2c SR |
281 | edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit), |
282 | ((priority & 0x7) << bit)); | |
283 | } | |
284 | ||
285 | /** | |
286 | * map_dmach_param - Maps channel number to param entry number | |
287 | * | |
288 | * This maps the dma channel number to param entry numberter. In | |
289 | * other words using the DMA channel mapping registers a param entry | |
290 | * can be mapped to any channel | |
291 | * | |
292 | * Callers are responsible for ensuring the channel mapping logic is | |
293 | * included in that particular EDMA variant (Eg : dm646x) | |
294 | * | |
295 | */ | |
296 | static void __init map_dmach_param(unsigned ctlr) | |
297 | { | |
298 | int i; | |
299 | for (i = 0; i < EDMA_MAX_DMACH; i++) | |
300 | edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5)); | |
a4768d22 KH |
301 | } |
302 | ||
303 | static inline void | |
304 | setup_dma_interrupt(unsigned lch, | |
305 | void (*callback)(unsigned channel, u16 ch_status, void *data), | |
306 | void *data) | |
307 | { | |
60902a2c SR |
308 | unsigned ctlr; |
309 | ||
310 | ctlr = EDMA_CTLR(lch); | |
311 | lch = EDMA_CHAN_SLOT(lch); | |
312 | ||
a4768d22 | 313 | if (!callback) { |
60902a2c | 314 | edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5, |
a4768d22 KH |
315 | (1 << (lch & 0x1f))); |
316 | } | |
317 | ||
60902a2c SR |
318 | edma_info[ctlr]->intr_data[lch].callback = callback; |
319 | edma_info[ctlr]->intr_data[lch].data = data; | |
a4768d22 KH |
320 | |
321 | if (callback) { | |
60902a2c | 322 | edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5, |
a4768d22 | 323 | (1 << (lch & 0x1f))); |
60902a2c | 324 | edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5, |
a4768d22 KH |
325 | (1 << (lch & 0x1f))); |
326 | } | |
327 | } | |
328 | ||
60902a2c SR |
329 | static int irq2ctlr(int irq) |
330 | { | |
331 | if (irq >= edma_info[0]->irq_res_start && | |
332 | irq <= edma_info[0]->irq_res_end) | |
333 | return 0; | |
334 | else if (irq >= edma_info[1]->irq_res_start && | |
335 | irq <= edma_info[1]->irq_res_end) | |
336 | return 1; | |
337 | ||
338 | return -1; | |
339 | } | |
340 | ||
a4768d22 KH |
341 | /****************************************************************************** |
342 | * | |
343 | * DMA interrupt handler | |
344 | * | |
345 | *****************************************************************************/ | |
346 | static irqreturn_t dma_irq_handler(int irq, void *data) | |
347 | { | |
348 | int i; | |
60902a2c | 349 | unsigned ctlr; |
a4768d22 KH |
350 | unsigned int cnt = 0; |
351 | ||
60902a2c SR |
352 | ctlr = irq2ctlr(irq); |
353 | ||
a4768d22 KH |
354 | dev_dbg(data, "dma_irq_handler\n"); |
355 | ||
60902a2c SR |
356 | if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0) |
357 | && (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0)) | |
a4768d22 KH |
358 | return IRQ_NONE; |
359 | ||
360 | while (1) { | |
361 | int j; | |
a7e05065 AA |
362 | if (edma_shadow0_read_array(ctlr, SH_IPR, 0) & |
363 | edma_shadow0_read_array(ctlr, SH_IER, 0)) | |
a4768d22 | 364 | j = 0; |
a7e05065 AA |
365 | else if (edma_shadow0_read_array(ctlr, SH_IPR, 1) & |
366 | edma_shadow0_read_array(ctlr, SH_IER, 1)) | |
a4768d22 KH |
367 | j = 1; |
368 | else | |
369 | break; | |
370 | dev_dbg(data, "IPR%d %08x\n", j, | |
60902a2c | 371 | edma_shadow0_read_array(ctlr, SH_IPR, j)); |
a4768d22 KH |
372 | for (i = 0; i < 32; i++) { |
373 | int k = (j << 5) + i; | |
a7e05065 AA |
374 | if ((edma_shadow0_read_array(ctlr, SH_IPR, j) & BIT(i)) |
375 | && (edma_shadow0_read_array(ctlr, | |
376 | SH_IER, j) & BIT(i))) { | |
a4768d22 | 377 | /* Clear the corresponding IPR bits */ |
60902a2c SR |
378 | edma_shadow0_write_array(ctlr, SH_ICR, j, |
379 | (1 << i)); | |
380 | if (edma_info[ctlr]->intr_data[k].callback) { | |
381 | edma_info[ctlr]->intr_data[k].callback( | |
382 | k, DMA_COMPLETE, | |
383 | edma_info[ctlr]->intr_data[k]. | |
384 | data); | |
a4768d22 KH |
385 | } |
386 | } | |
387 | } | |
388 | cnt++; | |
389 | if (cnt > 10) | |
390 | break; | |
391 | } | |
60902a2c | 392 | edma_shadow0_write(ctlr, SH_IEVAL, 1); |
a4768d22 KH |
393 | return IRQ_HANDLED; |
394 | } | |
395 | ||
396 | /****************************************************************************** | |
397 | * | |
398 | * DMA error interrupt handler | |
399 | * | |
400 | *****************************************************************************/ | |
401 | static irqreturn_t dma_ccerr_handler(int irq, void *data) | |
402 | { | |
403 | int i; | |
60902a2c | 404 | unsigned ctlr; |
a4768d22 KH |
405 | unsigned int cnt = 0; |
406 | ||
60902a2c SR |
407 | ctlr = irq2ctlr(irq); |
408 | ||
a4768d22 KH |
409 | dev_dbg(data, "dma_ccerr_handler\n"); |
410 | ||
60902a2c SR |
411 | if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) && |
412 | (edma_read_array(ctlr, EDMA_EMR, 1) == 0) && | |
413 | (edma_read(ctlr, EDMA_QEMR) == 0) && | |
414 | (edma_read(ctlr, EDMA_CCERR) == 0)) | |
a4768d22 KH |
415 | return IRQ_NONE; |
416 | ||
417 | while (1) { | |
418 | int j = -1; | |
60902a2c | 419 | if (edma_read_array(ctlr, EDMA_EMR, 0)) |
a4768d22 | 420 | j = 0; |
60902a2c | 421 | else if (edma_read_array(ctlr, EDMA_EMR, 1)) |
a4768d22 KH |
422 | j = 1; |
423 | if (j >= 0) { | |
424 | dev_dbg(data, "EMR%d %08x\n", j, | |
60902a2c | 425 | edma_read_array(ctlr, EDMA_EMR, j)); |
a4768d22 KH |
426 | for (i = 0; i < 32; i++) { |
427 | int k = (j << 5) + i; | |
60902a2c SR |
428 | if (edma_read_array(ctlr, EDMA_EMR, j) & |
429 | (1 << i)) { | |
a4768d22 | 430 | /* Clear the corresponding EMR bits */ |
60902a2c SR |
431 | edma_write_array(ctlr, EDMA_EMCR, j, |
432 | 1 << i); | |
a4768d22 | 433 | /* Clear any SER */ |
60902a2c SR |
434 | edma_shadow0_write_array(ctlr, SH_SECR, |
435 | j, (1 << i)); | |
436 | if (edma_info[ctlr]->intr_data[k]. | |
437 | callback) { | |
438 | edma_info[ctlr]->intr_data[k]. | |
439 | callback(k, | |
440 | DMA_CC_ERROR, | |
441 | edma_info[ctlr]->intr_data | |
442 | [k].data); | |
a4768d22 KH |
443 | } |
444 | } | |
445 | } | |
60902a2c | 446 | } else if (edma_read(ctlr, EDMA_QEMR)) { |
a4768d22 | 447 | dev_dbg(data, "QEMR %02x\n", |
60902a2c | 448 | edma_read(ctlr, EDMA_QEMR)); |
a4768d22 | 449 | for (i = 0; i < 8; i++) { |
60902a2c | 450 | if (edma_read(ctlr, EDMA_QEMR) & (1 << i)) { |
a4768d22 | 451 | /* Clear the corresponding IPR bits */ |
60902a2c SR |
452 | edma_write(ctlr, EDMA_QEMCR, 1 << i); |
453 | edma_shadow0_write(ctlr, SH_QSECR, | |
454 | (1 << i)); | |
a4768d22 KH |
455 | |
456 | /* NOTE: not reported!! */ | |
457 | } | |
458 | } | |
60902a2c | 459 | } else if (edma_read(ctlr, EDMA_CCERR)) { |
a4768d22 | 460 | dev_dbg(data, "CCERR %08x\n", |
60902a2c | 461 | edma_read(ctlr, EDMA_CCERR)); |
a4768d22 KH |
462 | /* FIXME: CCERR.BIT(16) ignored! much better |
463 | * to just write CCERRCLR with CCERR value... | |
464 | */ | |
465 | for (i = 0; i < 8; i++) { | |
60902a2c | 466 | if (edma_read(ctlr, EDMA_CCERR) & (1 << i)) { |
a4768d22 | 467 | /* Clear the corresponding IPR bits */ |
60902a2c | 468 | edma_write(ctlr, EDMA_CCERRCLR, 1 << i); |
a4768d22 KH |
469 | |
470 | /* NOTE: not reported!! */ | |
471 | } | |
472 | } | |
473 | } | |
60902a2c SR |
474 | if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) |
475 | && (edma_read_array(ctlr, EDMA_EMR, 1) == 0) | |
476 | && (edma_read(ctlr, EDMA_QEMR) == 0) | |
477 | && (edma_read(ctlr, EDMA_CCERR) == 0)) { | |
a4768d22 KH |
478 | break; |
479 | } | |
480 | cnt++; | |
481 | if (cnt > 10) | |
482 | break; | |
483 | } | |
60902a2c | 484 | edma_write(ctlr, EDMA_EEVAL, 1); |
a4768d22 KH |
485 | return IRQ_HANDLED; |
486 | } | |
487 | ||
488 | /****************************************************************************** | |
489 | * | |
490 | * Transfer controller error interrupt handlers | |
491 | * | |
492 | *****************************************************************************/ | |
493 | ||
494 | #define tc_errs_handled false /* disabled as long as they're NOPs */ | |
495 | ||
496 | static irqreturn_t dma_tc0err_handler(int irq, void *data) | |
497 | { | |
498 | dev_dbg(data, "dma_tc0err_handler\n"); | |
499 | return IRQ_HANDLED; | |
500 | } | |
501 | ||
502 | static irqreturn_t dma_tc1err_handler(int irq, void *data) | |
503 | { | |
504 | dev_dbg(data, "dma_tc1err_handler\n"); | |
505 | return IRQ_HANDLED; | |
506 | } | |
507 | ||
134ce221 SP |
508 | static int reserve_contiguous_slots(int ctlr, unsigned int id, |
509 | unsigned int num_slots, | |
510 | unsigned int start_slot) | |
213765d7 SP |
511 | { |
512 | int i, j; | |
134ce221 SP |
513 | unsigned int count = num_slots; |
514 | int stop_slot = start_slot; | |
cc93fc3f | 515 | DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY); |
213765d7 | 516 | |
134ce221 | 517 | for (i = start_slot; i < edma_info[ctlr]->num_slots; ++i) { |
213765d7 | 518 | j = EDMA_CHAN_SLOT(i); |
cc93fc3f SP |
519 | if (!test_and_set_bit(j, edma_info[ctlr]->edma_inuse)) { |
520 | /* Record our current beginning slot */ | |
134ce221 SP |
521 | if (count == num_slots) |
522 | stop_slot = i; | |
cc93fc3f | 523 | |
213765d7 | 524 | count--; |
cc93fc3f SP |
525 | set_bit(j, tmp_inuse); |
526 | ||
213765d7 SP |
527 | if (count == 0) |
528 | break; | |
cc93fc3f SP |
529 | } else { |
530 | clear_bit(j, tmp_inuse); | |
531 | ||
532 | if (id == EDMA_CONT_PARAMS_FIXED_EXACT) { | |
134ce221 | 533 | stop_slot = i; |
cc93fc3f SP |
534 | break; |
535 | } else | |
134ce221 | 536 | count = num_slots; |
cc93fc3f | 537 | } |
213765d7 SP |
538 | } |
539 | ||
540 | /* | |
541 | * We have to clear any bits that we set | |
134ce221 SP |
542 | * if we run out parameter RAM slots, i.e we do find a set |
543 | * of contiguous parameter RAM slots but do not find the exact number | |
544 | * requested as we may reach the total number of parameter RAM slots | |
213765d7 | 545 | */ |
cc93fc3f | 546 | if (i == edma_info[ctlr]->num_slots) |
134ce221 | 547 | stop_slot = i; |
cc93fc3f | 548 | |
134ce221 | 549 | for (j = start_slot; j < stop_slot; j++) |
cc93fc3f | 550 | if (test_bit(j, tmp_inuse)) |
213765d7 SP |
551 | clear_bit(j, edma_info[ctlr]->edma_inuse); |
552 | ||
cc93fc3f | 553 | if (count) |
213765d7 | 554 | return -EBUSY; |
213765d7 | 555 | |
134ce221 | 556 | for (j = i - num_slots + 1; j <= i; ++j) |
213765d7 SP |
557 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j), |
558 | &dummy_paramset, PARM_SIZE); | |
559 | ||
134ce221 | 560 | return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1); |
213765d7 SP |
561 | } |
562 | ||
f900d552 SR |
563 | static int prepare_unused_channel_list(struct device *dev, void *data) |
564 | { | |
565 | struct platform_device *pdev = to_platform_device(dev); | |
566 | int i, ctlr; | |
567 | ||
568 | for (i = 0; i < pdev->num_resources; i++) { | |
569 | if ((pdev->resource[i].flags & IORESOURCE_DMA) && | |
570 | (int)pdev->resource[i].start >= 0) { | |
571 | ctlr = EDMA_CTLR(pdev->resource[i].start); | |
572 | clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start), | |
573 | edma_info[ctlr]->edma_unused); | |
574 | } | |
575 | } | |
576 | ||
577 | return 0; | |
578 | } | |
579 | ||
a4768d22 KH |
580 | /*-----------------------------------------------------------------------*/ |
581 | ||
f900d552 SR |
582 | static bool unused_chan_list_done; |
583 | ||
a4768d22 KH |
584 | /* Resource alloc/free: dma channels, parameter RAM slots */ |
585 | ||
586 | /** | |
587 | * edma_alloc_channel - allocate DMA channel and paired parameter RAM | |
588 | * @channel: specific channel to allocate; negative for "any unmapped channel" | |
589 | * @callback: optional; to be issued on DMA completion or errors | |
590 | * @data: passed to callback | |
591 | * @eventq_no: an EVENTQ_* constant, used to choose which Transfer | |
592 | * Controller (TC) executes requests using this channel. Use | |
593 | * EVENTQ_DEFAULT unless you really need a high priority queue. | |
594 | * | |
595 | * This allocates a DMA channel and its associated parameter RAM slot. | |
596 | * The parameter RAM is initialized to hold a dummy transfer. | |
597 | * | |
598 | * Normal use is to pass a specific channel number as @channel, to make | |
599 | * use of hardware events mapped to that channel. When the channel will | |
600 | * be used only for software triggering or event chaining, channels not | |
601 | * mapped to hardware events (or mapped to unused events) are preferable. | |
602 | * | |
603 | * DMA transfers start from a channel using edma_start(), or by | |
604 | * chaining. When the transfer described in that channel's parameter RAM | |
605 | * slot completes, that slot's data may be reloaded through a link. | |
606 | * | |
607 | * DMA errors are only reported to the @callback associated with the | |
608 | * channel driving that transfer, but transfer completion callbacks can | |
609 | * be sent to another channel under control of the TCC field in | |
610 | * the option word of the transfer's parameter RAM set. Drivers must not | |
611 | * use DMA transfer completion callbacks for channels they did not allocate. | |
612 | * (The same applies to TCC codes used in transfer chaining.) | |
613 | * | |
614 | * Returns the number of the channel, else negative errno. | |
615 | */ | |
616 | int edma_alloc_channel(int channel, | |
617 | void (*callback)(unsigned channel, u16 ch_status, void *data), | |
618 | void *data, | |
619 | enum dma_event_q eventq_no) | |
620 | { | |
447f18f1 | 621 | unsigned i, done = 0, ctlr = 0; |
f900d552 SR |
622 | int ret = 0; |
623 | ||
624 | if (!unused_chan_list_done) { | |
625 | /* | |
626 | * Scan all the platform devices to find out the EDMA channels | |
627 | * used and clear them in the unused list, making the rest | |
628 | * available for ARM usage. | |
629 | */ | |
630 | ret = bus_for_each_dev(&platform_bus_type, NULL, NULL, | |
631 | prepare_unused_channel_list); | |
632 | if (ret < 0) | |
633 | return ret; | |
634 | ||
635 | unused_chan_list_done = true; | |
636 | } | |
60902a2c SR |
637 | |
638 | if (channel >= 0) { | |
639 | ctlr = EDMA_CTLR(channel); | |
640 | channel = EDMA_CHAN_SLOT(channel); | |
641 | } | |
642 | ||
a4768d22 | 643 | if (channel < 0) { |
2d517508 | 644 | for (i = 0; i < arch_num_cc; i++) { |
60902a2c SR |
645 | channel = 0; |
646 | for (;;) { | |
647 | channel = find_next_bit(edma_info[i]-> | |
f900d552 | 648 | edma_unused, |
60902a2c SR |
649 | edma_info[i]->num_channels, |
650 | channel); | |
651 | if (channel == edma_info[i]->num_channels) | |
447f18f1 | 652 | break; |
60902a2c SR |
653 | if (!test_and_set_bit(channel, |
654 | edma_info[i]->edma_inuse)) { | |
655 | done = 1; | |
656 | ctlr = i; | |
657 | break; | |
658 | } | |
659 | channel++; | |
660 | } | |
661 | if (done) | |
a4768d22 | 662 | break; |
a4768d22 | 663 | } |
447f18f1 SR |
664 | if (!done) |
665 | return -ENOMEM; | |
60902a2c | 666 | } else if (channel >= edma_info[ctlr]->num_channels) { |
a4768d22 | 667 | return -EINVAL; |
60902a2c | 668 | } else if (test_and_set_bit(channel, edma_info[ctlr]->edma_inuse)) { |
a4768d22 KH |
669 | return -EBUSY; |
670 | } | |
671 | ||
672 | /* ensure access through shadow region 0 */ | |
60902a2c | 673 | edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, 1 << (channel & 0x1f)); |
a4768d22 KH |
674 | |
675 | /* ensure no events are pending */ | |
60902a2c SR |
676 | edma_stop(EDMA_CTLR_CHAN(ctlr, channel)); |
677 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel), | |
a4768d22 KH |
678 | &dummy_paramset, PARM_SIZE); |
679 | ||
680 | if (callback) | |
60902a2c SR |
681 | setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel), |
682 | callback, data); | |
a4768d22 | 683 | |
60902a2c | 684 | map_dmach_queue(ctlr, channel, eventq_no); |
a4768d22 | 685 | |
0e6cb8d2 | 686 | return EDMA_CTLR_CHAN(ctlr, channel); |
a4768d22 KH |
687 | } |
688 | EXPORT_SYMBOL(edma_alloc_channel); | |
689 | ||
690 | ||
691 | /** | |
692 | * edma_free_channel - deallocate DMA channel | |
693 | * @channel: dma channel returned from edma_alloc_channel() | |
694 | * | |
695 | * This deallocates the DMA channel and associated parameter RAM slot | |
696 | * allocated by edma_alloc_channel(). | |
697 | * | |
698 | * Callers are responsible for ensuring the channel is inactive, and | |
699 | * will not be reactivated by linking, chaining, or software calls to | |
700 | * edma_start(). | |
701 | */ | |
702 | void edma_free_channel(unsigned channel) | |
703 | { | |
60902a2c SR |
704 | unsigned ctlr; |
705 | ||
706 | ctlr = EDMA_CTLR(channel); | |
707 | channel = EDMA_CHAN_SLOT(channel); | |
708 | ||
709 | if (channel >= edma_info[ctlr]->num_channels) | |
a4768d22 KH |
710 | return; |
711 | ||
712 | setup_dma_interrupt(channel, NULL, NULL); | |
713 | /* REVISIT should probably take out of shadow region 0 */ | |
714 | ||
60902a2c | 715 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel), |
a4768d22 | 716 | &dummy_paramset, PARM_SIZE); |
60902a2c | 717 | clear_bit(channel, edma_info[ctlr]->edma_inuse); |
a4768d22 KH |
718 | } |
719 | EXPORT_SYMBOL(edma_free_channel); | |
720 | ||
721 | /** | |
722 | * edma_alloc_slot - allocate DMA parameter RAM | |
723 | * @slot: specific slot to allocate; negative for "any unused slot" | |
724 | * | |
725 | * This allocates a parameter RAM slot, initializing it to hold a | |
726 | * dummy transfer. Slots allocated using this routine have not been | |
727 | * mapped to a hardware DMA channel, and will normally be used by | |
728 | * linking to them from a slot associated with a DMA channel. | |
729 | * | |
730 | * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific | |
731 | * slots may be allocated on behalf of DSP firmware. | |
732 | * | |
733 | * Returns the number of the slot, else negative errno. | |
734 | */ | |
60902a2c | 735 | int edma_alloc_slot(unsigned ctlr, int slot) |
a4768d22 | 736 | { |
60902a2c SR |
737 | if (slot >= 0) |
738 | slot = EDMA_CHAN_SLOT(slot); | |
739 | ||
a4768d22 | 740 | if (slot < 0) { |
60902a2c | 741 | slot = edma_info[ctlr]->num_channels; |
a4768d22 | 742 | for (;;) { |
60902a2c SR |
743 | slot = find_next_zero_bit(edma_info[ctlr]->edma_inuse, |
744 | edma_info[ctlr]->num_slots, slot); | |
745 | if (slot == edma_info[ctlr]->num_slots) | |
a4768d22 | 746 | return -ENOMEM; |
60902a2c SR |
747 | if (!test_and_set_bit(slot, |
748 | edma_info[ctlr]->edma_inuse)) | |
a4768d22 KH |
749 | break; |
750 | } | |
60902a2c SR |
751 | } else if (slot < edma_info[ctlr]->num_channels || |
752 | slot >= edma_info[ctlr]->num_slots) { | |
a4768d22 | 753 | return -EINVAL; |
60902a2c | 754 | } else if (test_and_set_bit(slot, edma_info[ctlr]->edma_inuse)) { |
a4768d22 KH |
755 | return -EBUSY; |
756 | } | |
757 | ||
60902a2c | 758 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), |
a4768d22 KH |
759 | &dummy_paramset, PARM_SIZE); |
760 | ||
60902a2c | 761 | return EDMA_CTLR_CHAN(ctlr, slot); |
a4768d22 KH |
762 | } |
763 | EXPORT_SYMBOL(edma_alloc_slot); | |
764 | ||
765 | /** | |
766 | * edma_free_slot - deallocate DMA parameter RAM | |
767 | * @slot: parameter RAM slot returned from edma_alloc_slot() | |
768 | * | |
769 | * This deallocates the parameter RAM slot allocated by edma_alloc_slot(). | |
770 | * Callers are responsible for ensuring the slot is inactive, and will | |
771 | * not be activated. | |
772 | */ | |
773 | void edma_free_slot(unsigned slot) | |
774 | { | |
60902a2c SR |
775 | unsigned ctlr; |
776 | ||
777 | ctlr = EDMA_CTLR(slot); | |
778 | slot = EDMA_CHAN_SLOT(slot); | |
779 | ||
780 | if (slot < edma_info[ctlr]->num_channels || | |
781 | slot >= edma_info[ctlr]->num_slots) | |
a4768d22 KH |
782 | return; |
783 | ||
60902a2c | 784 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), |
a4768d22 | 785 | &dummy_paramset, PARM_SIZE); |
60902a2c | 786 | clear_bit(slot, edma_info[ctlr]->edma_inuse); |
a4768d22 KH |
787 | } |
788 | EXPORT_SYMBOL(edma_free_slot); | |
789 | ||
213765d7 SP |
790 | |
791 | /** | |
792 | * edma_alloc_cont_slots- alloc contiguous parameter RAM slots | |
793 | * The API will return the starting point of a set of | |
134ce221 | 794 | * contiguous parameter RAM slots that have been requested |
213765d7 SP |
795 | * |
796 | * @id: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT | |
797 | * or EDMA_CONT_PARAMS_FIXED_NOT_EXACT | |
134ce221 SP |
798 | * @count: number of contiguous Paramter RAM slots |
799 | * @slot - the start value of Parameter RAM slot that should be passed if id | |
213765d7 SP |
800 | * is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT |
801 | * | |
802 | * If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of | |
134ce221 SP |
803 | * contiguous Parameter RAM slots from parameter RAM 64 in the case of |
804 | * DaVinci SOCs and 32 in the case of DA8xx SOCs. | |
213765d7 SP |
805 | * |
806 | * If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a | |
134ce221 | 807 | * set of contiguous parameter RAM slots from the "slot" that is passed as an |
213765d7 SP |
808 | * argument to the API. |
809 | * | |
810 | * If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries | |
134ce221 | 811 | * starts looking for a set of contiguous parameter RAMs from the "slot" |
213765d7 | 812 | * that is passed as an argument to the API. On failure the API will try to |
134ce221 SP |
813 | * find a set of contiguous Parameter RAM slots from the remaining Parameter |
814 | * RAM slots | |
213765d7 SP |
815 | */ |
816 | int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count) | |
817 | { | |
818 | /* | |
819 | * The start slot requested should be greater than | |
820 | * the number of channels and lesser than the total number | |
821 | * of slots | |
822 | */ | |
6b0cf4e9 SP |
823 | if ((id != EDMA_CONT_PARAMS_ANY) && |
824 | (slot < edma_info[ctlr]->num_channels || | |
825 | slot >= edma_info[ctlr]->num_slots)) | |
213765d7 SP |
826 | return -EINVAL; |
827 | ||
828 | /* | |
134ce221 | 829 | * The number of parameter RAM slots requested cannot be less than 1 |
213765d7 SP |
830 | * and cannot be more than the number of slots minus the number of |
831 | * channels | |
832 | */ | |
833 | if (count < 1 || count > | |
834 | (edma_info[ctlr]->num_slots - edma_info[ctlr]->num_channels)) | |
835 | return -EINVAL; | |
836 | ||
837 | switch (id) { | |
838 | case EDMA_CONT_PARAMS_ANY: | |
134ce221 | 839 | return reserve_contiguous_slots(ctlr, id, count, |
213765d7 SP |
840 | edma_info[ctlr]->num_channels); |
841 | case EDMA_CONT_PARAMS_FIXED_EXACT: | |
842 | case EDMA_CONT_PARAMS_FIXED_NOT_EXACT: | |
134ce221 | 843 | return reserve_contiguous_slots(ctlr, id, count, slot); |
213765d7 SP |
844 | default: |
845 | return -EINVAL; | |
846 | } | |
847 | ||
848 | } | |
849 | EXPORT_SYMBOL(edma_alloc_cont_slots); | |
850 | ||
851 | /** | |
134ce221 SP |
852 | * edma_free_cont_slots - deallocate DMA parameter RAM slots |
853 | * @slot: first parameter RAM of a set of parameter RAM slots to be freed | |
854 | * @count: the number of contiguous parameter RAM slots to be freed | |
213765d7 SP |
855 | * |
856 | * This deallocates the parameter RAM slots allocated by | |
857 | * edma_alloc_cont_slots. | |
858 | * Callers/applications need to keep track of sets of contiguous | |
134ce221 | 859 | * parameter RAM slots that have been allocated using the edma_alloc_cont_slots |
213765d7 SP |
860 | * API. |
861 | * Callers are responsible for ensuring the slots are inactive, and will | |
862 | * not be activated. | |
863 | */ | |
864 | int edma_free_cont_slots(unsigned slot, int count) | |
865 | { | |
51c99e04 | 866 | unsigned ctlr, slot_to_free; |
213765d7 SP |
867 | int i; |
868 | ||
869 | ctlr = EDMA_CTLR(slot); | |
870 | slot = EDMA_CHAN_SLOT(slot); | |
871 | ||
872 | if (slot < edma_info[ctlr]->num_channels || | |
873 | slot >= edma_info[ctlr]->num_slots || | |
874 | count < 1) | |
875 | return -EINVAL; | |
876 | ||
877 | for (i = slot; i < slot + count; ++i) { | |
878 | ctlr = EDMA_CTLR(i); | |
51c99e04 | 879 | slot_to_free = EDMA_CHAN_SLOT(i); |
213765d7 | 880 | |
51c99e04 | 881 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free), |
213765d7 | 882 | &dummy_paramset, PARM_SIZE); |
51c99e04 | 883 | clear_bit(slot_to_free, edma_info[ctlr]->edma_inuse); |
213765d7 SP |
884 | } |
885 | ||
886 | return 0; | |
887 | } | |
888 | EXPORT_SYMBOL(edma_free_cont_slots); | |
889 | ||
a4768d22 KH |
890 | /*-----------------------------------------------------------------------*/ |
891 | ||
892 | /* Parameter RAM operations (i) -- read/write partial slots */ | |
893 | ||
894 | /** | |
895 | * edma_set_src - set initial DMA source address in parameter RAM slot | |
896 | * @slot: parameter RAM slot being configured | |
897 | * @src_port: physical address of source (memory, controller FIFO, etc) | |
898 | * @addressMode: INCR, except in very rare cases | |
899 | * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the | |
900 | * width to use when addressing the fifo (e.g. W8BIT, W32BIT) | |
901 | * | |
902 | * Note that the source address is modified during the DMA transfer | |
903 | * according to edma_set_src_index(). | |
904 | */ | |
905 | void edma_set_src(unsigned slot, dma_addr_t src_port, | |
906 | enum address_mode mode, enum fifo_width width) | |
907 | { | |
60902a2c SR |
908 | unsigned ctlr; |
909 | ||
910 | ctlr = EDMA_CTLR(slot); | |
911 | slot = EDMA_CHAN_SLOT(slot); | |
912 | ||
913 | if (slot < edma_info[ctlr]->num_slots) { | |
914 | unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); | |
a4768d22 KH |
915 | |
916 | if (mode) { | |
917 | /* set SAM and program FWID */ | |
918 | i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8)); | |
919 | } else { | |
920 | /* clear SAM */ | |
921 | i &= ~SAM; | |
922 | } | |
60902a2c | 923 | edma_parm_write(ctlr, PARM_OPT, slot, i); |
a4768d22 KH |
924 | |
925 | /* set the source port address | |
926 | in source register of param structure */ | |
60902a2c | 927 | edma_parm_write(ctlr, PARM_SRC, slot, src_port); |
a4768d22 KH |
928 | } |
929 | } | |
930 | EXPORT_SYMBOL(edma_set_src); | |
931 | ||
932 | /** | |
933 | * edma_set_dest - set initial DMA destination address in parameter RAM slot | |
934 | * @slot: parameter RAM slot being configured | |
935 | * @dest_port: physical address of destination (memory, controller FIFO, etc) | |
936 | * @addressMode: INCR, except in very rare cases | |
937 | * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the | |
938 | * width to use when addressing the fifo (e.g. W8BIT, W32BIT) | |
939 | * | |
940 | * Note that the destination address is modified during the DMA transfer | |
941 | * according to edma_set_dest_index(). | |
942 | */ | |
943 | void edma_set_dest(unsigned slot, dma_addr_t dest_port, | |
944 | enum address_mode mode, enum fifo_width width) | |
945 | { | |
60902a2c SR |
946 | unsigned ctlr; |
947 | ||
948 | ctlr = EDMA_CTLR(slot); | |
949 | slot = EDMA_CHAN_SLOT(slot); | |
950 | ||
951 | if (slot < edma_info[ctlr]->num_slots) { | |
952 | unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); | |
a4768d22 KH |
953 | |
954 | if (mode) { | |
955 | /* set DAM and program FWID */ | |
956 | i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8)); | |
957 | } else { | |
958 | /* clear DAM */ | |
959 | i &= ~DAM; | |
960 | } | |
60902a2c | 961 | edma_parm_write(ctlr, PARM_OPT, slot, i); |
a4768d22 KH |
962 | /* set the destination port address |
963 | in dest register of param structure */ | |
60902a2c | 964 | edma_parm_write(ctlr, PARM_DST, slot, dest_port); |
a4768d22 KH |
965 | } |
966 | } | |
967 | EXPORT_SYMBOL(edma_set_dest); | |
968 | ||
969 | /** | |
970 | * edma_get_position - returns the current transfer points | |
971 | * @slot: parameter RAM slot being examined | |
972 | * @src: pointer to source port position | |
973 | * @dst: pointer to destination port position | |
974 | * | |
975 | * Returns current source and destination addresses for a particular | |
976 | * parameter RAM slot. Its channel should not be active when this is called. | |
977 | */ | |
978 | void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst) | |
979 | { | |
980 | struct edmacc_param temp; | |
60902a2c SR |
981 | unsigned ctlr; |
982 | ||
983 | ctlr = EDMA_CTLR(slot); | |
984 | slot = EDMA_CHAN_SLOT(slot); | |
a4768d22 | 985 | |
60902a2c | 986 | edma_read_slot(EDMA_CTLR_CHAN(ctlr, slot), &temp); |
a4768d22 KH |
987 | if (src != NULL) |
988 | *src = temp.src; | |
989 | if (dst != NULL) | |
990 | *dst = temp.dst; | |
991 | } | |
992 | EXPORT_SYMBOL(edma_get_position); | |
993 | ||
994 | /** | |
995 | * edma_set_src_index - configure DMA source address indexing | |
996 | * @slot: parameter RAM slot being configured | |
997 | * @src_bidx: byte offset between source arrays in a frame | |
998 | * @src_cidx: byte offset between source frames in a block | |
999 | * | |
1000 | * Offsets are specified to support either contiguous or discontiguous | |
1001 | * memory transfers, or repeated access to a hardware register, as needed. | |
1002 | * When accessing hardware registers, both offsets are normally zero. | |
1003 | */ | |
1004 | void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx) | |
1005 | { | |
60902a2c SR |
1006 | unsigned ctlr; |
1007 | ||
1008 | ctlr = EDMA_CTLR(slot); | |
1009 | slot = EDMA_CHAN_SLOT(slot); | |
1010 | ||
1011 | if (slot < edma_info[ctlr]->num_slots) { | |
1012 | edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, | |
a4768d22 | 1013 | 0xffff0000, src_bidx); |
60902a2c | 1014 | edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, |
a4768d22 KH |
1015 | 0xffff0000, src_cidx); |
1016 | } | |
1017 | } | |
1018 | EXPORT_SYMBOL(edma_set_src_index); | |
1019 | ||
1020 | /** | |
1021 | * edma_set_dest_index - configure DMA destination address indexing | |
1022 | * @slot: parameter RAM slot being configured | |
1023 | * @dest_bidx: byte offset between destination arrays in a frame | |
1024 | * @dest_cidx: byte offset between destination frames in a block | |
1025 | * | |
1026 | * Offsets are specified to support either contiguous or discontiguous | |
1027 | * memory transfers, or repeated access to a hardware register, as needed. | |
1028 | * When accessing hardware registers, both offsets are normally zero. | |
1029 | */ | |
1030 | void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx) | |
1031 | { | |
60902a2c SR |
1032 | unsigned ctlr; |
1033 | ||
1034 | ctlr = EDMA_CTLR(slot); | |
1035 | slot = EDMA_CHAN_SLOT(slot); | |
1036 | ||
1037 | if (slot < edma_info[ctlr]->num_slots) { | |
1038 | edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, | |
a4768d22 | 1039 | 0x0000ffff, dest_bidx << 16); |
60902a2c | 1040 | edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, |
a4768d22 KH |
1041 | 0x0000ffff, dest_cidx << 16); |
1042 | } | |
1043 | } | |
1044 | EXPORT_SYMBOL(edma_set_dest_index); | |
1045 | ||
1046 | /** | |
1047 | * edma_set_transfer_params - configure DMA transfer parameters | |
1048 | * @slot: parameter RAM slot being configured | |
1049 | * @acnt: how many bytes per array (at least one) | |
1050 | * @bcnt: how many arrays per frame (at least one) | |
1051 | * @ccnt: how many frames per block (at least one) | |
1052 | * @bcnt_rld: used only for A-Synchronized transfers; this specifies | |
1053 | * the value to reload into bcnt when it decrements to zero | |
1054 | * @sync_mode: ASYNC or ABSYNC | |
1055 | * | |
1056 | * See the EDMA3 documentation to understand how to configure and link | |
1057 | * transfers using the fields in PaRAM slots. If you are not doing it | |
1058 | * all at once with edma_write_slot(), you will use this routine | |
1059 | * plus two calls each for source and destination, setting the initial | |
1060 | * address and saying how to index that address. | |
1061 | * | |
1062 | * An example of an A-Synchronized transfer is a serial link using a | |
1063 | * single word shift register. In that case, @acnt would be equal to | |
1064 | * that word size; the serial controller issues a DMA synchronization | |
1065 | * event to transfer each word, and memory access by the DMA transfer | |
1066 | * controller will be word-at-a-time. | |
1067 | * | |
1068 | * An example of an AB-Synchronized transfer is a device using a FIFO. | |
1069 | * In that case, @acnt equals the FIFO width and @bcnt equals its depth. | |
1070 | * The controller with the FIFO issues DMA synchronization events when | |
1071 | * the FIFO threshold is reached, and the DMA transfer controller will | |
1072 | * transfer one frame to (or from) the FIFO. It will probably use | |
1073 | * efficient burst modes to access memory. | |
1074 | */ | |
1075 | void edma_set_transfer_params(unsigned slot, | |
1076 | u16 acnt, u16 bcnt, u16 ccnt, | |
1077 | u16 bcnt_rld, enum sync_dimension sync_mode) | |
1078 | { | |
60902a2c SR |
1079 | unsigned ctlr; |
1080 | ||
1081 | ctlr = EDMA_CTLR(slot); | |
1082 | slot = EDMA_CHAN_SLOT(slot); | |
1083 | ||
1084 | if (slot < edma_info[ctlr]->num_slots) { | |
1085 | edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot, | |
a4768d22 KH |
1086 | 0x0000ffff, bcnt_rld << 16); |
1087 | if (sync_mode == ASYNC) | |
60902a2c | 1088 | edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM); |
a4768d22 | 1089 | else |
60902a2c | 1090 | edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM); |
a4768d22 | 1091 | /* Set the acount, bcount, ccount registers */ |
60902a2c SR |
1092 | edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt); |
1093 | edma_parm_write(ctlr, PARM_CCNT, slot, ccnt); | |
a4768d22 KH |
1094 | } |
1095 | } | |
1096 | EXPORT_SYMBOL(edma_set_transfer_params); | |
1097 | ||
1098 | /** | |
1099 | * edma_link - link one parameter RAM slot to another | |
1100 | * @from: parameter RAM slot originating the link | |
1101 | * @to: parameter RAM slot which is the link target | |
1102 | * | |
1103 | * The originating slot should not be part of any active DMA transfer. | |
1104 | */ | |
1105 | void edma_link(unsigned from, unsigned to) | |
1106 | { | |
60902a2c SR |
1107 | unsigned ctlr_from, ctlr_to; |
1108 | ||
1109 | ctlr_from = EDMA_CTLR(from); | |
1110 | from = EDMA_CHAN_SLOT(from); | |
1111 | ctlr_to = EDMA_CTLR(to); | |
1112 | to = EDMA_CHAN_SLOT(to); | |
1113 | ||
1114 | if (from >= edma_info[ctlr_from]->num_slots) | |
a4768d22 | 1115 | return; |
60902a2c | 1116 | if (to >= edma_info[ctlr_to]->num_slots) |
a4768d22 | 1117 | return; |
60902a2c SR |
1118 | edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000, |
1119 | PARM_OFFSET(to)); | |
a4768d22 KH |
1120 | } |
1121 | EXPORT_SYMBOL(edma_link); | |
1122 | ||
1123 | /** | |
1124 | * edma_unlink - cut link from one parameter RAM slot | |
1125 | * @from: parameter RAM slot originating the link | |
1126 | * | |
1127 | * The originating slot should not be part of any active DMA transfer. | |
1128 | * Its link is set to 0xffff. | |
1129 | */ | |
1130 | void edma_unlink(unsigned from) | |
1131 | { | |
60902a2c SR |
1132 | unsigned ctlr; |
1133 | ||
1134 | ctlr = EDMA_CTLR(from); | |
1135 | from = EDMA_CHAN_SLOT(from); | |
1136 | ||
1137 | if (from >= edma_info[ctlr]->num_slots) | |
a4768d22 | 1138 | return; |
60902a2c | 1139 | edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff); |
a4768d22 KH |
1140 | } |
1141 | EXPORT_SYMBOL(edma_unlink); | |
1142 | ||
1143 | /*-----------------------------------------------------------------------*/ | |
1144 | ||
1145 | /* Parameter RAM operations (ii) -- read/write whole parameter sets */ | |
1146 | ||
1147 | /** | |
1148 | * edma_write_slot - write parameter RAM data for slot | |
1149 | * @slot: number of parameter RAM slot being modified | |
1150 | * @param: data to be written into parameter RAM slot | |
1151 | * | |
1152 | * Use this to assign all parameters of a transfer at once. This | |
1153 | * allows more efficient setup of transfers than issuing multiple | |
1154 | * calls to set up those parameters in small pieces, and provides | |
1155 | * complete control over all transfer options. | |
1156 | */ | |
1157 | void edma_write_slot(unsigned slot, const struct edmacc_param *param) | |
1158 | { | |
60902a2c SR |
1159 | unsigned ctlr; |
1160 | ||
1161 | ctlr = EDMA_CTLR(slot); | |
1162 | slot = EDMA_CHAN_SLOT(slot); | |
1163 | ||
1164 | if (slot >= edma_info[ctlr]->num_slots) | |
a4768d22 | 1165 | return; |
60902a2c SR |
1166 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param, |
1167 | PARM_SIZE); | |
a4768d22 KH |
1168 | } |
1169 | EXPORT_SYMBOL(edma_write_slot); | |
1170 | ||
1171 | /** | |
1172 | * edma_read_slot - read parameter RAM data from slot | |
1173 | * @slot: number of parameter RAM slot being copied | |
1174 | * @param: where to store copy of parameter RAM data | |
1175 | * | |
1176 | * Use this to read data from a parameter RAM slot, perhaps to | |
1177 | * save them as a template for later reuse. | |
1178 | */ | |
1179 | void edma_read_slot(unsigned slot, struct edmacc_param *param) | |
1180 | { | |
60902a2c SR |
1181 | unsigned ctlr; |
1182 | ||
1183 | ctlr = EDMA_CTLR(slot); | |
1184 | slot = EDMA_CHAN_SLOT(slot); | |
1185 | ||
1186 | if (slot >= edma_info[ctlr]->num_slots) | |
a4768d22 | 1187 | return; |
60902a2c SR |
1188 | memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot), |
1189 | PARM_SIZE); | |
a4768d22 KH |
1190 | } |
1191 | EXPORT_SYMBOL(edma_read_slot); | |
1192 | ||
1193 | /*-----------------------------------------------------------------------*/ | |
1194 | ||
1195 | /* Various EDMA channel control operations */ | |
1196 | ||
1197 | /** | |
1198 | * edma_pause - pause dma on a channel | |
1199 | * @channel: on which edma_start() has been called | |
1200 | * | |
1201 | * This temporarily disables EDMA hardware events on the specified channel, | |
1202 | * preventing them from triggering new transfers on its behalf | |
1203 | */ | |
1204 | void edma_pause(unsigned channel) | |
1205 | { | |
60902a2c SR |
1206 | unsigned ctlr; |
1207 | ||
1208 | ctlr = EDMA_CTLR(channel); | |
1209 | channel = EDMA_CHAN_SLOT(channel); | |
1210 | ||
1211 | if (channel < edma_info[ctlr]->num_channels) { | |
a4768d22 KH |
1212 | unsigned int mask = (1 << (channel & 0x1f)); |
1213 | ||
60902a2c | 1214 | edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask); |
a4768d22 KH |
1215 | } |
1216 | } | |
1217 | EXPORT_SYMBOL(edma_pause); | |
1218 | ||
1219 | /** | |
1220 | * edma_resume - resumes dma on a paused channel | |
1221 | * @channel: on which edma_pause() has been called | |
1222 | * | |
1223 | * This re-enables EDMA hardware events on the specified channel. | |
1224 | */ | |
1225 | void edma_resume(unsigned channel) | |
1226 | { | |
60902a2c SR |
1227 | unsigned ctlr; |
1228 | ||
1229 | ctlr = EDMA_CTLR(channel); | |
1230 | channel = EDMA_CHAN_SLOT(channel); | |
1231 | ||
1232 | if (channel < edma_info[ctlr]->num_channels) { | |
a4768d22 KH |
1233 | unsigned int mask = (1 << (channel & 0x1f)); |
1234 | ||
60902a2c | 1235 | edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask); |
a4768d22 KH |
1236 | } |
1237 | } | |
1238 | EXPORT_SYMBOL(edma_resume); | |
1239 | ||
1240 | /** | |
1241 | * edma_start - start dma on a channel | |
1242 | * @channel: channel being activated | |
1243 | * | |
1244 | * Channels with event associations will be triggered by their hardware | |
1245 | * events, and channels without such associations will be triggered by | |
1246 | * software. (At this writing there is no interface for using software | |
1247 | * triggers except with channels that don't support hardware triggers.) | |
1248 | * | |
1249 | * Returns zero on success, else negative errno. | |
1250 | */ | |
1251 | int edma_start(unsigned channel) | |
1252 | { | |
60902a2c SR |
1253 | unsigned ctlr; |
1254 | ||
1255 | ctlr = EDMA_CTLR(channel); | |
1256 | channel = EDMA_CHAN_SLOT(channel); | |
1257 | ||
1258 | if (channel < edma_info[ctlr]->num_channels) { | |
a4768d22 KH |
1259 | int j = channel >> 5; |
1260 | unsigned int mask = (1 << (channel & 0x1f)); | |
1261 | ||
1262 | /* EDMA channels without event association */ | |
f900d552 | 1263 | if (test_bit(channel, edma_info[ctlr]->edma_unused)) { |
a4768d22 | 1264 | pr_debug("EDMA: ESR%d %08x\n", j, |
60902a2c SR |
1265 | edma_shadow0_read_array(ctlr, SH_ESR, j)); |
1266 | edma_shadow0_write_array(ctlr, SH_ESR, j, mask); | |
a4768d22 KH |
1267 | return 0; |
1268 | } | |
1269 | ||
1270 | /* EDMA channel with event association */ | |
1271 | pr_debug("EDMA: ER%d %08x\n", j, | |
60902a2c | 1272 | edma_shadow0_read_array(ctlr, SH_ER, j)); |
bb17ef10 BN |
1273 | /* Clear any pending event or error */ |
1274 | edma_write_array(ctlr, EDMA_ECR, j, mask); | |
60902a2c | 1275 | edma_write_array(ctlr, EDMA_EMCR, j, mask); |
a4768d22 | 1276 | /* Clear any SER */ |
60902a2c SR |
1277 | edma_shadow0_write_array(ctlr, SH_SECR, j, mask); |
1278 | edma_shadow0_write_array(ctlr, SH_EESR, j, mask); | |
a4768d22 | 1279 | pr_debug("EDMA: EER%d %08x\n", j, |
60902a2c | 1280 | edma_shadow0_read_array(ctlr, SH_EER, j)); |
a4768d22 KH |
1281 | return 0; |
1282 | } | |
1283 | ||
1284 | return -EINVAL; | |
1285 | } | |
1286 | EXPORT_SYMBOL(edma_start); | |
1287 | ||
1288 | /** | |
1289 | * edma_stop - stops dma on the channel passed | |
1290 | * @channel: channel being deactivated | |
1291 | * | |
1292 | * When @lch is a channel, any active transfer is paused and | |
1293 | * all pending hardware events are cleared. The current transfer | |
1294 | * may not be resumed, and the channel's Parameter RAM should be | |
1295 | * reinitialized before being reused. | |
1296 | */ | |
1297 | void edma_stop(unsigned channel) | |
1298 | { | |
60902a2c SR |
1299 | unsigned ctlr; |
1300 | ||
1301 | ctlr = EDMA_CTLR(channel); | |
1302 | channel = EDMA_CHAN_SLOT(channel); | |
1303 | ||
1304 | if (channel < edma_info[ctlr]->num_channels) { | |
a4768d22 KH |
1305 | int j = channel >> 5; |
1306 | unsigned int mask = (1 << (channel & 0x1f)); | |
1307 | ||
60902a2c SR |
1308 | edma_shadow0_write_array(ctlr, SH_EECR, j, mask); |
1309 | edma_shadow0_write_array(ctlr, SH_ECR, j, mask); | |
1310 | edma_shadow0_write_array(ctlr, SH_SECR, j, mask); | |
1311 | edma_write_array(ctlr, EDMA_EMCR, j, mask); | |
a4768d22 KH |
1312 | |
1313 | pr_debug("EDMA: EER%d %08x\n", j, | |
60902a2c | 1314 | edma_shadow0_read_array(ctlr, SH_EER, j)); |
a4768d22 KH |
1315 | |
1316 | /* REVISIT: consider guarding against inappropriate event | |
1317 | * chaining by overwriting with dummy_paramset. | |
1318 | */ | |
1319 | } | |
1320 | } | |
1321 | EXPORT_SYMBOL(edma_stop); | |
1322 | ||
1323 | /****************************************************************************** | |
1324 | * | |
1325 | * It cleans ParamEntry qand bring back EDMA to initial state if media has | |
1326 | * been removed before EDMA has finished.It is usedful for removable media. | |
1327 | * Arguments: | |
1328 | * ch_no - channel no | |
1329 | * | |
1330 | * Return: zero on success, or corresponding error no on failure | |
1331 | * | |
1332 | * FIXME this should not be needed ... edma_stop() should suffice. | |
1333 | * | |
1334 | *****************************************************************************/ | |
1335 | ||
1336 | void edma_clean_channel(unsigned channel) | |
1337 | { | |
60902a2c SR |
1338 | unsigned ctlr; |
1339 | ||
1340 | ctlr = EDMA_CTLR(channel); | |
1341 | channel = EDMA_CHAN_SLOT(channel); | |
1342 | ||
1343 | if (channel < edma_info[ctlr]->num_channels) { | |
a4768d22 KH |
1344 | int j = (channel >> 5); |
1345 | unsigned int mask = 1 << (channel & 0x1f); | |
1346 | ||
1347 | pr_debug("EDMA: EMR%d %08x\n", j, | |
60902a2c SR |
1348 | edma_read_array(ctlr, EDMA_EMR, j)); |
1349 | edma_shadow0_write_array(ctlr, SH_ECR, j, mask); | |
a4768d22 | 1350 | /* Clear the corresponding EMR bits */ |
60902a2c | 1351 | edma_write_array(ctlr, EDMA_EMCR, j, mask); |
a4768d22 | 1352 | /* Clear any SER */ |
60902a2c SR |
1353 | edma_shadow0_write_array(ctlr, SH_SECR, j, mask); |
1354 | edma_write(ctlr, EDMA_CCERRCLR, (1 << 16) | 0x3); | |
a4768d22 KH |
1355 | } |
1356 | } | |
1357 | EXPORT_SYMBOL(edma_clean_channel); | |
1358 | ||
1359 | /* | |
1360 | * edma_clear_event - clear an outstanding event on the DMA channel | |
1361 | * Arguments: | |
1362 | * channel - channel number | |
1363 | */ | |
1364 | void edma_clear_event(unsigned channel) | |
1365 | { | |
60902a2c SR |
1366 | unsigned ctlr; |
1367 | ||
1368 | ctlr = EDMA_CTLR(channel); | |
1369 | channel = EDMA_CHAN_SLOT(channel); | |
1370 | ||
1371 | if (channel >= edma_info[ctlr]->num_channels) | |
a4768d22 KH |
1372 | return; |
1373 | if (channel < 32) | |
60902a2c | 1374 | edma_write(ctlr, EDMA_ECR, 1 << channel); |
a4768d22 | 1375 | else |
60902a2c | 1376 | edma_write(ctlr, EDMA_ECRH, 1 << (channel - 32)); |
a4768d22 KH |
1377 | } |
1378 | EXPORT_SYMBOL(edma_clear_event); | |
1379 | ||
1380 | /*-----------------------------------------------------------------------*/ | |
1381 | ||
1382 | static int __init edma_probe(struct platform_device *pdev) | |
1383 | { | |
1384 | struct edma_soc_info *info = pdev->dev.platform_data; | |
60902a2c SR |
1385 | const s8 (*queue_priority_mapping)[2]; |
1386 | const s8 (*queue_tc_mapping)[2]; | |
1387 | int i, j, found = 0; | |
1388 | int status = -1; | |
60902a2c SR |
1389 | int irq[EDMA_MAX_CC] = {0, 0}; |
1390 | int err_irq[EDMA_MAX_CC] = {0, 0}; | |
1391 | struct resource *r[EDMA_MAX_CC] = {NULL}; | |
1392 | resource_size_t len[EDMA_MAX_CC]; | |
1393 | char res_name[10]; | |
1394 | char irq_name[10]; | |
a4768d22 KH |
1395 | |
1396 | if (!info) | |
1397 | return -ENODEV; | |
1398 | ||
60902a2c SR |
1399 | for (j = 0; j < EDMA_MAX_CC; j++) { |
1400 | sprintf(res_name, "edma_cc%d", j); | |
1401 | r[j] = platform_get_resource_byname(pdev, IORESOURCE_MEM, | |
1402 | res_name); | |
1403 | if (!r[j]) { | |
1404 | if (found) | |
1405 | break; | |
1406 | else | |
1407 | return -ENODEV; | |
1408 | } else | |
1409 | found = 1; | |
1410 | ||
1411 | len[j] = resource_size(r[j]); | |
1412 | ||
1413 | r[j] = request_mem_region(r[j]->start, len[j], | |
1414 | dev_name(&pdev->dev)); | |
1415 | if (!r[j]) { | |
1416 | status = -EBUSY; | |
1417 | goto fail1; | |
1418 | } | |
a4768d22 | 1419 | |
60902a2c SR |
1420 | edmacc_regs_base[j] = ioremap(r[j]->start, len[j]); |
1421 | if (!edmacc_regs_base[j]) { | |
1422 | status = -EBUSY; | |
1423 | goto fail1; | |
1424 | } | |
a4768d22 | 1425 | |
60902a2c SR |
1426 | edma_info[j] = kmalloc(sizeof(struct edma), GFP_KERNEL); |
1427 | if (!edma_info[j]) { | |
1428 | status = -ENOMEM; | |
1429 | goto fail1; | |
1430 | } | |
1431 | memset(edma_info[j], 0, sizeof(struct edma)); | |
1432 | ||
1433 | edma_info[j]->num_channels = min_t(unsigned, info[j].n_channel, | |
1434 | EDMA_MAX_DMACH); | |
1435 | edma_info[j]->num_slots = min_t(unsigned, info[j].n_slot, | |
1436 | EDMA_MAX_PARAMENTRY); | |
1437 | edma_info[j]->num_cc = min_t(unsigned, info[j].n_cc, | |
1438 | EDMA_MAX_CC); | |
1439 | ||
a0f0202e SP |
1440 | edma_info[j]->default_queue = info[j].default_queue; |
1441 | if (!edma_info[j]->default_queue) | |
1442 | edma_info[j]->default_queue = EVENTQ_1; | |
1443 | ||
60902a2c SR |
1444 | dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n", |
1445 | edmacc_regs_base[j]); | |
1446 | ||
1447 | for (i = 0; i < edma_info[j]->num_slots; i++) | |
1448 | memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i), | |
1449 | &dummy_paramset, PARM_SIZE); | |
1450 | ||
f900d552 SR |
1451 | /* Mark all channels as unused */ |
1452 | memset(edma_info[j]->edma_unused, 0xff, | |
1453 | sizeof(edma_info[j]->edma_unused)); | |
a4768d22 | 1454 | |
60902a2c SR |
1455 | sprintf(irq_name, "edma%d", j); |
1456 | irq[j] = platform_get_irq_byname(pdev, irq_name); | |
1457 | edma_info[j]->irq_res_start = irq[j]; | |
1458 | status = request_irq(irq[j], dma_irq_handler, 0, "edma", | |
1459 | &pdev->dev); | |
1460 | if (status < 0) { | |
1461 | dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n", | |
1462 | irq[j], status); | |
1463 | goto fail; | |
1464 | } | |
a4768d22 | 1465 | |
60902a2c SR |
1466 | sprintf(irq_name, "edma%d_err", j); |
1467 | err_irq[j] = platform_get_irq_byname(pdev, irq_name); | |
1468 | edma_info[j]->irq_res_end = err_irq[j]; | |
1469 | status = request_irq(err_irq[j], dma_ccerr_handler, 0, | |
1470 | "edma_error", &pdev->dev); | |
1471 | if (status < 0) { | |
1472 | dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n", | |
1473 | err_irq[j], status); | |
1474 | goto fail; | |
1475 | } | |
a4768d22 | 1476 | |
60902a2c SR |
1477 | /* Everything lives on transfer controller 1 until otherwise |
1478 | * specified. This way, long transfers on the low priority queue | |
1479 | * started by the codec engine will not cause audio defects. | |
1480 | */ | |
1481 | for (i = 0; i < edma_info[j]->num_channels; i++) | |
1482 | map_dmach_queue(j, i, EVENTQ_1); | |
a4768d22 | 1483 | |
60902a2c SR |
1484 | queue_tc_mapping = info[j].queue_tc_mapping; |
1485 | queue_priority_mapping = info[j].queue_priority_mapping; | |
a4768d22 | 1486 | |
60902a2c SR |
1487 | /* Event queue to TC mapping */ |
1488 | for (i = 0; queue_tc_mapping[i][0] != -1; i++) | |
1489 | map_queue_tc(j, queue_tc_mapping[i][0], | |
1490 | queue_tc_mapping[i][1]); | |
a4768d22 | 1491 | |
60902a2c SR |
1492 | /* Event queue priority mapping */ |
1493 | for (i = 0; queue_priority_mapping[i][0] != -1; i++) | |
1494 | assign_priority_to_queue(j, | |
1495 | queue_priority_mapping[i][0], | |
1496 | queue_priority_mapping[i][1]); | |
1497 | ||
1498 | /* Map the channel to param entry if channel mapping logic | |
1499 | * exist | |
1500 | */ | |
1501 | if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST) | |
1502 | map_dmach_param(j); | |
a4768d22 | 1503 | |
60902a2c SR |
1504 | for (i = 0; i < info[j].n_region; i++) { |
1505 | edma_write_array2(j, EDMA_DRAE, i, 0, 0x0); | |
1506 | edma_write_array2(j, EDMA_DRAE, i, 1, 0x0); | |
1507 | edma_write_array(j, EDMA_QRAE, i, 0x0); | |
1508 | } | |
2d517508 | 1509 | arch_num_cc++; |
a4768d22 KH |
1510 | } |
1511 | ||
1512 | if (tc_errs_handled) { | |
1513 | status = request_irq(IRQ_TCERRINT0, dma_tc0err_handler, 0, | |
1514 | "edma_tc0", &pdev->dev); | |
1515 | if (status < 0) { | |
1516 | dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n", | |
1517 | IRQ_TCERRINT0, status); | |
1518 | return status; | |
1519 | } | |
1520 | status = request_irq(IRQ_TCERRINT, dma_tc1err_handler, 0, | |
1521 | "edma_tc1", &pdev->dev); | |
1522 | if (status < 0) { | |
1523 | dev_dbg(&pdev->dev, "request_irq %d --> %d\n", | |
1524 | IRQ_TCERRINT, status); | |
1525 | return status; | |
1526 | } | |
1527 | } | |
1528 | ||
a4768d22 KH |
1529 | return 0; |
1530 | ||
1531 | fail: | |
60902a2c SR |
1532 | for (i = 0; i < EDMA_MAX_CC; i++) { |
1533 | if (err_irq[i]) | |
1534 | free_irq(err_irq[i], &pdev->dev); | |
1535 | if (irq[i]) | |
1536 | free_irq(irq[i], &pdev->dev); | |
1537 | } | |
a4768d22 | 1538 | fail1: |
60902a2c SR |
1539 | for (i = 0; i < EDMA_MAX_CC; i++) { |
1540 | if (r[i]) | |
1541 | release_mem_region(r[i]->start, len[i]); | |
1542 | if (edmacc_regs_base[i]) | |
1543 | iounmap(edmacc_regs_base[i]); | |
1544 | kfree(edma_info[i]); | |
1545 | } | |
a4768d22 KH |
1546 | return status; |
1547 | } | |
1548 | ||
1549 | ||
1550 | static struct platform_driver edma_driver = { | |
1551 | .driver.name = "edma", | |
1552 | }; | |
1553 | ||
1554 | static int __init edma_init(void) | |
1555 | { | |
1556 | return platform_driver_probe(&edma_driver, edma_probe); | |
1557 | } | |
1558 | arch_initcall(edma_init); | |
1559 |