[deliverable/linux.git] / arch / arm / mach-davinci / include / mach / asp.h

/*
 * <mach/asp.h> - DaVinci Audio Serial Port support
 */
#ifndef __ASM_ARCH_DAVINCI_ASP_H
#define __ASM_ARCH_DAVINCI_ASP_H

#include <mach/irqs.h>
#include <mach/edma.h>

/* Bases of dm644x and dm355 register banks */
#define DAVINCI_ASP0_BASE	0x01E02000
#define DAVINCI_ASP1_BASE	0x01E04000

/* Bases of dm365 register banks */
#define DAVINCI_DM365_ASP0_BASE	0x01D02000

/* Bases of dm646x register banks */
#define	DAVINCI_DM646X_MCASP0_REG_BASE		0x01D01000
#define DAVINCI_DM646X_MCASP1_REG_BASE		0x01D01800

/* Bases of da850/da830 McASP0  register banks */
#define DAVINCI_DA8XX_MCASP0_REG_BASE	0x01D00000

/* Bases of da830 McASP1 register banks */
#define DAVINCI_DA830_MCASP1_REG_BASE	0x01D04000

/* EDMA channels of dm644x and dm355 */
#define DAVINCI_DMA_ASP0_TX	2
#define DAVINCI_DMA_ASP0_RX	3
#define DAVINCI_DMA_ASP1_TX	8
#define DAVINCI_DMA_ASP1_RX	9

/* EDMA channels of dm646x */
#define	DAVINCI_DM646X_DMA_MCASP0_AXEVT0	6
#define	DAVINCI_DM646X_DMA_MCASP0_AREVT0	9
#define	DAVINCI_DM646X_DMA_MCASP1_AXEVT1	12

/* EDMA channels of da850/da830 McASP0 */
#define	DAVINCI_DA8XX_DMA_MCASP0_AREVT	0
#define	DAVINCI_DA8XX_DMA_MCASP0_AXEVT	1

/* EDMA channels of da830 McASP1 */
#define	DAVINCI_DA830_DMA_MCASP1_AREVT	2
#define	DAVINCI_DA830_DMA_MCASP1_AXEVT	3

/* Interrupts */
#define DAVINCI_ASP0_RX_INT	IRQ_MBRINT
#define DAVINCI_ASP0_TX_INT	IRQ_MBXINT
#define DAVINCI_ASP1_RX_INT	IRQ_MBRINT
#define DAVINCI_ASP1_TX_INT	IRQ_MBXINT

struct snd_platform_data {
	u32 tx_dma_offset;
	u32 rx_dma_offset;
	enum dma_event_q eventq_no;	/* event queue number */
	unsigned int codec_fmt;
	/*
	 * Allowing this is more efficient and eliminates left and right swaps
	 * caused by underruns, but will swap the left and right channels
	 * when compared to previous behavior.
	 */
	unsigned enable_channel_combine:1;
	unsigned sram_size_playback;
	unsigned sram_size_capture;

	/*
	 * If McBSP peripheral gets the clock from an external pin,
	 * there are three chooses, that are MCBSP_CLKX, MCBSP_CLKR
	 * and MCBSP_CLKS.
	 * Depending on different hardware connections it is possible
	 * to use this setting to change the behaviour of McBSP
	 * driver. The dm365_clk_input_pin enum is available for dm365
	 */
	int clk_input_pin;

	/* McASP specific fields */
	int tdm_slots;
	u8 op_mode;
	u8 num_serializer;
	u8 *serial_dir;
	u8 version;
	u8 txnumevt;
	u8 rxnumevt;
};

enum {
	MCASP_VERSION_1 = 0,	/* DM646x */
	MCASP_VERSION_2,	/* DA8xx/OMAPL1x */
};

enum dm365_clk_input_pin {
	MCBSP_CLKR = 0,		/* DM365 */
	MCBSP_CLKS,
};

#define INACTIVE_MODE	0
#define TX_MODE		1
#define RX_MODE		2

#define DAVINCI_MCASP_IIS_MODE	0
#define DAVINCI_MCASP_DIT_MODE	1

#endif /* __ASM_ARCH_DAVINCI_ASP_H */
Commit	Line	Data
f492ec9f DB	1	/*
	2	* <mach/asp.h> - DaVinci Audio Serial Port support
	3	*/
	4	#ifndef __ASM_ARCH_DAVINCI_ASP_H
	5	#define __ASM_ARCH_DAVINCI_ASP_H
	6
	7	#include <mach/irqs.h>
25acf553	8	#include <mach/edma.h>
f492ec9f	9
25acf553	10	/* Bases of dm644x and dm355 register banks */
f492ec9f DB	11	#define DAVINCI_ASP0_BASE 0x01E02000
	12	#define DAVINCI_ASP1_BASE 0x01E04000
	13
e9ab3214 MA	14	/* Bases of dm365 register banks */
	15	#define DAVINCI_DM365_ASP0_BASE 0x01D02000
	16
25acf553 C	17	/* Bases of dm646x register banks */
	18	#define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000
	19	#define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800
	20
491214e1 C	21	/* Bases of da850/da830 McASP0 register banks */
	22	#define DAVINCI_DA8XX_MCASP0_REG_BASE 0x01D00000
	23
e33ef5e3 C	24	/* Bases of da830 McASP1 register banks */
	25	#define DAVINCI_DA830_MCASP1_REG_BASE 0x01D04000
	26
25acf553	27	/* EDMA channels of dm644x and dm355 */
f492ec9f DB	28	#define DAVINCI_DMA_ASP0_TX 2
	29	#define DAVINCI_DMA_ASP0_RX 3
	30	#define DAVINCI_DMA_ASP1_TX 8
	31	#define DAVINCI_DMA_ASP1_RX 9
	32
25acf553 C	33	/* EDMA channels of dm646x */
	34	#define DAVINCI_DM646X_DMA_MCASP0_AXEVT0 6
	35	#define DAVINCI_DM646X_DMA_MCASP0_AREVT0 9
	36	#define DAVINCI_DM646X_DMA_MCASP1_AXEVT1 12
	37
491214e1 C	38	/* EDMA channels of da850/da830 McASP0 */
	39	#define DAVINCI_DA8XX_DMA_MCASP0_AREVT 0
	40	#define DAVINCI_DA8XX_DMA_MCASP0_AXEVT 1
	41
e33ef5e3 C	42	/* EDMA channels of da830 McASP1 */
	43	#define DAVINCI_DA830_DMA_MCASP1_AREVT 2
	44	#define DAVINCI_DA830_DMA_MCASP1_AXEVT 3
	45
f492ec9f DB	46	/* Interrupts */
	47	#define DAVINCI_ASP0_RX_INT IRQ_MBRINT
	48	#define DAVINCI_ASP0_TX_INT IRQ_MBXINT
	49	#define DAVINCI_ASP1_RX_INT IRQ_MBRINT
	50	#define DAVINCI_ASP1_TX_INT IRQ_MBXINT
	51
25acf553	52	struct snd_platform_data {
25acf553 C	53	u32 tx_dma_offset;
	54	u32 rx_dma_offset;
	55	enum dma_event_q eventq_no; /* event queue number */
	56	unsigned int codec_fmt;
0d6c9774 TK	57	/*
	58	* Allowing this is more efficient and eliminates left and right swaps
	59	* caused by underruns, but will swap the left and right channels
	60	* when compared to previous behavior.
	61	*/
	62	unsigned enable_channel_combine:1;
1e224f32 TK	63	unsigned sram_size_playback;
1e224f32 TK	64	unsigned sram_size_capture;
25acf553	65
ec637553 RR	66	/*
	67	* If McBSP peripheral gets the clock from an external pin,
	68	* there are three chooses, that are MCBSP_CLKX, MCBSP_CLKR
	69	* and MCBSP_CLKS.
	70	* Depending on different hardware connections it is possible
	71	* to use this setting to change the behaviour of McBSP
	72	* driver. The dm365_clk_input_pin enum is available for dm365
	73	*/
	74	int clk_input_pin;
	75
25acf553 C	76	/* McASP specific fields */
	77	int tdm_slots;
	78	u8 op_mode;
	79	u8 num_serializer;
	80	u8 *serial_dir;
e33ef5e3 C	81	u8 version;
	82	u8 txnumevt;
	83	u8 rxnumevt;
	84	};
	85
	86	enum {
	87	MCASP_VERSION_1 = 0, /* DM646x */
	88	MCASP_VERSION_2, /* DA8xx/OMAPL1x */
25acf553 C	89	};
25acf553 C	90
ec637553 RR	91	enum dm365_clk_input_pin {
	92	MCBSP_CLKR = 0, /* DM365 */
	93	MCBSP_CLKS,
	94	};
	95
25acf553 C	96	#define INACTIVE_MODE 0
	97	#define TX_MODE 1
	98	#define RX_MODE 2
	99
	100	#define DAVINCI_MCASP_IIS_MODE 0
	101	#define DAVINCI_MCASP_DIT_MODE 1
	102
f492ec9f	103	#endif /* __ASM_ARCH_DAVINCI_ASP_H */