projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 55c79a40 MG |
1 | /* |
| 2 | * Chip specific defines for DA8XX/OMAP L1XX SoC | |
| 3 | * | |
| 4 | * Author: Mark A. Greer <mgreer@mvista.com> | |
| 5 | * | |
| 75392dd3 | 6 | * 2007, 2009-2010 (c) MontaVista Software, Inc. This file is licensed under |
| 55c79a40 MG |
7 | * the terms of the GNU General Public License version 2. This program |
| 8 | * is licensed "as is" without any warranty of any kind, whether express | |
| 9 | * or implied. | |
| 10 | */ | |
| 11 | #ifndef __ASM_ARCH_DAVINCI_DA8XX_H | |
| 12 | #define __ASM_ARCH_DAVINCI_DA8XX_H | |
| 13 | ||
| b9e6342b MG |
14 | #include <video/da8xx-fb.h> |
| 15 | ||
| 75392dd3 | 16 | #include <linux/platform_device.h> |
| 8ee2bf9a | 17 | #include <linux/davinci_emac.h> |
| 54ce6883 | 18 | #include <linux/spi/spi.h> |
| 896f66b7 | 19 | #include <linux/platform_data/davinci_asp.h> |
| 154d54a8 | 20 | #include <linux/videodev2.h> |
| 75392dd3 | 21 | |
| 55c79a40 | 22 | #include <mach/serial.h> |
| 044ca015 | 23 | #include <mach/pm.h> |
| 3ad7a42d | 24 | #include <linux/platform_data/edma.h> |
| ec2a0833 AB |
25 | #include <linux/platform_data/i2c-davinci.h> |
| 26 | #include <linux/platform_data/mmc-davinci.h> | |
| 27 | #include <linux/platform_data/usb-davinci.h> | |
| 28 | #include <linux/platform_data/spi-davinci.h> | |
| 8e0d72d2 | 29 | #include <linux/platform_data/uio_pruss.h> |
| 55c79a40 | 30 | |
| 154d54a8 MH |
31 | #include <media/davinci/vpif_types.h> |
| 32 | ||
| d2de0582 SN |
33 | extern void __iomem *da8xx_syscfg0_base; |
| 34 | extern void __iomem *da8xx_syscfg1_base; | |
| 6a28adef | 35 | |
| 39e14550 SN |
36 | /* |
| 37 | * If the DA850/OMAP-L138/AM18x SoC on board is of a higher speed grade | |
| 38 | * (than the regular 300Mhz variant), the board code should set this up | |
| 39 | * with the supported speed before calling da850_register_cpufreq(). | |
| 40 | */ | |
| 41 | extern unsigned int da850_max_speed; | |
| 42 | ||
| 55c79a40 MG |
43 | /* |
| 44 | * The cp_intc interrupt controller for the da8xx isn't in the same | |
| 45 | * chunk of physical memory space as the other registers (like it is | |
| 46 | * on the davincis) so it needs to be mapped separately. It will be | |
| 47 | * mapped early on when the I/O space is mapped and we'll put it just | |
| 48 | * before the I/O space in the processor's virtual memory space. | |
| 49 | */ | |
| 50 | #define DA8XX_CP_INTC_BASE 0xfffee000 | |
| 51 | #define DA8XX_CP_INTC_SIZE SZ_8K | |
| 52 | #define DA8XX_CP_INTC_VIRT (IO_VIRT - DA8XX_CP_INTC_SIZE - SZ_4K) | |
| 53 | ||
| d2de0582 SN |
54 | #define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000) |
| 55 | #define DA8XX_SYSCFG0_VIRT(x) (da8xx_syscfg0_base + (x)) | |
| cd874448 | 56 | #define DA8XX_JTAG_ID_REG 0x18 |
| 5c71d618 RT |
57 | #define DA8XX_HOST1CFG_REG 0x44 |
| 58 | #define DA8XX_CHIPSIG_REG 0x174 | |
| 683b1e1f | 59 | #define DA8XX_CFGCHIP0_REG 0x17c |
| bb170e61 | 60 | #define DA8XX_CFGCHIP1_REG 0x180 |
| 371b53e0 | 61 | #define DA8XX_CFGCHIP2_REG 0x184 |
| 5d36a332 | 62 | #define DA8XX_CFGCHIP3_REG 0x188 |
| 55c79a40 | 63 | |
| d2de0582 SN |
64 | #define DA8XX_SYSCFG1_BASE (IO_PHYS + 0x22C000) |
| 65 | #define DA8XX_SYSCFG1_VIRT(x) (da8xx_syscfg1_base + (x)) | |
| 044ca015 | 66 | #define DA8XX_DEEPSLEEP_REG 0x8 |
| cbb2c961 | 67 | #define DA8XX_PWRDN_REG 0x18 |
| d2de0582 | 68 | |
| bea238f6 RS |
69 | #define DA8XX_PSC0_BASE 0x01c10000 |
| 70 | #define DA8XX_PLL0_BASE 0x01c11000 | |
| bea238f6 RS |
71 | #define DA8XX_TIMER64P0_BASE 0x01c20000 |
| 72 | #define DA8XX_TIMER64P1_BASE 0x01c21000 | |
| 154d54a8 | 73 | #define DA8XX_VPIF_BASE 0x01e17000 |
| bea238f6 RS |
74 | #define DA8XX_GPIO_BASE 0x01e26000 |
| 75 | #define DA8XX_PSC1_BASE 0x01e27000 | |
| 7c5ec609 | 76 | #define DA8XX_AEMIF_CS2_BASE 0x60000000 |
| 38beb929 SR |
77 | #define DA8XX_AEMIF_CS3_BASE 0x62000000 |
| 78 | #define DA8XX_AEMIF_CTL_BASE 0x68000000 | |
| c94472d4 | 79 | #define DA8XX_SHARED_RAM_BASE 0x80000000 |
| 60cd02e1 | 80 | #define DA8XX_ARM_RAM_BASE 0xffff0000 |
| bea238f6 | 81 | |
| b464e3cb LP |
82 | void da830_init(void); |
| 83 | void da850_init(void); | |
| 55c79a40 | 84 | |
| a941c503 RS |
85 | int da830_register_edma(struct edma_rsv_info *rsv); |
| 86 | int da850_register_edma(struct edma_rsv_info *rsv[2]); | |
| 55c79a40 | 87 | int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata); |
| 0273612c | 88 | int da8xx_register_spi_bus(int instance, unsigned num_chipselect); |
| 55c79a40 | 89 | int da8xx_register_watchdog(void); |
| b0ea26e1 | 90 | int da8xx_register_usb20(unsigned mA, unsigned potpgt); |
| e5d3d252 | 91 | int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata); |
| 55c79a40 | 92 | int da8xx_register_emac(void); |
| 8e0d72d2 | 93 | int da8xx_register_uio_pruss(void); |
| b9e6342b | 94 | int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata); |
| 700691f2 | 95 | int da8xx_register_mmcsd0(struct davinci_mmc_config *config); |
| b8241aef | 96 | int da850_register_mmcsd1(struct davinci_mmc_config *config); |
| b464e3cb | 97 | void da8xx_register_mcasp(int id, struct snd_platform_data *pdata); |
| c51df70b | 98 | int da8xx_register_rtc(void); |
| b987c4b2 | 99 | int da850_register_cpufreq(char *async_clk); |
| 1960e693 | 100 | int da8xx_register_cpuidle(void); |
| b464e3cb | 101 | void __iomem *da8xx_get_mem_ctlr(void); |
| 044ca015 | 102 | int da850_register_pm(struct platform_device *pdev); |
| b464e3cb LP |
103 | int da850_register_sata(unsigned long refclkpn); |
| 104 | int da850_register_vpif(void); | |
| 105 | int da850_register_vpif_display | |
| 154d54a8 | 106 | (struct vpif_display_config *display_config); |
| b464e3cb | 107 | int da850_register_vpif_capture |
| 154d54a8 | 108 | (struct vpif_capture_config *capture_config); |
| c6121ddd | 109 | void da8xx_restart(char mode, const char *cmd); |
| 5c71d618 RT |
110 | void da8xx_rproc_reserve_cma(void); |
| 111 | int da8xx_register_rproc(void); | |
| 55c79a40 MG |
112 | |
| 113 | extern struct platform_device da8xx_serial_device; | |
| 114 | extern struct emac_platform_data da8xx_emac_pdata; | |
| b9e6342b MG |
115 | extern struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata; |
| 116 | extern struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata; | |
| 55c79a40 | 117 | |
| c78a5bc2 | 118 | |
| 55c79a40 MG |
119 | extern const short da830_emif25_pins[]; |
| 120 | extern const short da830_spi0_pins[]; | |
| 121 | extern const short da830_spi1_pins[]; | |
| 122 | extern const short da830_mmc_sd_pins[]; | |
| 123 | extern const short da830_uart0_pins[]; | |
| 124 | extern const short da830_uart1_pins[]; | |
| 125 | extern const short da830_uart2_pins[]; | |
| 126 | extern const short da830_usb20_pins[]; | |
| 127 | extern const short da830_usb11_pins[]; | |
| 128 | extern const short da830_uhpi_pins[]; | |
| 129 | extern const short da830_cpgmac_pins[]; | |
| 130 | extern const short da830_emif3c_pins[]; | |
| 131 | extern const short da830_mcasp0_pins[]; | |
| 132 | extern const short da830_mcasp1_pins[]; | |
| 133 | extern const short da830_mcasp2_pins[]; | |
| 134 | extern const short da830_i2c0_pins[]; | |
| 135 | extern const short da830_i2c1_pins[]; | |
| 136 | extern const short da830_lcdcntl_pins[]; | |
| 137 | extern const short da830_pwm_pins[]; | |
| 138 | extern const short da830_ecap0_pins[]; | |
| 139 | extern const short da830_ecap1_pins[]; | |
| 140 | extern const short da830_ecap2_pins[]; | |
| 141 | extern const short da830_eqep0_pins[]; | |
| 142 | extern const short da830_eqep1_pins[]; | |
| 154d54a8 MH |
143 | extern const short da850_vpif_capture_pins[]; |
| 144 | extern const short da850_vpif_display_pins[]; | |
| 55c79a40 | 145 | |
| e1a8d7e2 SR |
146 | extern const short da850_i2c0_pins[]; |
| 147 | extern const short da850_i2c1_pins[]; | |
| 5cbdf276 | 148 | extern const short da850_lcdcntl_pins[]; |
| e1a8d7e2 | 149 | |
| 55c79a40 | 150 | #endif /* __ASM_ARCH_DAVINCI_DA8XX_H */ |