[deliverable/linux.git] / arch / arm / mach-davinci / include / mach / gpio.h

/*
 * TI DaVinci GPIO Support
 *
 * Copyright (c) 2006 David Brownell
 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#ifndef	__DAVINCI_GPIO_H
#define	__DAVINCI_GPIO_H

#include <linux/io.h>
#include <asm-generic/gpio.h>
#include <mach/hardware.h>
#include <mach/irqs.h>

/*
 * basic gpio routines
 *
 * board-specific init should be done by arch/.../.../board-XXX.c (maybe
 * initializing banks together) rather than boot loaders; kexec() won't
 * go through boot loaders.
 *
 * the gpio clock will be turned on when gpios are used, and you may also
 * need to pay attention to PINMUX0 and PINMUX1 to be sure those pins are
 * used as gpios, not with other peripherals.
 *
 * On-chip GPIOs are numbered 0..(DAVINCI_N_GPIO-1).  For documentation,
 * and maybe for later updates, code should write GPIO(N) or:
 *  - GPIOV18(N) for 1.8V pins, N in 0..53; same as GPIO(0)..GPIO(53)
 *  - GPIOV33(N) for 3.3V pins, N in 0..17; same as GPIO(54)..GPIO(70)
 *
 * For GPIO IRQs use gpio_to_irq(GPIO(N)) or gpio_to_irq(GPIOV33(N)) etc
 * for now, that's != GPIO(N)
 *
 * GPIOs can also be on external chips, numbered after the ones built-in
 * to the DaVinci chip.  For now, they won't be usable as IRQ sources.
 */
#define	GPIO(X)		(X)		/* 0 <= X <= 70 */
#define	GPIOV18(X)	(X)		/* 1.8V i/o; 0 <= X <= 53 */
#define	GPIOV33(X)	((X)+54)	/* 3.3V i/o; 0 <= X <= 17 */

struct gpio_controller {
	u32	dir;
	u32	out_data;
	u32	set_data;
	u32	clr_data;
	u32	in_data;
	u32	set_rising;
	u32	clr_rising;
	u32	set_falling;
	u32	clr_falling;
	u32	intstat;
};

/* The __gpio_to_controller() and __gpio_mask() functions inline to constants
 * with constant parameters; or in outlined code they execute at runtime.
 *
 * You'd access the controller directly when reading or writing more than
 * one gpio value at a time, and to support wired logic where the value
 * being driven by the cpu need not match the value read back.
 *
 * These are NOT part of the cross-platform GPIO interface
 */
static inline struct gpio_controller *__iomem
__gpio_to_controller(unsigned gpio)
{
	void *__iomem ptr;

	if (gpio < 32)
		ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x10);
	else if (gpio < 64)
		ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x38);
	else if (gpio < DAVINCI_N_GPIO)
		ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x60);
	else
		ptr = NULL;
	return ptr;
}

static inline u32 __gpio_mask(unsigned gpio)
{
	return 1 << (gpio % 32);
}

/* The get/set/clear functions will inline when called with constant
 * parameters referencing built-in GPIOs, for low-overhead bitbanging.
 *
 * Otherwise, calls with variable parameters or referencing external
 * GPIOs (e.g. on GPIO expander chips) use outlined functions.
 */
static inline void gpio_set_value(unsigned gpio, int value)
{
	if (__builtin_constant_p(value) && gpio < DAVINCI_N_GPIO) {
		struct gpio_controller	*__iomem g;
		u32			mask;

		g = __gpio_to_controller(gpio);
		mask = __gpio_mask(gpio);
		if (value)
			__raw_writel(mask, &g->set_data);
		else
			__raw_writel(mask, &g->clr_data);
		return;
	}

	__gpio_set_value(gpio, value);
}

/* Returns zero or nonzero; works for gpios configured as inputs OR
 * as outputs, at least for built-in GPIOs.
 *
 * NOTE: for built-in GPIOs, changes in reported values are synchronized
 * to the GPIO clock.  This is easily seen after calling gpio_set_value()
 * and then immediately gpio_get_value(), where the gpio_get_value() will
 * return the old value until the GPIO clock ticks and the new value gets
 * latched.
 */
static inline int gpio_get_value(unsigned gpio)
{
	struct gpio_controller	*__iomem g;

	if (!__builtin_constant_p(gpio) || gpio >= DAVINCI_N_GPIO)
		return __gpio_get_value(gpio);

	g = __gpio_to_controller(gpio);
	return __gpio_mask(gpio) & __raw_readl(&g->in_data);
}

static inline int gpio_cansleep(unsigned gpio)
{
	if (__builtin_constant_p(gpio) && gpio < DAVINCI_N_GPIO)
		return 0;
	else
		return __gpio_cansleep(gpio);
}

static inline int gpio_to_irq(unsigned gpio)
{
	if (gpio >= DAVINCI_N_GPIO)
		return -EINVAL;
	return DAVINCI_N_AINTC_IRQ + gpio;
}

static inline int irq_to_gpio(unsigned irq)
{
	/* caller guarantees gpio_to_irq() succeeded */
	return irq - DAVINCI_N_AINTC_IRQ;
}

#endif				/* __DAVINCI_GPIO_H */
Commit	Line	Data
3d9edf09 VB	1	/*
	2	* TI DaVinci GPIO Support
	3	*
	4	* Copyright (c) 2006 David Brownell
	5	* Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*/
	12
	13	#ifndef __DAVINCI_GPIO_H
	14	#define __DAVINCI_GPIO_H
	15
558de8a7	16	#include <linux/io.h>
dce1115b	17	#include <asm-generic/gpio.h>
a09e64fb	18	#include <mach/hardware.h>
80b02c17	19	#include <mach/irqs.h>
558de8a7	20
3d9edf09 VB	21	/*
	22	* basic gpio routines
	23	*
	24	* board-specific init should be done by arch/.../.../board-XXX.c (maybe
	25	* initializing banks together) rather than boot loaders; kexec() won't
	26	* go through boot loaders.
	27	*
	28	* the gpio clock will be turned on when gpios are used, and you may also
	29	* need to pay attention to PINMUX0 and PINMUX1 to be sure those pins are
	30	* used as gpios, not with other peripherals.
	31	*
dce1115b DB	32	* On-chip GPIOs are numbered 0..(DAVINCI_N_GPIO-1). For documentation,
dce1115b DB	33	* and maybe for later updates, code should write GPIO(N) or:
3d9edf09 VB	34	* - GPIOV18(N) for 1.8V pins, N in 0..53; same as GPIO(0)..GPIO(53)
	35	* - GPIOV33(N) for 3.3V pins, N in 0..17; same as GPIO(54)..GPIO(70)
	36	*
	37	* For GPIO IRQs use gpio_to_irq(GPIO(N)) or gpio_to_irq(GPIOV33(N)) etc
	38	* for now, that's != GPIO(N)
dce1115b DB	39	*
	40	* GPIOs can also be on external chips, numbered after the ones built-in
	41	* to the DaVinci chip. For now, they won't be usable as IRQ sources.
3d9edf09 VB	42	*/
	43	#define GPIO(X) (X) /* 0 <= X <= 70 */
	44	#define GPIOV18(X) (X) /* 1.8V i/o; 0 <= X <= 53 */
	45	#define GPIOV33(X) ((X)+54) /* 3.3V i/o; 0 <= X <= 17 */
	46
	47	struct gpio_controller {
	48	u32 dir;
	49	u32 out_data;
	50	u32 set_data;
	51	u32 clr_data;
	52	u32 in_data;
	53	u32 set_rising;
	54	u32 clr_rising;
	55	u32 set_falling;
	56	u32 clr_falling;
	57	u32 intstat;
	58	};
	59
	60	/* The __gpio_to_controller() and __gpio_mask() functions inline to constants
	61	* with constant parameters; or in outlined code they execute at runtime.
	62	*
	63	* You'd access the controller directly when reading or writing more than
	64	* one gpio value at a time, and to support wired logic where the value
	65	* being driven by the cpu need not match the value read back.
	66	*
	67	* These are NOT part of the cross-platform GPIO interface
	68	*/
	69	static inline struct gpio_controller *__iomem
	70	__gpio_to_controller(unsigned gpio)
	71	{
	72	void *__iomem ptr;
	73
	74	if (gpio < 32)
dce1115b	75	ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x10);
3d9edf09	76	else if (gpio < 64)
dce1115b	77	ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x38);
3d9edf09	78	else if (gpio < DAVINCI_N_GPIO)
dce1115b	79	ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x60);
3d9edf09 VB	80	else
	81	ptr = NULL;
	82	return ptr;
	83	}
	84
	85	static inline u32 __gpio_mask(unsigned gpio)
	86	{
	87	return 1 << (gpio % 32);
	88	}
	89
	90	/* The get/set/clear functions will inline when called with constant
dce1115b	91	* parameters referencing built-in GPIOs, for low-overhead bitbanging.
3d9edf09	92	*
dce1115b DB	93	* Otherwise, calls with variable parameters or referencing external
dce1115b DB	94	* GPIOs (e.g. on GPIO expander chips) use outlined functions.
3d9edf09	95	*/
3d9edf09 VB	96	static inline void gpio_set_value(unsigned gpio, int value)
3d9edf09 VB	97	{
dce1115b	98	if (__builtin_constant_p(value) && gpio < DAVINCI_N_GPIO) {
3d9edf09 VB	99	struct gpio_controller *__iomem g;
	100	u32 mask;
	101
3d9edf09 VB	102	g = __gpio_to_controller(gpio);
	103	mask = __gpio_mask(gpio);
	104	if (value)
	105	__raw_writel(mask, &g->set_data);
	106	else
	107	__raw_writel(mask, &g->clr_data);
	108	return;
	109	}
	110
dce1115b	111	__gpio_set_value(gpio, value);
3d9edf09 VB	112	}
	113
	114	/* Returns zero or nonzero; works for gpios configured as inputs OR
dce1115b	115	* as outputs, at least for built-in GPIOs.
3d9edf09	116	*
dce1115b DB	117	* NOTE: for built-in GPIOs, changes in reported values are synchronized
	118	* to the GPIO clock. This is easily seen after calling gpio_set_value()
	119	* and then immediately gpio_get_value(), where the gpio_get_value() will
	120	* return the old value until the GPIO clock ticks and the new value gets
	121	* latched.
3d9edf09	122	*/
3d9edf09 VB	123	static inline int gpio_get_value(unsigned gpio)
3d9edf09 VB	124	{
dce1115b	125	struct gpio_controller *__iomem g;
3d9edf09	126
dce1115b DB	127	if (!__builtin_constant_p(gpio) \|\| gpio >= DAVINCI_N_GPIO)
dce1115b DB	128	return __gpio_get_value(gpio);
3d9edf09 VB	129
3d9edf09 VB	130	g = __gpio_to_controller(gpio);
dce1115b	131	return __gpio_mask(gpio) & __raw_readl(&g->in_data);
3d9edf09 VB	132	}
3d9edf09 VB	133
dce1115b DB	134	static inline int gpio_cansleep(unsigned gpio)
	135	{
	136	if (__builtin_constant_p(gpio) && gpio < DAVINCI_N_GPIO)
	137	return 0;
	138	else
	139	return __gpio_cansleep(gpio);
	140	}
3d9edf09 VB	141
	142	static inline int gpio_to_irq(unsigned gpio)
	143	{
dce1115b DB	144	if (gpio >= DAVINCI_N_GPIO)
dce1115b DB	145	return -EINVAL;
3d9edf09 VB	146	return DAVINCI_N_AINTC_IRQ + gpio;
	147	}
	148
	149	static inline int irq_to_gpio(unsigned irq)
	150	{
dce1115b	151	/* caller guarantees gpio_to_irq() succeeded */
3d9edf09 VB	152	return irq - DAVINCI_N_AINTC_IRQ;
	153	}
	154
	155	#endif /* __DAVINCI_GPIO_H */