[deliverable/linux.git] / arch / arm / mach-davinci / mux.c

/*
 * Utility to set the DAVINCI MUX register from a table in mux.h
 *
 * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
 *
 * Based on linux/arch/arm/plat-omap/mux.c:
 * Copyright (C) 2003 - 2005 Nokia Corporation
 *
 * Written by Tony Lindgren
 *
 * 2007 (c) MontaVista Software, Inc. This file is licensed under
 * the terms of the GNU General Public License version 2. This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 *
 * Copyright (C) 2008 Texas Instruments.
 */
#include <linux/io.h>
#include <linux/module.h>
#include <linux/spinlock.h>

#include <mach/mux.h>
#include <mach/common.h>

static void __iomem *pinmux_base;

/*
 * Sets the DAVINCI MUX register based on the table
 */
int __init_or_module davinci_cfg_reg(const unsigned long index)
{
	static DEFINE_SPINLOCK(mux_spin_lock);
	struct davinci_soc_info *soc_info = &davinci_soc_info;
	unsigned long flags;
	const struct mux_config *cfg;
	unsigned int reg_orig = 0, reg = 0;
	unsigned int mask, warn = 0;

	if (WARN_ON(!soc_info->pinmux_pins))
		return -ENODEV;

	if (!pinmux_base) {
		pinmux_base = ioremap(soc_info->pinmux_base, SZ_4K);
		if (WARN_ON(!pinmux_base))
			return -ENOMEM;
	}

	if (index >= soc_info->pinmux_pins_num) {
		printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
		       index, soc_info->pinmux_pins_num);
		dump_stack();
		return -ENODEV;
	}

	cfg = &soc_info->pinmux_pins[index];

	if (cfg->name == NULL) {
		printk(KERN_ERR "No entry for the specified index\n");
		return -ENODEV;
	}

	/* Update the mux register in question */
	if (cfg->mask) {
		unsigned	tmp1, tmp2;

		spin_lock_irqsave(&mux_spin_lock, flags);
		reg_orig = __raw_readl(pinmux_base + cfg->mux_reg);

		mask = (cfg->mask << cfg->mask_offset);
		tmp1 = reg_orig & mask;
		reg = reg_orig & ~mask;

		tmp2 = (cfg->mode << cfg->mask_offset);
		reg |= tmp2;

		if (tmp1 != tmp2)
			warn = 1;

		__raw_writel(reg, pinmux_base + cfg->mux_reg);
		spin_unlock_irqrestore(&mux_spin_lock, flags);
	}

	if (warn) {
#ifdef CONFIG_DAVINCI_MUX_WARNINGS
		printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
#endif
	}

#ifdef CONFIG_DAVINCI_MUX_DEBUG
	if (cfg->debug || warn) {
		printk(KERN_WARNING "MUX: Setting register %s\n", cfg->name);
		printk(KERN_WARNING "	   %s (0x%08x) = 0x%08x -> 0x%08x\n",
		       cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
	}
#endif

	return 0;
}
EXPORT_SYMBOL(davinci_cfg_reg);

int __init_or_module davinci_cfg_reg_list(const short pins[])
{
	int i, error = -EINVAL;

	if (pins)
		for (i = 0; pins[i] >= 0; i++) {
			error = davinci_cfg_reg(pins[i]);
			if (error)
				break;
		}

	return error;
}
Commit	Line	Data
83f53220	1	/*
5526b3f7	2	* Utility to set the DAVINCI MUX register from a table in mux.h
83f53220 VB	3	*
	4	* Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
	5	*
5526b3f7 KH	6	* Based on linux/arch/arm/plat-omap/mux.c:
	7	* Copyright (C) 2003 - 2005 Nokia Corporation
	8	*
	9	* Written by Tony Lindgren
	10	*
83f53220 VB	11	* 2007 (c) MontaVista Software, Inc. This file is licensed under
	12	* the terms of the GNU General Public License version 2. This program
	13	* is licensed "as is" without any warranty of any kind, whether express
	14	* or implied.
5526b3f7 KH	15	*
5526b3f7 KH	16	* Copyright (C) 2008 Texas Instruments.
83f53220 VB	17	*/
83f53220 VB	18	#include <linux/io.h>
5526b3f7	19	#include <linux/module.h>
83f53220 VB	20	#include <linux/spinlock.h>
83f53220 VB	21
a09e64fb	22	#include <mach/mux.h>
0e585952	23	#include <mach/common.h>
83f53220	24
779b0d53 CC	25	static void __iomem *pinmux_base;
779b0d53 CC	26
5526b3f7 KH	27	/*
	28	* Sets the DAVINCI MUX register based on the table
	29	*/
	30	int __init_or_module davinci_cfg_reg(const unsigned long index)
83f53220	31	{
5526b3f7	32	static DEFINE_SPINLOCK(mux_spin_lock);
0e585952	33	struct davinci_soc_info *soc_info = &davinci_soc_info;
5526b3f7 KH	34	unsigned long flags;
	35	const struct mux_config *cfg;
	36	unsigned int reg_orig = 0, reg = 0;
	37	unsigned int mask, warn = 0;
	38
779b0d53 CC	39	if (WARN_ON(!soc_info->pinmux_pins))
	40	return -ENODEV;
	41
	42	if (!pinmux_base) {
	43	pinmux_base = ioremap(soc_info->pinmux_base, SZ_4K);
	44	if (WARN_ON(!pinmux_base))
	45	return -ENOMEM;
	46	}
5526b3f7	47
0e585952	48	if (index >= soc_info->pinmux_pins_num) {
5526b3f7	49	printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
0e585952	50	index, soc_info->pinmux_pins_num);
5526b3f7 KH	51	dump_stack();
	52	return -ENODEV;
	53	}
	54
0e585952	55	cfg = &soc_info->pinmux_pins[index];
5526b3f7 KH	56
	57	if (cfg->name == NULL) {
	58	printk(KERN_ERR "No entry for the specified index\n");
	59	return -ENODEV;
	60	}
	61
	62	/* Update the mux register in question */
	63	if (cfg->mask) {
	64	unsigned tmp1, tmp2;
	65
	66	spin_lock_irqsave(&mux_spin_lock, flags);
779b0d53	67	reg_orig = __raw_readl(pinmux_base + cfg->mux_reg);
5526b3f7 KH	68
	69	mask = (cfg->mask << cfg->mask_offset);
	70	tmp1 = reg_orig & mask;
	71	reg = reg_orig & ~mask;
	72
	73	tmp2 = (cfg->mode << cfg->mask_offset);
	74	reg \|= tmp2;
	75
	76	if (tmp1 != tmp2)
	77	warn = 1;
	78
779b0d53	79	__raw_writel(reg, pinmux_base + cfg->mux_reg);
5526b3f7 KH	80	spin_unlock_irqrestore(&mux_spin_lock, flags);
	81	}
	82
	83	if (warn) {
	84	#ifdef CONFIG_DAVINCI_MUX_WARNINGS
	85	printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
	86	#endif
	87	}
83f53220	88
5526b3f7 KH	89	#ifdef CONFIG_DAVINCI_MUX_DEBUG
	90	if (cfg->debug \|\| warn) {
	91	printk(KERN_WARNING "MUX: Setting register %s\n", cfg->name);
	92	printk(KERN_WARNING " %s (0x%08x) = 0x%08x -> 0x%08x\n",
	93	cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
83f53220	94	}
5526b3f7	95	#endif
83f53220	96
5526b3f7	97	return 0;
83f53220	98	}
5526b3f7	99	EXPORT_SYMBOL(davinci_cfg_reg);
c96b56c5	100
3821d10a	101	int __init_or_module davinci_cfg_reg_list(const short pins[])
c96b56c5 SR	102	{
	103	int i, error = -EINVAL;
	104
	105	if (pins)
	106	for (i = 0; pins[i] >= 0; i++) {
	107	error = davinci_cfg_reg(pins[i]);
	108	if (error)
	109	break;
	110	}
	111
	112	return error;
	113	}