[deliverable/linux.git] / arch / arm / mach-davinci / psc.c

/*
 * TI DaVinci Power and Sleep Controller (PSC)
 *
 * Copyright (C) 2006 Texas Instruments.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 */
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/io.h>

#include <mach/cputype.h>
#include <mach/hardware.h>
#include <mach/psc.h>
#include <mach/mux.h>

#define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01C41000

/* PSC register offsets */
#define EPCPR		0x070
#define PTCMD		0x120
#define PTSTAT		0x128
#define PDSTAT		0x200
#define PDCTL1		0x304
#define MDSTAT		0x800
#define MDCTL		0xA00

#define MDSTAT_STATE_MASK 0x1f

/* Return nonzero iff the domain's clock is active */
int __init davinci_psc_is_clk_active(unsigned int id)
{
	void __iomem *psc_base = IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE);
	u32 mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);

	/* if clocked, state can be "Enable" or "SyncReset" */
	return mdstat & BIT(12);
}

/* Enable or disable a PSC domain */
void davinci_psc_config(unsigned int domain, unsigned int id, char enable)
{
	u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl;
	void __iomem *psc_base = IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE);
	u32 next_state = enable ? 0x3 : 0x2; /* 0x3 enables, 0x2 disables */

	mdctl = __raw_readl(psc_base + MDCTL + 4 * id);
	mdctl &= ~MDSTAT_STATE_MASK;
	mdctl |= next_state;
	__raw_writel(mdctl, psc_base + MDCTL + 4 * id);

	pdstat = __raw_readl(psc_base + PDSTAT);
	if ((pdstat & 0x00000001) == 0) {
		pdctl1 = __raw_readl(psc_base + PDCTL1);
		pdctl1 |= 0x1;
		__raw_writel(pdctl1, psc_base + PDCTL1);

		ptcmd = 1 << domain;
		__raw_writel(ptcmd, psc_base + PTCMD);

		do {
			epcpr = __raw_readl(psc_base + EPCPR);
		} while ((((epcpr >> domain) & 1) == 0));

		pdctl1 = __raw_readl(psc_base + PDCTL1);
		pdctl1 |= 0x100;
		__raw_writel(pdctl1, psc_base + PDCTL1);

		do {
			ptstat = __raw_readl(psc_base +
					       PTSTAT);
		} while (!(((ptstat >> domain) & 1) == 0));
	} else {
		ptcmd = 1 << domain;
		__raw_writel(ptcmd, psc_base + PTCMD);

		do {
			ptstat = __raw_readl(psc_base + PTSTAT);
		} while (!(((ptstat >> domain) & 1) == 0));
	}

	do {
		mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
	} while (!((mdstat & MDSTAT_STATE_MASK) == next_state));
}
Commit	Line	Data
7c6337e2 KH	1	/*
	2	* TI DaVinci Power and Sleep Controller (PSC)
	3	*
	4	* Copyright (C) 2006 Texas Instruments.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	19	*
	20	*/
	21	#include <linux/kernel.h>
	22	#include <linux/module.h>
	23	#include <linux/init.h>
fced80c7	24	#include <linux/io.h>
7c6337e2	25
c5b736d0	26	#include <mach/cputype.h>
a09e64fb RK	27	#include <mach/hardware.h>
	28	#include <mach/psc.h>
	29	#include <mach/mux.h>
7c6337e2	30
f5c122da KH	31	#define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01C41000
f5c122da KH	32
83f53220 VB	33	/* PSC register offsets */
	34	#define EPCPR 0x070
	35	#define PTCMD 0x120
	36	#define PTSTAT 0x128
	37	#define PDSTAT 0x200
	38	#define PDCTL1 0x304
	39	#define MDSTAT 0x800
	40	#define MDCTL 0xA00
7c6337e2	41
fe277d9b	42	#define MDSTAT_STATE_MASK 0x1f
7c6337e2	43
c5b736d0 KH	44	/* Return nonzero iff the domain's clock is active */
c5b736d0 KH	45	int __init davinci_psc_is_clk_active(unsigned int id)
7c6337e2	46	{
c5b736d0 KH	47	void __iomem *psc_base = IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE);
	48	u32 mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
	49
	50	/* if clocked, state can be "Enable" or "SyncReset" */
	51	return mdstat & BIT(12);
7c6337e2 KH	52	}
	53
	54	/* Enable or disable a PSC domain */
	55	void davinci_psc_config(unsigned int domain, unsigned int id, char enable)
	56	{
fe277d9b	57	u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl;
c5b736d0	58	void __iomem *psc_base = IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE);
fe277d9b	59	u32 next_state = enable ? 0x3 : 0x2; /* 0x3 enables, 0x2 disables */
7c6337e2	60
c5b736d0	61	mdctl = __raw_readl(psc_base + MDCTL + 4 * id);
fe277d9b MG	62	mdctl &= ~MDSTAT_STATE_MASK;
fe277d9b MG	63	mdctl \|= next_state;
c5b736d0	64	__raw_writel(mdctl, psc_base + MDCTL + 4 * id);
83f53220	65
c5b736d0	66	pdstat = __raw_readl(psc_base + PDSTAT);
83f53220	67	if ((pdstat & 0x00000001) == 0) {
c5b736d0	68	pdctl1 = __raw_readl(psc_base + PDCTL1);
83f53220	69	pdctl1 \|= 0x1;
c5b736d0	70	__raw_writel(pdctl1, psc_base + PDCTL1);
83f53220 VB	71
83f53220 VB	72	ptcmd = 1 << domain;
c5b736d0	73	__raw_writel(ptcmd, psc_base + PTCMD);
7c6337e2	74
83f53220	75	do {
c5b736d0	76	epcpr = __raw_readl(psc_base + EPCPR);
83f53220	77	} while ((((epcpr >> domain) & 1) == 0));
7c6337e2	78
c5b736d0	79	pdctl1 = __raw_readl(psc_base + PDCTL1);
83f53220	80	pdctl1 \|= 0x100;
c5b736d0	81	__raw_writel(pdctl1, psc_base + PDCTL1);
83f53220 VB	82
83f53220 VB	83	do {
c5b736d0	84	ptstat = __raw_readl(psc_base +
83f53220 VB	85	PTSTAT);
83f53220 VB	86	} while (!(((ptstat >> domain) & 1) == 0));
7c6337e2	87	} else {
83f53220	88	ptcmd = 1 << domain;
c5b736d0	89	__raw_writel(ptcmd, psc_base + PTCMD);
83f53220 VB	90
83f53220 VB	91	do {
c5b736d0	92	ptstat = __raw_readl(psc_base + PTSTAT);
83f53220	93	} while (!(((ptstat >> domain) & 1) == 0));
7c6337e2 KH	94	}
7c6337e2 KH	95
83f53220	96	do {
c5b736d0	97	mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
fe277d9b	98	} while (!((mdstat & MDSTAT_STATE_MASK) == next_state));
7c6337e2	99	}