Commit | Line | Data |
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7c6337e2 KH |
1 | /* |
2 | * TI DaVinci serial driver | |
3 | * | |
4 | * Copyright (C) 2006 Texas Instruments. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | * | |
20 | */ | |
21 | ||
22 | #include <linux/kernel.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/serial_8250.h> | |
25 | #include <linux/serial_reg.h> | |
26 | #include <linux/platform_device.h> | |
27 | #include <linux/delay.h> | |
28 | #include <linux/clk.h> | |
fced80c7 | 29 | #include <linux/io.h> |
7c6337e2 | 30 | |
a09e64fb | 31 | #include <mach/serial.h> |
617b925f | 32 | #include <mach/cputype.h> |
7c6337e2 | 33 | |
617b925f KH |
34 | static inline unsigned int serial_read_reg(struct plat_serial8250_port *up, |
35 | int offset) | |
7c6337e2 KH |
36 | { |
37 | offset <<= up->regshift; | |
9ee1acef CC |
38 | |
39 | WARN_ONCE(!up->membase, "unmapped read: uart[%d]\n", offset); | |
40 | ||
41 | return (unsigned int)__raw_readl(up->membase + offset); | |
7c6337e2 KH |
42 | } |
43 | ||
617b925f KH |
44 | static inline void serial_write_reg(struct plat_serial8250_port *p, int offset, |
45 | int value) | |
7c6337e2 KH |
46 | { |
47 | offset <<= p->regshift; | |
9ee1acef CC |
48 | |
49 | WARN_ONCE(!p->membase, "unmapped write: uart[%d]\n", offset); | |
50 | ||
51 | __raw_writel(value, p->membase + offset); | |
7c6337e2 KH |
52 | } |
53 | ||
7c6337e2 KH |
54 | static void __init davinci_serial_reset(struct plat_serial8250_port *p) |
55 | { | |
7c6337e2 KH |
56 | unsigned int pwremu = 0; |
57 | ||
617b925f | 58 | serial_write_reg(p, UART_IER, 0); /* disable all interrupts */ |
7c6337e2 | 59 | |
617b925f KH |
60 | /* reset both transmitter and receiver: bits 14,13 = UTRST, URRST */ |
61 | serial_write_reg(p, UART_DAVINCI_PWREMU, pwremu); | |
7c6337e2 KH |
62 | mdelay(10); |
63 | ||
64 | pwremu |= (0x3 << 13); | |
65 | pwremu |= 0x1; | |
617b925f KH |
66 | serial_write_reg(p, UART_DAVINCI_PWREMU, pwremu); |
67 | ||
68 | if (cpu_is_davinci_dm646x()) | |
69 | serial_write_reg(p, UART_DM646X_SCR, | |
70 | UART_DM646X_SCR_TX_WATERMARK); | |
71 | } | |
72 | ||
76d57ce6 SN |
73 | /* Enable UART clock and obtain its rate */ |
74 | int __init davinci_serial_setup_clk(unsigned instance, unsigned int *rate) | |
617b925f | 75 | { |
76d57ce6 SN |
76 | struct clk *clk; |
77 | struct davinci_soc_info *soc_info = &davinci_soc_info; | |
19955c3d | 78 | struct device *dev = &soc_info->serial_dev[instance].dev; |
76d57ce6 | 79 | |
19955c3d | 80 | clk = clk_get(dev, NULL); |
76d57ce6 SN |
81 | if (IS_ERR(clk)) { |
82 | pr_err("%s:%d: failed to get UART%d clock\n", | |
83 | __func__, __LINE__, instance); | |
84 | return PTR_ERR(clk); | |
85 | } | |
86 | ||
87 | clk_prepare_enable(clk); | |
88 | ||
89 | if (rate) | |
90 | *rate = clk_get_rate(clk); | |
91 | ||
92 | return 0; | |
93 | } | |
94 | ||
95 | int __init davinci_serial_init(struct davinci_uart_config *info) | |
96 | { | |
19955c3d | 97 | int i, ret = 0; |
65e866a9 | 98 | struct davinci_soc_info *soc_info = &davinci_soc_info; |
19955c3d MP |
99 | struct device *dev; |
100 | struct plat_serial8250_port *p; | |
617b925f KH |
101 | |
102 | /* | |
103 | * Make sure the serial ports are muxed on at this point. | |
65e866a9 | 104 | * You have to mux them off in device drivers later on if not needed. |
617b925f | 105 | */ |
19955c3d MP |
106 | for (i = 0; soc_info->serial_dev[i].dev.platform_data != NULL; i++) { |
107 | dev = &soc_info->serial_dev[i].dev; | |
108 | p = dev->platform_data; | |
65e866a9 | 109 | if (!(info->enabled_uarts & (1 << i))) |
617b925f | 110 | continue; |
617b925f | 111 | |
19955c3d MP |
112 | ret = platform_device_register(&soc_info->serial_dev[i]); |
113 | if (ret) | |
114 | continue; | |
115 | ||
76d57ce6 SN |
116 | ret = davinci_serial_setup_clk(i, &p->uartclk); |
117 | if (ret) | |
9ee1acef | 118 | continue; |
9ee1acef CC |
119 | |
120 | if (!p->membase && p->mapbase) { | |
121 | p->membase = ioremap(p->mapbase, SZ_4K); | |
122 | ||
123 | if (p->membase) | |
124 | p->flags &= ~UPF_IOREMAP; | |
125 | else | |
126 | pr_err("uart regs ioremap failed\n"); | |
127 | } | |
128 | ||
e2800007 | 129 | if (p->membase && p->type != PORT_AR7) |
9ee1acef | 130 | davinci_serial_reset(p); |
617b925f | 131 | } |
19955c3d | 132 | return ret; |
7c6337e2 | 133 | } |