[deliverable/linux.git] / arch / arm / mach-dove / common.c

/*
 * arch/arm/mach-dove/common.c
 *
 * Core functions for Marvell Dove 88AP510 System On Chip
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/clk-provider.h>
#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_data/dma-mv_xor.h>
#include <linux/platform_data/usb-ehci-orion.h>
#include <linux/platform_device.h>
#include <asm/hardware/cache-tauros2.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <mach/bridge-regs.h>
#include <mach/pm.h>
#include <plat/common.h>
#include <plat/irq.h>
#include <plat/time.h>
#include "common.h"

/* These can go away once Dove uses the mvebu-mbus DT binding */
#define DOVE_MBUS_PCIE0_MEM_TARGET    0x4
#define DOVE_MBUS_PCIE0_MEM_ATTR      0xe8
#define DOVE_MBUS_PCIE0_IO_TARGET     0x4
#define DOVE_MBUS_PCIE0_IO_ATTR       0xe0
#define DOVE_MBUS_PCIE1_MEM_TARGET    0x8
#define DOVE_MBUS_PCIE1_MEM_ATTR      0xe8
#define DOVE_MBUS_PCIE1_IO_TARGET     0x8
#define DOVE_MBUS_PCIE1_IO_ATTR       0xe0
#define DOVE_MBUS_CESA_TARGET         0x3
#define DOVE_MBUS_CESA_ATTR           0x1
#define DOVE_MBUS_BOOTROM_TARGET      0x1
#define DOVE_MBUS_BOOTROM_ATTR        0xfd
#define DOVE_MBUS_SCRATCHPAD_TARGET   0xd
#define DOVE_MBUS_SCRATCHPAD_ATTR     0x0

/*****************************************************************************
 * I/O Address Mapping
 ****************************************************************************/
static struct map_desc dove_io_desc[] __initdata = {
	{
		.virtual	= (unsigned long) DOVE_SB_REGS_VIRT_BASE,
		.pfn		= __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
		.length		= DOVE_SB_REGS_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long) DOVE_NB_REGS_VIRT_BASE,
		.pfn		= __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
		.length		= DOVE_NB_REGS_SIZE,
		.type		= MT_DEVICE,
	},
};

void __init dove_map_io(void)
{
	iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
}

/*****************************************************************************
 * CLK tree
 ****************************************************************************/
static int dove_tclk;

static DEFINE_SPINLOCK(gating_lock);
static struct clk *tclk;

static struct clk __init *dove_register_gate(const char *name,
					     const char *parent, u8 bit_idx)
{
	return clk_register_gate(NULL, name, parent, 0,
				 (void __iomem *)CLOCK_GATING_CONTROL,
				 bit_idx, 0, &gating_lock);
}

static void __init dove_clk_init(void)
{
	struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1;
	struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma;
	struct clk *xor0, *xor1, *ge, *gephy;

	tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
				       dove_tclk);

	usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0);
	usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1);
	sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA);
	pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0);
	pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1);
	sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0);
	sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1);
	nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND);
	camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA);
	i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0);
	i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1);
	crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO);
	ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97);
	pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA);
	xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0);
	xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1);
	gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY);
	ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE);

	orion_clkdev_add(NULL, "orion_spi.0", tclk);
	orion_clkdev_add(NULL, "orion_spi.1", tclk);
	orion_clkdev_add(NULL, "orion_wdt", tclk);
	orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk);

	orion_clkdev_add(NULL, "orion-ehci.0", usb0);
	orion_clkdev_add(NULL, "orion-ehci.1", usb1);
	orion_clkdev_add(NULL, "mv643xx_eth_port.0", ge);
	orion_clkdev_add(NULL, "sata_mv.0", sata);
	orion_clkdev_add("0", "pcie", pex0);
	orion_clkdev_add("1", "pcie", pex1);
	orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
	orion_clkdev_add(NULL, "sdhci-dove.1", sdio1);
	orion_clkdev_add(NULL, "orion_nand", nand);
	orion_clkdev_add(NULL, "cafe1000-ccic.0", camera);
	orion_clkdev_add(NULL, "mvebu-audio.0", i2s0);
	orion_clkdev_add(NULL, "mvebu-audio.1", i2s1);
	orion_clkdev_add(NULL, "mv_crypto", crypto);
	orion_clkdev_add(NULL, "dove-ac97", ac97);
	orion_clkdev_add(NULL, "dove-pdma", pdma);
	orion_clkdev_add(NULL, MV_XOR_NAME ".0", xor0);
	orion_clkdev_add(NULL, MV_XOR_NAME ".1", xor1);
}

/*****************************************************************************
 * EHCI0
 ****************************************************************************/
void __init dove_ehci0_init(void)
{
	orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA);
}

/*****************************************************************************
 * EHCI1
 ****************************************************************************/
void __init dove_ehci1_init(void)
{
	orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
}

/*****************************************************************************
 * GE00
 ****************************************************************************/
void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
{
	orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE,
			IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR,
			1600);
}

/*****************************************************************************
 * SoC RTC
 ****************************************************************************/
static void __init dove_rtc_init(void)
{
	orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
}

/*****************************************************************************
 * SATA
 ****************************************************************************/
void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
{
	orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);

}

/*****************************************************************************
 * UART0
 ****************************************************************************/
void __init dove_uart0_init(void)
{
	orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
			 IRQ_DOVE_UART_0, tclk);
}

/*****************************************************************************
 * UART1
 ****************************************************************************/
void __init dove_uart1_init(void)
{
	orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
			 IRQ_DOVE_UART_1, tclk);
}

/*****************************************************************************
 * UART2
 ****************************************************************************/
void __init dove_uart2_init(void)
{
	orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
			 IRQ_DOVE_UART_2, tclk);
}

/*****************************************************************************
 * UART3
 ****************************************************************************/
void __init dove_uart3_init(void)
{
	orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
			 IRQ_DOVE_UART_3, tclk);
}

/*****************************************************************************
 * SPI
 ****************************************************************************/
void __init dove_spi0_init(void)
{
	orion_spi_init(DOVE_SPI0_PHYS_BASE);
}

void __init dove_spi1_init(void)
{
	orion_spi_1_init(DOVE_SPI1_PHYS_BASE);
}

/*****************************************************************************
 * I2C
 ****************************************************************************/
void __init dove_i2c_init(void)
{
	orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10);
}

/*****************************************************************************
 * Time handling
 ****************************************************************************/
void __init dove_init_early(void)
{
	orion_time_set_base(TIMER_VIRT_BASE);
	mvebu_mbus_init("marvell,dove-mbus",
			BRIDGE_WINS_BASE, BRIDGE_WINS_SZ,
			DOVE_MC_WINS_BASE, DOVE_MC_WINS_SZ);
}

static int __init dove_find_tclk(void)
{
	return 166666667;
}

void __init dove_timer_init(void)
{
	dove_tclk = dove_find_tclk();
	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
			IRQ_DOVE_BRIDGE, dove_tclk);
}

/*****************************************************************************
 * XOR 0
 ****************************************************************************/
static void __init dove_xor0_init(void)
{
	orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
			IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
}

/*****************************************************************************
 * XOR 1
 ****************************************************************************/
static void __init dove_xor1_init(void)
{
	orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE,
			IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11);
}

/*****************************************************************************
 * SDIO
 ****************************************************************************/
static u64 sdio_dmamask = DMA_BIT_MASK(32);

static struct resource dove_sdio0_resources[] = {
	{
		.start	= DOVE_SDIO0_PHYS_BASE,
		.end	= DOVE_SDIO0_PHYS_BASE + 0xff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_DOVE_SDIO0,
		.end	= IRQ_DOVE_SDIO0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dove_sdio0 = {
	.name		= "sdhci-dove",
	.id		= 0,
	.dev		= {
		.dma_mask		= &sdio_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
	.resource	= dove_sdio0_resources,
	.num_resources	= ARRAY_SIZE(dove_sdio0_resources),
};

void __init dove_sdio0_init(void)
{
	platform_device_register(&dove_sdio0);
}

static struct resource dove_sdio1_resources[] = {
	{
		.start	= DOVE_SDIO1_PHYS_BASE,
		.end	= DOVE_SDIO1_PHYS_BASE + 0xff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_DOVE_SDIO1,
		.end	= IRQ_DOVE_SDIO1,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dove_sdio1 = {
	.name		= "sdhci-dove",
	.id		= 1,
	.dev		= {
		.dma_mask		= &sdio_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
	.resource	= dove_sdio1_resources,
	.num_resources	= ARRAY_SIZE(dove_sdio1_resources),
};

void __init dove_sdio1_init(void)
{
	platform_device_register(&dove_sdio1);
}

void __init dove_setup_cpu_wins(void)
{
	/*
	 * The PCIe windows will no longer be statically allocated
	 * here once Dove is migrated to the pci-mvebu driver. The
	 * non-PCIe windows will no longer be created here once Dove
	 * fully moves to DT.
	 */
	mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE0_IO_TARGET,
					  DOVE_MBUS_PCIE0_IO_ATTR,
					  DOVE_PCIE0_IO_PHYS_BASE,
					  DOVE_PCIE0_IO_SIZE,
					  DOVE_PCIE0_IO_BUS_BASE);
	mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE1_IO_TARGET,
					  DOVE_MBUS_PCIE1_IO_ATTR,
					  DOVE_PCIE1_IO_PHYS_BASE,
					  DOVE_PCIE1_IO_SIZE,
					  DOVE_PCIE1_IO_BUS_BASE);
	mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE0_MEM_TARGET,
				    DOVE_MBUS_PCIE0_MEM_ATTR,
				    DOVE_PCIE0_MEM_PHYS_BASE,
				    DOVE_PCIE0_MEM_SIZE);
	mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE1_MEM_TARGET,
				    DOVE_MBUS_PCIE1_MEM_ATTR,
				    DOVE_PCIE1_MEM_PHYS_BASE,
				    DOVE_PCIE1_MEM_SIZE);
	mvebu_mbus_add_window_by_id(DOVE_MBUS_CESA_TARGET,
				    DOVE_MBUS_CESA_ATTR,
				    DOVE_CESA_PHYS_BASE,
				    DOVE_CESA_SIZE);
	mvebu_mbus_add_window_by_id(DOVE_MBUS_BOOTROM_TARGET,
				    DOVE_MBUS_BOOTROM_ATTR,
				    DOVE_BOOTROM_PHYS_BASE,
				    DOVE_BOOTROM_SIZE);
	mvebu_mbus_add_window_by_id(DOVE_MBUS_SCRATCHPAD_TARGET,
				    DOVE_MBUS_SCRATCHPAD_ATTR,
				    DOVE_SCRATCHPAD_PHYS_BASE,
				    DOVE_SCRATCHPAD_SIZE);
}

void __init dove_init(void)
{
	pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
		(dove_tclk + 499999) / 1000000);

#ifdef CONFIG_CACHE_TAUROS2
	tauros2_init(0);
#endif
	dove_setup_cpu_wins();

	/* Setup root of clk tree */
	dove_clk_init();

	/* internal devices that every board has */
	dove_rtc_init();
	dove_xor0_init();
	dove_xor1_init();
}

void dove_restart(enum reboot_mode mode, const char *cmd)
{
	/*
	 * Enable soft reset to assert RSTOUTn.
	 */
	writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);

	/*
	 * Assert soft reset.
	 */
	writel(SOFT_RESET, SYSTEM_SOFT_RESET);

	while (1)
		;
}
Commit	Line	Data
edabd38e SB	1	/*
	2	* arch/arm/mach-dove/common.c
	3	*
	4	* Core functions for Marvell Dove 88AP510 System On Chip
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10
2f129bf4	11	#include <linux/clk-provider.h>
b3af7a1f SH	12	#include <linux/dma-mapping.h>
b3af7a1f SH	13	#include <linux/init.h>
81d2ef7c SH	14	#include <linux/of.h>
81d2ef7c SH	15	#include <linux/of_platform.h>
b3af7a1f SH	16	#include <linux/platform_data/dma-mv_xor.h>
	17	#include <linux/platform_data/usb-ehci-orion.h>
	18	#include <linux/platform_device.h>
573a652f	19	#include <asm/hardware/cache-tauros2.h>
b3af7a1f	20	#include <asm/mach/arch.h>
edabd38e SB	21	#include <asm/mach/map.h>
edabd38e SB	22	#include <asm/mach/time.h>
edabd38e	23	#include <mach/bridge-regs.h>
b3af7a1f	24	#include <mach/pm.h>
28a2b450	25	#include <plat/common.h>
b3af7a1f SH	26	#include <plat/irq.h>
b3af7a1f SH	27	#include <plat/time.h>
edabd38e SB	28	#include "common.h"
edabd38e SB	29
89a7fbfb TP	30	/* These can go away once Dove uses the mvebu-mbus DT binding */
	31	#define DOVE_MBUS_PCIE0_MEM_TARGET 0x4
	32	#define DOVE_MBUS_PCIE0_MEM_ATTR 0xe8
	33	#define DOVE_MBUS_PCIE0_IO_TARGET 0x4
	34	#define DOVE_MBUS_PCIE0_IO_ATTR 0xe0
	35	#define DOVE_MBUS_PCIE1_MEM_TARGET 0x8
	36	#define DOVE_MBUS_PCIE1_MEM_ATTR 0xe8
	37	#define DOVE_MBUS_PCIE1_IO_TARGET 0x8
	38	#define DOVE_MBUS_PCIE1_IO_ATTR 0xe0
	39	#define DOVE_MBUS_CESA_TARGET 0x3
	40	#define DOVE_MBUS_CESA_ATTR 0x1
	41	#define DOVE_MBUS_BOOTROM_TARGET 0x1
	42	#define DOVE_MBUS_BOOTROM_ATTR 0xfd
	43	#define DOVE_MBUS_SCRATCHPAD_TARGET 0xd
	44	#define DOVE_MBUS_SCRATCHPAD_ATTR 0x0
	45
edabd38e SB	46	/*****************************************************************************
	47	* I/O Address Mapping
	48	****************************************************************************/
	49	static struct map_desc dove_io_desc[] __initdata = {
	50	{
c3c5a281	51	.virtual = (unsigned long) DOVE_SB_REGS_VIRT_BASE,
edabd38e SB	52	.pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
	53	.length = DOVE_SB_REGS_SIZE,
	54	.type = MT_DEVICE,
	55	}, {
c3c5a281	56	.virtual = (unsigned long) DOVE_NB_REGS_VIRT_BASE,
edabd38e SB	57	.pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
	58	.length = DOVE_NB_REGS_SIZE,
	59	.type = MT_DEVICE,
edabd38e SB	60	},
	61	};
	62
	63	void __init dove_map_io(void)
	64	{
	65	iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
	66	}
	67
2f129bf4 AL	68	/*****************************************************************************
	69	* CLK tree
	70	****************************************************************************/
5817d10b	71	static int dove_tclk;
52167471 SH	72
52167471 SH	73	static DEFINE_SPINLOCK(gating_lock);
2f129bf4 AL	74	static struct clk *tclk;
2f129bf4 AL	75
52167471 SH	76	static struct clk __init dove_register_gate(const char name,
52167471 SH	77	const char *parent, u8 bit_idx)
2f129bf4	78	{
52167471 SH	79	return clk_register_gate(NULL, name, parent, 0,
	80	(void __iomem *)CLOCK_GATING_CONTROL,
	81	bit_idx, 0, &gating_lock);
	82	}
	83
5817d10b	84	static void __init dove_clk_init(void)
2f129bf4	85	{
52167471 SH	86	struct clk usb0, usb1, sata, pex0, pex1, sdio0, *sdio1;
	87	struct clk nand, camera, i2s0, i2s1, crypto, ac97, *pdma;
	88	struct clk xor0, xor1, ge, gephy;
4574b886	89
2f129bf4	90	tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
5817d10b	91	dove_tclk);
4574b886	92
52167471 SH	93	usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0);
	94	usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1);
	95	sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA);
	96	pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0);
	97	pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1);
	98	sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0);
	99	sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1);
	100	nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND);
	101	camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA);
	102	i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0);
	103	i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1);
	104	crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO);
	105	ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97);
	106	pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA);
	107	xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0);
	108	xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1);
	109	gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY);
	110	ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE);
	111
	112	orion_clkdev_add(NULL, "orion_spi.0", tclk);
	113	orion_clkdev_add(NULL, "orion_spi.1", tclk);
	114	orion_clkdev_add(NULL, "orion_wdt", tclk);
	115	orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk);
	116
	117	orion_clkdev_add(NULL, "orion-ehci.0", usb0);
	118	orion_clkdev_add(NULL, "orion-ehci.1", usb1);
3fbcd3d0 SH	119	orion_clkdev_add(NULL, "mv643xx_eth_port.0", ge);
3fbcd3d0 SH	120	orion_clkdev_add(NULL, "sata_mv.0", sata);
52167471 SH	121	orion_clkdev_add("0", "pcie", pex0);
	122	orion_clkdev_add("1", "pcie", pex1);
	123	orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
	124	orion_clkdev_add(NULL, "sdhci-dove.1", sdio1);
	125	orion_clkdev_add(NULL, "orion_nand", nand);
	126	orion_clkdev_add(NULL, "cafe1000-ccic.0", camera);
64ddf1f8 RK	127	orion_clkdev_add(NULL, "mvebu-audio.0", i2s0);
64ddf1f8 RK	128	orion_clkdev_add(NULL, "mvebu-audio.1", i2s1);
52167471 SH	129	orion_clkdev_add(NULL, "mv_crypto", crypto);
	130	orion_clkdev_add(NULL, "dove-ac97", ac97);
	131	orion_clkdev_add(NULL, "dove-pdma", pdma);
0dddee7a TP	132	orion_clkdev_add(NULL, MV_XOR_NAME ".0", xor0);
0dddee7a TP	133	orion_clkdev_add(NULL, MV_XOR_NAME ".1", xor1);
2f129bf4 AL	134	}
2f129bf4 AL	135
edabd38e SB	136	/*****************************************************************************
	137	* EHCI0
	138	****************************************************************************/
edabd38e SB	139	void __init dove_ehci0_init(void)
edabd38e SB	140	{
72053353	141	orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA);
edabd38e SB	142	}
	143
	144	/*****************************************************************************
	145	* EHCI1
	146	****************************************************************************/
edabd38e SB	147	void __init dove_ehci1_init(void)
edabd38e SB	148	{
db33f4de	149	orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
edabd38e SB	150	}
	151
	152	/*****************************************************************************
	153	* GE00
	154	****************************************************************************/
edabd38e SB	155	void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
edabd38e SB	156	{
30e0f580	157	orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE,
58569aee APR	158	IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR,
58569aee APR	159	1600);
edabd38e SB	160	}
	161
	162	/*****************************************************************************
	163	* SoC RTC
	164	****************************************************************************/
887c206a	165	static void __init dove_rtc_init(void)
edabd38e	166	{
f6eaccb3	167	orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
edabd38e SB	168	}
	169
	170	/*****************************************************************************
	171	* SATA
	172	****************************************************************************/
edabd38e SB	173	void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
edabd38e SB	174	{
db33f4de	175	orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);
9e613f8a	176
edabd38e SB	177	}
	178
	179	/*****************************************************************************
	180	* UART0
	181	****************************************************************************/
edabd38e SB	182	void __init dove_uart0_init(void)
edabd38e SB	183	{
28a2b450	184	orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
74c33576	185	IRQ_DOVE_UART_0, tclk);
edabd38e SB	186	}
	187
	188	/*****************************************************************************
	189	* UART1
	190	****************************************************************************/
edabd38e SB	191	void __init dove_uart1_init(void)
edabd38e SB	192	{
28a2b450	193	orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
74c33576	194	IRQ_DOVE_UART_1, tclk);
edabd38e SB	195	}
	196
	197	/*****************************************************************************
	198	* UART2
	199	****************************************************************************/
edabd38e SB	200	void __init dove_uart2_init(void)
edabd38e SB	201	{
28a2b450	202	orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
74c33576	203	IRQ_DOVE_UART_2, tclk);
edabd38e SB	204	}
	205
	206	/*****************************************************************************
	207	* UART3
	208	****************************************************************************/
edabd38e SB	209	void __init dove_uart3_init(void)
edabd38e SB	210	{
28a2b450	211	orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
74c33576	212	IRQ_DOVE_UART_3, tclk);
edabd38e SB	213	}
	214
	215	/*****************************************************************************
980f9f60	216	* SPI
edabd38e	217	****************************************************************************/
edabd38e SB	218	void __init dove_spi0_init(void)
edabd38e SB	219	{
4574b886	220	orion_spi_init(DOVE_SPI0_PHYS_BASE);
edabd38e SB	221	}
edabd38e SB	222
edabd38e SB	223	void __init dove_spi1_init(void)
edabd38e SB	224	{
4574b886	225	orion_spi_1_init(DOVE_SPI1_PHYS_BASE);
edabd38e SB	226	}
	227
	228	/*****************************************************************************
	229	* I2C
	230	****************************************************************************/
edabd38e SB	231	void __init dove_i2c_init(void)
edabd38e SB	232	{
aac7ffa3	233	orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10);
edabd38e SB	234	}
	235
	236	/*****************************************************************************
	237	* Time handling
	238	****************************************************************************/
4ee1f6b5 LB	239	void __init dove_init_early(void)
	240	{
	241	orion_time_set_base(TIMER_VIRT_BASE);
7d554902 TP	242	mvebu_mbus_init("marvell,dove-mbus",
	243	BRIDGE_WINS_BASE, BRIDGE_WINS_SZ,
	244	DOVE_MC_WINS_BASE, DOVE_MC_WINS_SZ);
4ee1f6b5 LB	245	}
4ee1f6b5 LB	246
5817d10b	247	static int __init dove_find_tclk(void)
edabd38e	248	{
edabd38e SB	249	return 166666667;
	250	}
	251
6bb27d73	252	void __init dove_timer_init(void)
edabd38e	253	{
5817d10b	254	dove_tclk = dove_find_tclk();
4ee1f6b5	255	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
5817d10b	256	IRQ_DOVE_BRIDGE, dove_tclk);
edabd38e SB	257	}
edabd38e SB	258
edabd38e SB	259	/*****************************************************************************
	260	* XOR 0
	261	****************************************************************************/
887c206a	262	static void __init dove_xor0_init(void)
edabd38e	263	{
db33f4de	264	orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
ee962723	265	IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
edabd38e SB	266	}
	267
	268	/*****************************************************************************
	269	* XOR 1
	270	****************************************************************************/
887c206a	271	static void __init dove_xor1_init(void)
edabd38e	272	{
ee962723 AL	273	orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE,
ee962723 AL	274	IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11);
edabd38e SB	275	}
edabd38e SB	276
16bc90af SB	277	/*****************************************************************************
	278	* SDIO
	279	****************************************************************************/
	280	static u64 sdio_dmamask = DMA_BIT_MASK(32);
	281
	282	static struct resource dove_sdio0_resources[] = {
	283	{
	284	.start = DOVE_SDIO0_PHYS_BASE,
	285	.end = DOVE_SDIO0_PHYS_BASE + 0xff,
	286	.flags = IORESOURCE_MEM,
	287	}, {
	288	.start = IRQ_DOVE_SDIO0,
	289	.end = IRQ_DOVE_SDIO0,
	290	.flags = IORESOURCE_IRQ,
	291	},
	292	};
	293
	294	static struct platform_device dove_sdio0 = {
930e2fe7	295	.name = "sdhci-dove",
16bc90af SB	296	.id = 0,
	297	.dev = {
	298	.dma_mask = &sdio_dmamask,
	299	.coherent_dma_mask = DMA_BIT_MASK(32),
	300	},
	301	.resource = dove_sdio0_resources,
	302	.num_resources = ARRAY_SIZE(dove_sdio0_resources),
	303	};
	304
	305	void __init dove_sdio0_init(void)
	306	{
	307	platform_device_register(&dove_sdio0);
	308	}
	309
	310	static struct resource dove_sdio1_resources[] = {
	311	{
	312	.start = DOVE_SDIO1_PHYS_BASE,
	313	.end = DOVE_SDIO1_PHYS_BASE + 0xff,
	314	.flags = IORESOURCE_MEM,
	315	}, {
	316	.start = IRQ_DOVE_SDIO1,
	317	.end = IRQ_DOVE_SDIO1,
	318	.flags = IORESOURCE_IRQ,
	319	},
	320	};
	321
	322	static struct platform_device dove_sdio1 = {
930e2fe7	323	.name = "sdhci-dove",
16bc90af SB	324	.id = 1,
	325	.dev = {
	326	.dma_mask = &sdio_dmamask,
	327	.coherent_dma_mask = DMA_BIT_MASK(32),
	328	},
	329	.resource = dove_sdio1_resources,
	330	.num_resources = ARRAY_SIZE(dove_sdio1_resources),
	331	};
	332
	333	void __init dove_sdio1_init(void)
	334	{
	335	platform_device_register(&dove_sdio1);
	336	}
	337
7d554902 TP	338	void __init dove_setup_cpu_wins(void)
	339	{
	340	/*
	341	* The PCIe windows will no longer be statically allocated
89a7fbfb TP	342	* here once Dove is migrated to the pci-mvebu driver. The
	343	* non-PCIe windows will no longer be created here once Dove
	344	* fully moves to DT.
7d554902	345	*/
89a7fbfb TP	346	mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE0_IO_TARGET,
89a7fbfb TP	347	DOVE_MBUS_PCIE0_IO_ATTR,
7d554902 TP	348	DOVE_PCIE0_IO_PHYS_BASE,
7d554902 TP	349	DOVE_PCIE0_IO_SIZE,
89a7fbfb TP	350	DOVE_PCIE0_IO_BUS_BASE);
	351	mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE1_IO_TARGET,
	352	DOVE_MBUS_PCIE1_IO_ATTR,
7d554902 TP	353	DOVE_PCIE1_IO_PHYS_BASE,
7d554902 TP	354	DOVE_PCIE1_IO_SIZE,
89a7fbfb TP	355	DOVE_PCIE1_IO_BUS_BASE);
	356	mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE0_MEM_TARGET,
	357	DOVE_MBUS_PCIE0_MEM_ATTR,
	358	DOVE_PCIE0_MEM_PHYS_BASE,
	359	DOVE_PCIE0_MEM_SIZE);
	360	mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE1_MEM_TARGET,
	361	DOVE_MBUS_PCIE1_MEM_ATTR,
	362	DOVE_PCIE1_MEM_PHYS_BASE,
	363	DOVE_PCIE1_MEM_SIZE);
	364	mvebu_mbus_add_window_by_id(DOVE_MBUS_CESA_TARGET,
	365	DOVE_MBUS_CESA_ATTR,
	366	DOVE_CESA_PHYS_BASE,
	367	DOVE_CESA_SIZE);
	368	mvebu_mbus_add_window_by_id(DOVE_MBUS_BOOTROM_TARGET,
	369	DOVE_MBUS_BOOTROM_ATTR,
	370	DOVE_BOOTROM_PHYS_BASE,
	371	DOVE_BOOTROM_SIZE);
	372	mvebu_mbus_add_window_by_id(DOVE_MBUS_SCRATCHPAD_TARGET,
	373	DOVE_MBUS_SCRATCHPAD_ATTR,
	374	DOVE_SCRATCHPAD_PHYS_BASE,
	375	DOVE_SCRATCHPAD_SIZE);
7d554902 TP	376	}
7d554902 TP	377
edabd38e SB	378	void __init dove_init(void)
edabd38e SB	379	{
5817d10b SH	380	pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
5817d10b SH	381	(dove_tclk + 499999) / 1000000);
edabd38e	382
573a652f	383	#ifdef CONFIG_CACHE_TAUROS2
5cc58157	384	tauros2_init(0);
573a652f	385	#endif
7d554902	386	dove_setup_cpu_wins();
edabd38e	387
2f129bf4	388	/* Setup root of clk tree */
5817d10b	389	dove_clk_init();
2f129bf4	390
edabd38e SB	391	/* internal devices that every board has */
	392	dove_rtc_init();
	393	dove_xor0_init();
	394	dove_xor1_init();
	395	}
6ca6ff97	396
7b6d864b	397	void dove_restart(enum reboot_mode mode, const char *cmd)
6ca6ff97 RK	398	{
	399	/*
	400	* Enable soft reset to assert RSTOUTn.
	401	*/
	402	writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
	403
	404	/*
	405	* Assert soft reset.
	406	*/
	407	writel(SOFT_RESET, SYSTEM_SOFT_RESET);
	408
	409	while (1)
	410	;
	411	}