[deliverable/linux.git] / arch / arm / mach-dove / common.c

/*
 * arch/arm/mach-dove/common.c
 *
 * Core functions for Marvell Dove 88AP510 System On Chip
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/pci.h>
#include <linux/serial_8250.h>
#include <linux/clk.h>
#include <linux/mbus.h>
#include <linux/mv643xx_eth.h>
#include <linux/mv643xx_i2c.h>
#include <linux/ata_platform.h>
#include <linux/serial_8250.h>
#include <linux/spi/orion_spi.h>
#include <linux/gpio.h>
#include <asm/page.h>
#include <asm/setup.h>
#include <asm/timex.h>
#include <asm/hardware/cache-tauros2.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/mach/pci.h>
#include <mach/dove.h>
#include <mach/bridge-regs.h>
#include <asm/mach/arch.h>
#include <linux/irq.h>
#include <plat/mv_xor.h>
#include <plat/ehci-orion.h>
#include <plat/time.h>
#include <plat/common.h>
#include "common.h"

static int get_tclk(void);

/*****************************************************************************
 * I/O Address Mapping
 ****************************************************************************/
static struct map_desc dove_io_desc[] __initdata = {
	{
		.virtual	= DOVE_SB_REGS_VIRT_BASE,
		.pfn		= __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
		.length		= DOVE_SB_REGS_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= DOVE_NB_REGS_VIRT_BASE,
		.pfn		= __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
		.length		= DOVE_NB_REGS_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= DOVE_PCIE0_IO_VIRT_BASE,
		.pfn		= __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE),
		.length		= DOVE_PCIE0_IO_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= DOVE_PCIE1_IO_VIRT_BASE,
		.pfn		= __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE),
		.length		= DOVE_PCIE1_IO_SIZE,
		.type		= MT_DEVICE,
	},
};

void __init dove_map_io(void)
{
	iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
}

/*****************************************************************************
 * EHCI
 ****************************************************************************/
static struct orion_ehci_data dove_ehci_data = {
	.dram		= &dove_mbus_dram_info,
	.phy_version	= EHCI_PHY_NA,
};

static u64 ehci_dmamask = DMA_BIT_MASK(32);

/*****************************************************************************
 * EHCI0
 ****************************************************************************/
static struct resource dove_ehci0_resources[] = {
	{
		.start	= DOVE_USB0_PHYS_BASE,
		.end	= DOVE_USB0_PHYS_BASE + SZ_4K - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_DOVE_USB0,
		.end	= IRQ_DOVE_USB0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dove_ehci0 = {
	.name		= "orion-ehci",
	.id		= 0,
	.dev		= {
		.dma_mask		= &ehci_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
		.platform_data		= &dove_ehci_data,
	},
	.resource	= dove_ehci0_resources,
	.num_resources	= ARRAY_SIZE(dove_ehci0_resources),
};

void __init dove_ehci0_init(void)
{
	platform_device_register(&dove_ehci0);
}

/*****************************************************************************
 * EHCI1
 ****************************************************************************/
static struct resource dove_ehci1_resources[] = {
	{
		.start	= DOVE_USB1_PHYS_BASE,
		.end	= DOVE_USB1_PHYS_BASE + SZ_4K - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_DOVE_USB1,
		.end	= IRQ_DOVE_USB1,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dove_ehci1 = {
	.name		= "orion-ehci",
	.id		= 1,
	.dev		= {
		.dma_mask		= &ehci_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
		.platform_data		= &dove_ehci_data,
	},
	.resource	= dove_ehci1_resources,
	.num_resources	= ARRAY_SIZE(dove_ehci1_resources),
};

void __init dove_ehci1_init(void)
{
	platform_device_register(&dove_ehci1);
}

/*****************************************************************************
 * GE00
 ****************************************************************************/
struct mv643xx_eth_shared_platform_data dove_ge00_shared_data = {
	.t_clk		= 0,
	.dram		= &dove_mbus_dram_info,
};

static struct resource dove_ge00_shared_resources[] = {
	{
		.name	= "ge00 base",
		.start	= DOVE_GE00_PHYS_BASE + 0x2000,
		.end	= DOVE_GE00_PHYS_BASE + SZ_16K - 1,
		.flags	= IORESOURCE_MEM,
	},
};

static struct platform_device dove_ge00_shared = {
	.name		= MV643XX_ETH_SHARED_NAME,
	.id		= 0,
	.dev		= {
		.platform_data	= &dove_ge00_shared_data,
	},
	.num_resources	= 1,
	.resource	= dove_ge00_shared_resources,
};

static struct resource dove_ge00_resources[] = {
	{
		.name	= "ge00 irq",
		.start	= IRQ_DOVE_GE00_SUM,
		.end	= IRQ_DOVE_GE00_SUM,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dove_ge00 = {
	.name		= MV643XX_ETH_NAME,
	.id		= 0,
	.num_resources	= 1,
	.resource	= dove_ge00_resources,
	.dev		= {
		.coherent_dma_mask	= 0xffffffff,
	},
};

void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
{
	eth_data->shared = &dove_ge00_shared;
	dove_ge00.dev.platform_data = eth_data;

	platform_device_register(&dove_ge00_shared);
	platform_device_register(&dove_ge00);
}

/*****************************************************************************
 * SoC RTC
 ****************************************************************************/
void __init dove_rtc_init(void)
{
	orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
}

/*****************************************************************************
 * SATA
 ****************************************************************************/
static struct resource dove_sata_resources[] = {
	{
		.name	= "sata base",
		.start	= DOVE_SATA_PHYS_BASE,
		.end	= DOVE_SATA_PHYS_BASE + 0x5000 - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.name	= "sata irq",
		.start	= IRQ_DOVE_SATA,
		.end	= IRQ_DOVE_SATA,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dove_sata = {
	.name		= "sata_mv",
	.id		= 0,
	.dev		= {
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
	.num_resources	= ARRAY_SIZE(dove_sata_resources),
	.resource	= dove_sata_resources,
};

void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
{
	sata_data->dram = &dove_mbus_dram_info;
	dove_sata.dev.platform_data = sata_data;
	platform_device_register(&dove_sata);
}

/*****************************************************************************
 * UART0
 ****************************************************************************/
void __init dove_uart0_init(void)
{
	orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
			 IRQ_DOVE_UART_0, get_tclk());
}

/*****************************************************************************
 * UART1
 ****************************************************************************/
void __init dove_uart1_init(void)
{
	orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
			 IRQ_DOVE_UART_1, get_tclk());
}

/*****************************************************************************
 * UART2
 ****************************************************************************/
void __init dove_uart2_init(void)
{
	orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
			 IRQ_DOVE_UART_2, get_tclk());
}

/*****************************************************************************
 * UART3
 ****************************************************************************/
void __init dove_uart3_init(void)
{
	orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
			 IRQ_DOVE_UART_3, get_tclk());
}

/*****************************************************************************
 * SPI0
 ****************************************************************************/
static struct orion_spi_info dove_spi0_data = {
	.tclk		= 0,
};

static struct resource dove_spi0_resources[] = {
	{
		.start	= DOVE_SPI0_PHYS_BASE,
		.end	= DOVE_SPI0_PHYS_BASE + SZ_512 - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_DOVE_SPI0,
		.end	= IRQ_DOVE_SPI0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dove_spi0 = {
	.name		= "orion_spi",
	.id		= 0,
	.resource	= dove_spi0_resources,
	.dev		= {
		.platform_data	= &dove_spi0_data,
	},
	.num_resources	= ARRAY_SIZE(dove_spi0_resources),
};

void __init dove_spi0_init(void)
{
	platform_device_register(&dove_spi0);
}

/*****************************************************************************
 * SPI1
 ****************************************************************************/
static struct orion_spi_info dove_spi1_data = {
	.tclk		= 0,
};

static struct resource dove_spi1_resources[] = {
	{
		.start	= DOVE_SPI1_PHYS_BASE,
		.end	= DOVE_SPI1_PHYS_BASE + SZ_512 - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_DOVE_SPI1,
		.end	= IRQ_DOVE_SPI1,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dove_spi1 = {
	.name		= "orion_spi",
	.id		= 1,
	.resource	= dove_spi1_resources,
	.dev		= {
		.platform_data	= &dove_spi1_data,
	},
	.num_resources	= ARRAY_SIZE(dove_spi1_resources),
};

void __init dove_spi1_init(void)
{
	platform_device_register(&dove_spi1);
}

/*****************************************************************************
 * I2C
 ****************************************************************************/
static struct mv64xxx_i2c_pdata dove_i2c_data = {
	.freq_m		= 10, /* assumes 166 MHz TCLK gets 94.3kHz */
	.freq_n		= 3,
	.timeout	= 1000, /* Default timeout of 1 second */
};

static struct resource dove_i2c_resources[] = {
	{
		.name	= "i2c base",
		.start	= DOVE_I2C_PHYS_BASE,
		.end	= DOVE_I2C_PHYS_BASE + 0x20 - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.name	= "i2c irq",
		.start	= IRQ_DOVE_I2C,
		.end	= IRQ_DOVE_I2C,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dove_i2c = {
	.name		= MV64XXX_I2C_CTLR_NAME,
	.id		= 0,
	.num_resources	= ARRAY_SIZE(dove_i2c_resources),
	.resource	= dove_i2c_resources,
	.dev		= {
		.platform_data = &dove_i2c_data,
	},
};

void __init dove_i2c_init(void)
{
	platform_device_register(&dove_i2c);
}

/*****************************************************************************
 * Time handling
 ****************************************************************************/
void __init dove_init_early(void)
{
	orion_time_set_base(TIMER_VIRT_BASE);
}

static int get_tclk(void)
{
	/* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */
	return 166666667;
}

static void dove_timer_init(void)
{
	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
			IRQ_DOVE_BRIDGE, get_tclk());
}

struct sys_timer dove_timer = {
	.init = dove_timer_init,
};

/*****************************************************************************
 * XOR
 ****************************************************************************/
static struct mv_xor_platform_shared_data dove_xor_shared_data = {
	.dram		= &dove_mbus_dram_info,
};

/*****************************************************************************
 * XOR 0
 ****************************************************************************/
static u64 dove_xor0_dmamask = DMA_BIT_MASK(32);

static struct resource dove_xor0_shared_resources[] = {
	{
		.name	= "xor 0 low",
		.start	= DOVE_XOR0_PHYS_BASE,
		.end	= DOVE_XOR0_PHYS_BASE + 0xff,
		.flags	= IORESOURCE_MEM,
	}, {
		.name	= "xor 0 high",
		.start	= DOVE_XOR0_HIGH_PHYS_BASE,
		.end	= DOVE_XOR0_HIGH_PHYS_BASE + 0xff,
		.flags	= IORESOURCE_MEM,
	},
};

static struct platform_device dove_xor0_shared = {
	.name		= MV_XOR_SHARED_NAME,
	.id		= 0,
	.dev		= {
		.platform_data = &dove_xor_shared_data,
	},
	.num_resources	= ARRAY_SIZE(dove_xor0_shared_resources),
	.resource	= dove_xor0_shared_resources,
};

static struct resource dove_xor00_resources[] = {
	[0] = {
		.start	= IRQ_DOVE_XOR_00,
		.end	= IRQ_DOVE_XOR_00,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct mv_xor_platform_data dove_xor00_data = {
	.shared		= &dove_xor0_shared,
	.hw_id		= 0,
	.pool_size	= PAGE_SIZE,
};

static struct platform_device dove_xor00_channel = {
	.name		= MV_XOR_NAME,
	.id		= 0,
	.num_resources	= ARRAY_SIZE(dove_xor00_resources),
	.resource	= dove_xor00_resources,
	.dev		= {
		.dma_mask		= &dove_xor0_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(64),
		.platform_data		= &dove_xor00_data,
	},
};

static struct resource dove_xor01_resources[] = {
	[0] = {
		.start	= IRQ_DOVE_XOR_01,
		.end	= IRQ_DOVE_XOR_01,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct mv_xor_platform_data dove_xor01_data = {
	.shared		= &dove_xor0_shared,
	.hw_id		= 1,
	.pool_size	= PAGE_SIZE,
};

static struct platform_device dove_xor01_channel = {
	.name		= MV_XOR_NAME,
	.id		= 1,
	.num_resources	= ARRAY_SIZE(dove_xor01_resources),
	.resource	= dove_xor01_resources,
	.dev		= {
		.dma_mask		= &dove_xor0_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(64),
		.platform_data		= &dove_xor01_data,
	},
};

void __init dove_xor0_init(void)
{
	platform_device_register(&dove_xor0_shared);

	/*
	 * two engines can't do memset simultaneously, this limitation
	 * satisfied by removing memset support from one of the engines.
	 */
	dma_cap_set(DMA_MEMCPY, dove_xor00_data.cap_mask);
	dma_cap_set(DMA_XOR, dove_xor00_data.cap_mask);
	platform_device_register(&dove_xor00_channel);

	dma_cap_set(DMA_MEMCPY, dove_xor01_data.cap_mask);
	dma_cap_set(DMA_MEMSET, dove_xor01_data.cap_mask);
	dma_cap_set(DMA_XOR, dove_xor01_data.cap_mask);
	platform_device_register(&dove_xor01_channel);
}

/*****************************************************************************
 * XOR 1
 ****************************************************************************/
static u64 dove_xor1_dmamask = DMA_BIT_MASK(32);

static struct resource dove_xor1_shared_resources[] = {
	{
		.name	= "xor 0 low",
		.start	= DOVE_XOR1_PHYS_BASE,
		.end	= DOVE_XOR1_PHYS_BASE + 0xff,
		.flags	= IORESOURCE_MEM,
	}, {
		.name	= "xor 0 high",
		.start	= DOVE_XOR1_HIGH_PHYS_BASE,
		.end	= DOVE_XOR1_HIGH_PHYS_BASE + 0xff,
		.flags	= IORESOURCE_MEM,
	},
};

static struct platform_device dove_xor1_shared = {
	.name		= MV_XOR_SHARED_NAME,
	.id		= 1,
	.dev		= {
		.platform_data = &dove_xor_shared_data,
	},
	.num_resources	= ARRAY_SIZE(dove_xor1_shared_resources),
	.resource	= dove_xor1_shared_resources,
};

static struct resource dove_xor10_resources[] = {
	[0] = {
		.start	= IRQ_DOVE_XOR_10,
		.end	= IRQ_DOVE_XOR_10,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct mv_xor_platform_data dove_xor10_data = {
	.shared		= &dove_xor1_shared,
	.hw_id		= 0,
	.pool_size	= PAGE_SIZE,
};

static struct platform_device dove_xor10_channel = {
	.name		= MV_XOR_NAME,
	.id		= 2,
	.num_resources	= ARRAY_SIZE(dove_xor10_resources),
	.resource	= dove_xor10_resources,
	.dev		= {
		.dma_mask		= &dove_xor1_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(64),
		.platform_data		= &dove_xor10_data,
	},
};

static struct resource dove_xor11_resources[] = {
	[0] = {
		.start	= IRQ_DOVE_XOR_11,
		.end	= IRQ_DOVE_XOR_11,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct mv_xor_platform_data dove_xor11_data = {
	.shared		= &dove_xor1_shared,
	.hw_id		= 1,
	.pool_size	= PAGE_SIZE,
};

static struct platform_device dove_xor11_channel = {
	.name		= MV_XOR_NAME,
	.id		= 3,
	.num_resources	= ARRAY_SIZE(dove_xor11_resources),
	.resource	= dove_xor11_resources,
	.dev		= {
		.dma_mask		= &dove_xor1_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(64),
		.platform_data		= &dove_xor11_data,
	},
};

void __init dove_xor1_init(void)
{
	platform_device_register(&dove_xor1_shared);

	/*
	 * two engines can't do memset simultaneously, this limitation
	 * satisfied by removing memset support from one of the engines.
	 */
	dma_cap_set(DMA_MEMCPY, dove_xor10_data.cap_mask);
	dma_cap_set(DMA_XOR, dove_xor10_data.cap_mask);
	platform_device_register(&dove_xor10_channel);

	dma_cap_set(DMA_MEMCPY, dove_xor11_data.cap_mask);
	dma_cap_set(DMA_MEMSET, dove_xor11_data.cap_mask);
	dma_cap_set(DMA_XOR, dove_xor11_data.cap_mask);
	platform_device_register(&dove_xor11_channel);
}

/*****************************************************************************
 * SDIO
 ****************************************************************************/
static u64 sdio_dmamask = DMA_BIT_MASK(32);

static struct resource dove_sdio0_resources[] = {
	{
		.start	= DOVE_SDIO0_PHYS_BASE,
		.end	= DOVE_SDIO0_PHYS_BASE + 0xff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_DOVE_SDIO0,
		.end	= IRQ_DOVE_SDIO0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dove_sdio0 = {
	.name		= "sdhci-dove",
	.id		= 0,
	.dev		= {
		.dma_mask		= &sdio_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
	.resource	= dove_sdio0_resources,
	.num_resources	= ARRAY_SIZE(dove_sdio0_resources),
};

void __init dove_sdio0_init(void)
{
	platform_device_register(&dove_sdio0);
}

static struct resource dove_sdio1_resources[] = {
	{
		.start	= DOVE_SDIO1_PHYS_BASE,
		.end	= DOVE_SDIO1_PHYS_BASE + 0xff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_DOVE_SDIO1,
		.end	= IRQ_DOVE_SDIO1,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dove_sdio1 = {
	.name		= "sdhci-dove",
	.id		= 1,
	.dev		= {
		.dma_mask		= &sdio_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
	.resource	= dove_sdio1_resources,
	.num_resources	= ARRAY_SIZE(dove_sdio1_resources),
};

void __init dove_sdio1_init(void)
{
	platform_device_register(&dove_sdio1);
}

void __init dove_init(void)
{
	int tclk;

	tclk = get_tclk();

	printk(KERN_INFO "Dove 88AP510 SoC, ");
	printk(KERN_INFO "TCLK = %dMHz\n", (tclk + 499999) / 1000000);

#ifdef CONFIG_CACHE_TAUROS2
	tauros2_init();
#endif
	dove_setup_cpu_mbus();

	dove_ge00_shared_data.t_clk = tclk;
	dove_spi0_data.tclk = tclk;
	dove_spi1_data.tclk = tclk;

	/* internal devices that every board has */
	dove_rtc_init();
	dove_xor0_init();
	dove_xor1_init();
}
Commit	Line	Data
edabd38e SB	1	/*
	2	* arch/arm/mach-dove/common.c
	3	*
	4	* Core functions for Marvell Dove 88AP510 System On Chip
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/delay.h>
	13	#include <linux/init.h>
	14	#include <linux/platform_device.h>
	15	#include <linux/pci.h>
	16	#include <linux/serial_8250.h>
	17	#include <linux/clk.h>
	18	#include <linux/mbus.h>
	19	#include <linux/mv643xx_eth.h>
	20	#include <linux/mv643xx_i2c.h>
	21	#include <linux/ata_platform.h>
5c602551	22	#include <linux/serial_8250.h>
edabd38e SB	23	#include <linux/spi/orion_spi.h>
	24	#include <linux/gpio.h>
	25	#include <asm/page.h>
	26	#include <asm/setup.h>
	27	#include <asm/timex.h>
573a652f	28	#include <asm/hardware/cache-tauros2.h>
edabd38e SB	29	#include <asm/mach/map.h>
	30	#include <asm/mach/time.h>
	31	#include <asm/mach/pci.h>
	32	#include <mach/dove.h>
	33	#include <mach/bridge-regs.h>
	34	#include <asm/mach/arch.h>
	35	#include <linux/irq.h>
	36	#include <plat/mv_xor.h>
	37	#include <plat/ehci-orion.h>
	38	#include <plat/time.h>
28a2b450	39	#include <plat/common.h>
edabd38e SB	40	#include "common.h"
edabd38e SB	41
28a2b450 AL	42	static int get_tclk(void);
28a2b450 AL	43
edabd38e SB	44	/*****************************************************************************
	45	* I/O Address Mapping
	46	****************************************************************************/
	47	static struct map_desc dove_io_desc[] __initdata = {
	48	{
	49	.virtual = DOVE_SB_REGS_VIRT_BASE,
	50	.pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
	51	.length = DOVE_SB_REGS_SIZE,
	52	.type = MT_DEVICE,
	53	}, {
	54	.virtual = DOVE_NB_REGS_VIRT_BASE,
	55	.pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
	56	.length = DOVE_NB_REGS_SIZE,
	57	.type = MT_DEVICE,
	58	}, {
	59	.virtual = DOVE_PCIE0_IO_VIRT_BASE,
	60	.pfn = __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE),
	61	.length = DOVE_PCIE0_IO_SIZE,
	62	.type = MT_DEVICE,
	63	}, {
	64	.virtual = DOVE_PCIE1_IO_VIRT_BASE,
	65	.pfn = __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE),
	66	.length = DOVE_PCIE1_IO_SIZE,
	67	.type = MT_DEVICE,
	68	},
	69	};
	70
	71	void __init dove_map_io(void)
	72	{
	73	iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
	74	}
	75
	76	/*****************************************************************************
	77	* EHCI
	78	****************************************************************************/
	79	static struct orion_ehci_data dove_ehci_data = {
	80	.dram = &dove_mbus_dram_info,
	81	.phy_version = EHCI_PHY_NA,
	82	};
	83
	84	static u64 ehci_dmamask = DMA_BIT_MASK(32);
	85
	86	/*****************************************************************************
	87	* EHCI0
	88	****************************************************************************/
	89	static struct resource dove_ehci0_resources[] = {
	90	{
	91	.start = DOVE_USB0_PHYS_BASE,
	92	.end = DOVE_USB0_PHYS_BASE + SZ_4K - 1,
	93	.flags = IORESOURCE_MEM,
	94	}, {
	95	.start = IRQ_DOVE_USB0,
	96	.end = IRQ_DOVE_USB0,
	97	.flags = IORESOURCE_IRQ,
	98	},
	99	};
	100
	101	static struct platform_device dove_ehci0 = {
	102	.name = "orion-ehci",
	103	.id = 0,
	104	.dev = {
	105	.dma_mask = &ehci_dmamask,
	106	.coherent_dma_mask = DMA_BIT_MASK(32),
	107	.platform_data = &dove_ehci_data,
108	},
109	.resource = dove_ehci0_resources,
110	.num_resources = ARRAY_SIZE(dove_ehci0_resources),
111	};
112
113	void __init dove_ehci0_init(void)
114	{
115	platform_device_register(&dove_ehci0);
116	}
117
118	/*****************************************************************************
119	* EHCI1
120	****************************************************************************/
121	static struct resource dove_ehci1_resources[] = {
122	{
123	.start = DOVE_USB1_PHYS_BASE,
124	.end = DOVE_USB1_PHYS_BASE + SZ_4K - 1,
125	.flags = IORESOURCE_MEM,
126	}, {
127	.start = IRQ_DOVE_USB1,
128	.end = IRQ_DOVE_USB1,
129	.flags = IORESOURCE_IRQ,
130	},
131	};
132
133	static struct platform_device dove_ehci1 = {
134	.name = "orion-ehci",
135	.id = 1,
136	.dev = {
137	.dma_mask = &ehci_dmamask,
138	.coherent_dma_mask = DMA_BIT_MASK(32),
139	.platform_data = &dove_ehci_data,
140	},
141	.resource = dove_ehci1_resources,
142	.num_resources = ARRAY_SIZE(dove_ehci1_resources),
143	};
144
145	void __init dove_ehci1_init(void)
146	{
147	platform_device_register(&dove_ehci1);
148	}
149
150	/*****************************************************************************
151	* GE00
152	****************************************************************************/
153	struct mv643xx_eth_shared_platform_data dove_ge00_shared_data = {
154	.t_clk = 0,
155	.dram = &dove_mbus_dram_info,
156	};
157
158	static struct resource dove_ge00_shared_resources[] = {
159	{
160	.name = "ge00 base",
161	.start = DOVE_GE00_PHYS_BASE + 0x2000,
162	.end = DOVE_GE00_PHYS_BASE + SZ_16K - 1,
163	.flags = IORESOURCE_MEM,
164	},
165	};
166
167	static struct platform_device dove_ge00_shared = {
168	.name = MV643XX_ETH_SHARED_NAME,
169	.id = 0,
170	.dev = {
171	.platform_data = &dove_ge00_shared_data,
172	},
173	.num_resources = 1,
174	.resource = dove_ge00_shared_resources,
175	};
176
177	static struct resource dove_ge00_resources[] = {
178	{
179	.name = "ge00 irq",
180	.start = IRQ_DOVE_GE00_SUM,
181	.end = IRQ_DOVE_GE00_SUM,
182	.flags = IORESOURCE_IRQ,
183	},
184	};
185
186	static struct platform_device dove_ge00 = {
187	.name = MV643XX_ETH_NAME,
188	.id = 0,
189	.num_resources = 1,
190	.resource = dove_ge00_resources,
191	.dev = {
192	.coherent_dma_mask = 0xffffffff,
193	},
194	};
195
196	void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
197	{
198	eth_data->shared = &dove_ge00_shared;
199	dove_ge00.dev.platform_data = eth_data;
200
201	platform_device_register(&dove_ge00_shared);
202	platform_device_register(&dove_ge00);
203	}
204
205	/*****************************************************************************
206	* SoC RTC
207	****************************************************************************/
edabd38e SB	208	void __init dove_rtc_init(void)
edabd38e SB	209	{
f6eaccb3	210	orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
edabd38e SB	211	}
	212
	213	/*****************************************************************************
	214	* SATA
	215	****************************************************************************/
	216	static struct resource dove_sata_resources[] = {
	217	{
	218	.name = "sata base",
	219	.start = DOVE_SATA_PHYS_BASE,
	220	.end = DOVE_SATA_PHYS_BASE + 0x5000 - 1,
	221	.flags = IORESOURCE_MEM,
	222	}, {
	223	.name = "sata irq",
	224	.start = IRQ_DOVE_SATA,
	225	.end = IRQ_DOVE_SATA,
	226	.flags = IORESOURCE_IRQ,
	227	},
	228	};
	229
	230	static struct platform_device dove_sata = {
	231	.name = "sata_mv",
	232	.id = 0,
	233	.dev = {
	234	.coherent_dma_mask = DMA_BIT_MASK(32),
	235	},
	236	.num_resources = ARRAY_SIZE(dove_sata_resources),
	237	.resource = dove_sata_resources,
	238	};
	239
	240	void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
	241	{
	242	sata_data->dram = &dove_mbus_dram_info;
	243	dove_sata.dev.platform_data = sata_data;
	244	platform_device_register(&dove_sata);
	245	}
	246
	247	/*****************************************************************************
	248	* UART0
	249	****************************************************************************/
edabd38e SB	250	void __init dove_uart0_init(void)
edabd38e SB	251	{
28a2b450 AL	252	orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
28a2b450 AL	253	IRQ_DOVE_UART_0, get_tclk());
edabd38e SB	254	}
	255
	256	/*****************************************************************************
	257	* UART1
	258	****************************************************************************/
edabd38e SB	259	void __init dove_uart1_init(void)
edabd38e SB	260	{
28a2b450 AL	261	orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
28a2b450 AL	262	IRQ_DOVE_UART_1, get_tclk());
edabd38e SB	263	}
	264
	265	/*****************************************************************************
	266	* UART2
	267	****************************************************************************/
edabd38e SB	268	void __init dove_uart2_init(void)
edabd38e SB	269	{
28a2b450 AL	270	orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
28a2b450 AL	271	IRQ_DOVE_UART_2, get_tclk());
edabd38e SB	272	}
	273
	274	/*****************************************************************************
	275	* UART3
	276	****************************************************************************/
edabd38e SB	277	void __init dove_uart3_init(void)
edabd38e SB	278	{
28a2b450 AL	279	orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
28a2b450 AL	280	IRQ_DOVE_UART_3, get_tclk());
edabd38e SB	281	}
	282
	283	/*****************************************************************************
	284	* SPI0
	285	****************************************************************************/
	286	static struct orion_spi_info dove_spi0_data = {
	287	.tclk = 0,
	288	};
	289
	290	static struct resource dove_spi0_resources[] = {
	291	{
	292	.start = DOVE_SPI0_PHYS_BASE,
	293	.end = DOVE_SPI0_PHYS_BASE + SZ_512 - 1,
	294	.flags = IORESOURCE_MEM,
	295	}, {
	296	.start = IRQ_DOVE_SPI0,
	297	.end = IRQ_DOVE_SPI0,
	298	.flags = IORESOURCE_IRQ,
	299	},
	300	};
	301
	302	static struct platform_device dove_spi0 = {
	303	.name = "orion_spi",
	304	.id = 0,
	305	.resource = dove_spi0_resources,
	306	.dev = {
	307	.platform_data = &dove_spi0_data,
	308	},
	309	.num_resources = ARRAY_SIZE(dove_spi0_resources),
	310	};
	311
	312	void __init dove_spi0_init(void)
	313	{
	314	platform_device_register(&dove_spi0);
	315	}
	316
	317	/*****************************************************************************
	318	* SPI1
	319	****************************************************************************/
	320	static struct orion_spi_info dove_spi1_data = {
	321	.tclk = 0,
	322	};
	323
	324	static struct resource dove_spi1_resources[] = {
	325	{
	326	.start = DOVE_SPI1_PHYS_BASE,
	327	.end = DOVE_SPI1_PHYS_BASE + SZ_512 - 1,
	328	.flags = IORESOURCE_MEM,
	329	}, {
	330	.start = IRQ_DOVE_SPI1,
	331	.end = IRQ_DOVE_SPI1,
	332	.flags = IORESOURCE_IRQ,
	333	},
	334	};
	335
	336	static struct platform_device dove_spi1 = {
	337	.name = "orion_spi",
	338	.id = 1,
	339	.resource = dove_spi1_resources,
	340	.dev = {
	341	.platform_data = &dove_spi1_data,
	342	},
	343	.num_resources = ARRAY_SIZE(dove_spi1_resources),
	344	};
345
346	void __init dove_spi1_init(void)
347	{
348	platform_device_register(&dove_spi1);
349	}
350
351	/*****************************************************************************
352	* I2C
353	****************************************************************************/
354	static struct mv64xxx_i2c_pdata dove_i2c_data = {
355	.freq_m = 10, /* assumes 166 MHz TCLK gets 94.3kHz */
356	.freq_n = 3,
357	.timeout = 1000, /* Default timeout of 1 second */
358	};
359
360	static struct resource dove_i2c_resources[] = {
361	{
362	.name = "i2c base",
363	.start = DOVE_I2C_PHYS_BASE,
364	.end = DOVE_I2C_PHYS_BASE + 0x20 - 1,
365	.flags = IORESOURCE_MEM,
366	}, {
367	.name = "i2c irq",
368	.start = IRQ_DOVE_I2C,
369	.end = IRQ_DOVE_I2C,
370	.flags = IORESOURCE_IRQ,
371	},
372	};
373
374	static struct platform_device dove_i2c = {
375	.name = MV64XXX_I2C_CTLR_NAME,
376	.id = 0,
377	.num_resources = ARRAY_SIZE(dove_i2c_resources),
378	.resource = dove_i2c_resources,
379	.dev = {
380	.platform_data = &dove_i2c_data,
381	},
382	};
383
384	void __init dove_i2c_init(void)
385	{
386	platform_device_register(&dove_i2c);
387	}
388
389	/*****************************************************************************
390	* Time handling
391	****************************************************************************/
4ee1f6b5 LB	392	void __init dove_init_early(void)
	393	{
	394	orion_time_set_base(TIMER_VIRT_BASE);
	395	}
	396
edabd38e SB	397	static int get_tclk(void)
	398	{
	399	/* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */
	400	return 166666667;
	401	}
	402
	403	static void dove_timer_init(void)
	404	{
4ee1f6b5 LB	405	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
4ee1f6b5 LB	406	IRQ_DOVE_BRIDGE, get_tclk());
edabd38e SB	407	}
	408
	409	struct sys_timer dove_timer = {
	410	.init = dove_timer_init,
	411	};
	412
	413	/*****************************************************************************
	414	* XOR
	415	****************************************************************************/
	416	static struct mv_xor_platform_shared_data dove_xor_shared_data = {
	417	.dram = &dove_mbus_dram_info,
	418	};
	419
	420	/*****************************************************************************
	421	* XOR 0
	422	****************************************************************************/
	423	static u64 dove_xor0_dmamask = DMA_BIT_MASK(32);
	424
	425	static struct resource dove_xor0_shared_resources[] = {
	426	{
	427	.name = "xor 0 low",
	428	.start = DOVE_XOR0_PHYS_BASE,
	429	.end = DOVE_XOR0_PHYS_BASE + 0xff,
	430	.flags = IORESOURCE_MEM,
	431	}, {
	432	.name = "xor 0 high",
	433	.start = DOVE_XOR0_HIGH_PHYS_BASE,
	434	.end = DOVE_XOR0_HIGH_PHYS_BASE + 0xff,
	435	.flags = IORESOURCE_MEM,
	436	},
	437	};
	438
	439	static struct platform_device dove_xor0_shared = {
	440	.name = MV_XOR_SHARED_NAME,
	441	.id = 0,
	442	.dev = {
	443	.platform_data = &dove_xor_shared_data,
	444	},
	445	.num_resources = ARRAY_SIZE(dove_xor0_shared_resources),
	446	.resource = dove_xor0_shared_resources,
	447	};
	448
	449	static struct resource dove_xor00_resources[] = {
	450	[0] = {
	451	.start = IRQ_DOVE_XOR_00,
	452	.end = IRQ_DOVE_XOR_00,
	453	.flags = IORESOURCE_IRQ,
	454	},
	455	};
	456
	457	static struct mv_xor_platform_data dove_xor00_data = {
	458	.shared = &dove_xor0_shared,
	459	.hw_id = 0,
	460	.pool_size = PAGE_SIZE,
	461	};
	462
	463	static struct platform_device dove_xor00_channel = {
	464	.name = MV_XOR_NAME,
	465	.id = 0,
	466	.num_resources = ARRAY_SIZE(dove_xor00_resources),
	467	.resource = dove_xor00_resources,
	468	.dev = {
	469	.dma_mask = &dove_xor0_dmamask,
	470	.coherent_dma_mask = DMA_BIT_MASK(64),
639b9be6	471	.platform_data = &dove_xor00_data,
edabd38e SB	472	},
	473	};
	474
	475	static struct resource dove_xor01_resources[] = {
	476	[0] = {
	477	.start = IRQ_DOVE_XOR_01,
	478	.end = IRQ_DOVE_XOR_01,
	479	.flags = IORESOURCE_IRQ,
	480	},
	481	};
	482
	483	static struct mv_xor_platform_data dove_xor01_data = {
	484	.shared = &dove_xor0_shared,
	485	.hw_id = 1,
	486	.pool_size = PAGE_SIZE,
	487	};
	488
	489	static struct platform_device dove_xor01_channel = {
	490	.name = MV_XOR_NAME,
	491	.id = 1,
	492	.num_resources = ARRAY_SIZE(dove_xor01_resources),
	493	.resource = dove_xor01_resources,
	494	.dev = {
	495	.dma_mask = &dove_xor0_dmamask,
	496	.coherent_dma_mask = DMA_BIT_MASK(64),
639b9be6	497	.platform_data = &dove_xor01_data,
edabd38e SB	498	},
	499	};
	500
	501	void __init dove_xor0_init(void)
	502	{
	503	platform_device_register(&dove_xor0_shared);
	504
	505	/*
	506	* two engines can't do memset simultaneously, this limitation
	507	* satisfied by removing memset support from one of the engines.
	508	*/
	509	dma_cap_set(DMA_MEMCPY, dove_xor00_data.cap_mask);
	510	dma_cap_set(DMA_XOR, dove_xor00_data.cap_mask);
	511	platform_device_register(&dove_xor00_channel);
	512
	513	dma_cap_set(DMA_MEMCPY, dove_xor01_data.cap_mask);
	514	dma_cap_set(DMA_MEMSET, dove_xor01_data.cap_mask);
	515	dma_cap_set(DMA_XOR, dove_xor01_data.cap_mask);
	516	platform_device_register(&dove_xor01_channel);
	517	}
	518
	519	/*****************************************************************************
	520	* XOR 1
	521	****************************************************************************/
	522	static u64 dove_xor1_dmamask = DMA_BIT_MASK(32);
	523
	524	static struct resource dove_xor1_shared_resources[] = {
	525	{
	526	.name = "xor 0 low",
	527	.start = DOVE_XOR1_PHYS_BASE,
	528	.end = DOVE_XOR1_PHYS_BASE + 0xff,
	529	.flags = IORESOURCE_MEM,
	530	}, {
	531	.name = "xor 0 high",
	532	.start = DOVE_XOR1_HIGH_PHYS_BASE,
	533	.end = DOVE_XOR1_HIGH_PHYS_BASE + 0xff,
	534	.flags = IORESOURCE_MEM,
	535	},
	536	};
	537
	538	static struct platform_device dove_xor1_shared = {
	539	.name = MV_XOR_SHARED_NAME,
	540	.id = 1,
	541	.dev = {
	542	.platform_data = &dove_xor_shared_data,
	543	},
	544	.num_resources = ARRAY_SIZE(dove_xor1_shared_resources),
	545	.resource = dove_xor1_shared_resources,
	546	};
	547
	548	static struct resource dove_xor10_resources[] = {
	549	[0] = {
	550	.start = IRQ_DOVE_XOR_10,
	551	.end = IRQ_DOVE_XOR_10,
	552	.flags = IORESOURCE_IRQ,
	553	},
	554	};
	555
	556	static struct mv_xor_platform_data dove_xor10_data = {
	557	.shared = &dove_xor1_shared,
	558	.hw_id = 0,
	559	.pool_size = PAGE_SIZE,
	560	};
	561
562	static struct platform_device dove_xor10_channel = {
563	.name = MV_XOR_NAME,
564	.id = 2,
565	.num_resources = ARRAY_SIZE(dove_xor10_resources),
566	.resource = dove_xor10_resources,
567	.dev = {
568	.dma_mask = &dove_xor1_dmamask,
569	.coherent_dma_mask = DMA_BIT_MASK(64),
639b9be6	570	.platform_data = &dove_xor10_data,
edabd38e SB	571	},
	572	};
	573
	574	static struct resource dove_xor11_resources[] = {
	575	[0] = {
	576	.start = IRQ_DOVE_XOR_11,
	577	.end = IRQ_DOVE_XOR_11,
	578	.flags = IORESOURCE_IRQ,
	579	},
	580	};
	581
	582	static struct mv_xor_platform_data dove_xor11_data = {
	583	.shared = &dove_xor1_shared,
	584	.hw_id = 1,
	585	.pool_size = PAGE_SIZE,
	586	};
	587
	588	static struct platform_device dove_xor11_channel = {
	589	.name = MV_XOR_NAME,
	590	.id = 3,
	591	.num_resources = ARRAY_SIZE(dove_xor11_resources),
	592	.resource = dove_xor11_resources,
	593	.dev = {
	594	.dma_mask = &dove_xor1_dmamask,
	595	.coherent_dma_mask = DMA_BIT_MASK(64),
639b9be6	596	.platform_data = &dove_xor11_data,
edabd38e SB	597	},
	598	};
	599
	600	void __init dove_xor1_init(void)
	601	{
	602	platform_device_register(&dove_xor1_shared);
	603
	604	/*
	605	* two engines can't do memset simultaneously, this limitation
	606	* satisfied by removing memset support from one of the engines.
	607	*/
	608	dma_cap_set(DMA_MEMCPY, dove_xor10_data.cap_mask);
	609	dma_cap_set(DMA_XOR, dove_xor10_data.cap_mask);
	610	platform_device_register(&dove_xor10_channel);
	611
	612	dma_cap_set(DMA_MEMCPY, dove_xor11_data.cap_mask);
	613	dma_cap_set(DMA_MEMSET, dove_xor11_data.cap_mask);
	614	dma_cap_set(DMA_XOR, dove_xor11_data.cap_mask);
	615	platform_device_register(&dove_xor11_channel);
	616	}
	617
16bc90af SB	618	/*****************************************************************************
	619	* SDIO
	620	****************************************************************************/
	621	static u64 sdio_dmamask = DMA_BIT_MASK(32);
	622
	623	static struct resource dove_sdio0_resources[] = {
	624	{
	625	.start = DOVE_SDIO0_PHYS_BASE,
	626	.end = DOVE_SDIO0_PHYS_BASE + 0xff,
	627	.flags = IORESOURCE_MEM,
	628	}, {
	629	.start = IRQ_DOVE_SDIO0,
	630	.end = IRQ_DOVE_SDIO0,
	631	.flags = IORESOURCE_IRQ,
	632	},
	633	};
	634
	635	static struct platform_device dove_sdio0 = {
930e2fe7	636	.name = "sdhci-dove",
16bc90af SB	637	.id = 0,
	638	.dev = {
	639	.dma_mask = &sdio_dmamask,
	640	.coherent_dma_mask = DMA_BIT_MASK(32),
	641	},
	642	.resource = dove_sdio0_resources,
	643	.num_resources = ARRAY_SIZE(dove_sdio0_resources),
	644	};
	645
	646	void __init dove_sdio0_init(void)
	647	{
	648	platform_device_register(&dove_sdio0);
	649	}
	650
	651	static struct resource dove_sdio1_resources[] = {
	652	{
	653	.start = DOVE_SDIO1_PHYS_BASE,
	654	.end = DOVE_SDIO1_PHYS_BASE + 0xff,
	655	.flags = IORESOURCE_MEM,
	656	}, {
	657	.start = IRQ_DOVE_SDIO1,
	658	.end = IRQ_DOVE_SDIO1,
	659	.flags = IORESOURCE_IRQ,
	660	},
	661	};
	662
	663	static struct platform_device dove_sdio1 = {
930e2fe7	664	.name = "sdhci-dove",
16bc90af SB	665	.id = 1,
	666	.dev = {
	667	.dma_mask = &sdio_dmamask,
	668	.coherent_dma_mask = DMA_BIT_MASK(32),
	669	},
	670	.resource = dove_sdio1_resources,
	671	.num_resources = ARRAY_SIZE(dove_sdio1_resources),
	672	};
	673
	674	void __init dove_sdio1_init(void)
	675	{
	676	platform_device_register(&dove_sdio1);
	677	}
	678
edabd38e SB	679	void __init dove_init(void)
	680	{
	681	int tclk;
	682
	683	tclk = get_tclk();
	684
	685	printk(KERN_INFO "Dove 88AP510 SoC, ");
	686	printk(KERN_INFO "TCLK = %dMHz\n", (tclk + 499999) / 1000000);
	687
573a652f LB	688	#ifdef CONFIG_CACHE_TAUROS2
	689	tauros2_init();
	690	#endif
edabd38e SB	691	dove_setup_cpu_mbus();
	692
	693	dove_ge00_shared_data.t_clk = tclk;
edabd38e SB	694	dove_spi0_data.tclk = tclk;
	695	dove_spi1_data.tclk = tclk;
	696
	697	/* internal devices that every board has */
	698	dove_rtc_init();
	699	dove_xor0_init();
	700	dove_xor1_init();
	701	}