[deliverable/linux.git] / arch / arm / mach-dove / common.c

/*
 * arch/arm/mach-dove/common.c
 *
 * Core functions for Marvell Dove 88AP510 System On Chip
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/pci.h>
#include <linux/serial_8250.h>
#include <linux/clk.h>
#include <linux/mbus.h>
#include <linux/ata_platform.h>
#include <linux/serial_8250.h>
#include <linux/spi/orion_spi.h>
#include <linux/gpio.h>
#include <asm/page.h>
#include <asm/setup.h>
#include <asm/timex.h>
#include <asm/hardware/cache-tauros2.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/mach/pci.h>
#include <mach/dove.h>
#include <mach/bridge-regs.h>
#include <asm/mach/arch.h>
#include <linux/irq.h>
#include <plat/mv_xor.h>
#include <plat/ehci-orion.h>
#include <plat/time.h>
#include <plat/common.h>
#include "common.h"

static int get_tclk(void);

/*****************************************************************************
 * I/O Address Mapping
 ****************************************************************************/
static struct map_desc dove_io_desc[] __initdata = {
	{
		.virtual	= DOVE_SB_REGS_VIRT_BASE,
		.pfn		= __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
		.length		= DOVE_SB_REGS_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= DOVE_NB_REGS_VIRT_BASE,
		.pfn		= __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
		.length		= DOVE_NB_REGS_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= DOVE_PCIE0_IO_VIRT_BASE,
		.pfn		= __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE),
		.length		= DOVE_PCIE0_IO_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= DOVE_PCIE1_IO_VIRT_BASE,
		.pfn		= __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE),
		.length		= DOVE_PCIE1_IO_SIZE,
		.type		= MT_DEVICE,
	},
};

void __init dove_map_io(void)
{
	iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
}

/*****************************************************************************
 * EHCI
 ****************************************************************************/
static struct orion_ehci_data dove_ehci_data = {
	.dram		= &dove_mbus_dram_info,
	.phy_version	= EHCI_PHY_NA,
};

static u64 ehci_dmamask = DMA_BIT_MASK(32);

/*****************************************************************************
 * EHCI0
 ****************************************************************************/
static struct resource dove_ehci0_resources[] = {
	{
		.start	= DOVE_USB0_PHYS_BASE,
		.end	= DOVE_USB0_PHYS_BASE + SZ_4K - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_DOVE_USB0,
		.end	= IRQ_DOVE_USB0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dove_ehci0 = {
	.name		= "orion-ehci",
	.id		= 0,
	.dev		= {
		.dma_mask		= &ehci_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
		.platform_data		= &dove_ehci_data,
	},
	.resource	= dove_ehci0_resources,
	.num_resources	= ARRAY_SIZE(dove_ehci0_resources),
};

void __init dove_ehci0_init(void)
{
	platform_device_register(&dove_ehci0);
}

/*****************************************************************************
 * EHCI1
 ****************************************************************************/
static struct resource dove_ehci1_resources[] = {
	{
		.start	= DOVE_USB1_PHYS_BASE,
		.end	= DOVE_USB1_PHYS_BASE + SZ_4K - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_DOVE_USB1,
		.end	= IRQ_DOVE_USB1,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dove_ehci1 = {
	.name		= "orion-ehci",
	.id		= 1,
	.dev		= {
		.dma_mask		= &ehci_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
		.platform_data		= &dove_ehci_data,
	},
	.resource	= dove_ehci1_resources,
	.num_resources	= ARRAY_SIZE(dove_ehci1_resources),
};

void __init dove_ehci1_init(void)
{
	platform_device_register(&dove_ehci1);
}

/*****************************************************************************
 * GE00
 ****************************************************************************/
void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
{
	orion_ge00_init(eth_data, &dove_mbus_dram_info,
			DOVE_GE00_PHYS_BASE, IRQ_DOVE_GE00_SUM,
			0, get_tclk());
}

/*****************************************************************************
 * SoC RTC
 ****************************************************************************/
void __init dove_rtc_init(void)
{
	orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
}

/*****************************************************************************
 * SATA
 ****************************************************************************/
static struct resource dove_sata_resources[] = {
	{
		.name	= "sata base",
		.start	= DOVE_SATA_PHYS_BASE,
		.end	= DOVE_SATA_PHYS_BASE + 0x5000 - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.name	= "sata irq",
		.start	= IRQ_DOVE_SATA,
		.end	= IRQ_DOVE_SATA,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dove_sata = {
	.name		= "sata_mv",
	.id		= 0,
	.dev		= {
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
	.num_resources	= ARRAY_SIZE(dove_sata_resources),
	.resource	= dove_sata_resources,
};

void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
{
	sata_data->dram = &dove_mbus_dram_info;
	dove_sata.dev.platform_data = sata_data;
	platform_device_register(&dove_sata);
}

/*****************************************************************************
 * UART0
 ****************************************************************************/
void __init dove_uart0_init(void)
{
	orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
			 IRQ_DOVE_UART_0, get_tclk());
}

/*****************************************************************************
 * UART1
 ****************************************************************************/
void __init dove_uart1_init(void)
{
	orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
			 IRQ_DOVE_UART_1, get_tclk());
}

/*****************************************************************************
 * UART2
 ****************************************************************************/
void __init dove_uart2_init(void)
{
	orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
			 IRQ_DOVE_UART_2, get_tclk());
}

/*****************************************************************************
 * UART3
 ****************************************************************************/
void __init dove_uart3_init(void)
{
	orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
			 IRQ_DOVE_UART_3, get_tclk());
}

/*****************************************************************************
 * SPI0
 ****************************************************************************/
static struct orion_spi_info dove_spi0_data = {
	.tclk		= 0,
};

static struct resource dove_spi0_resources[] = {
	{
		.start	= DOVE_SPI0_PHYS_BASE,
		.end	= DOVE_SPI0_PHYS_BASE + SZ_512 - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_DOVE_SPI0,
		.end	= IRQ_DOVE_SPI0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dove_spi0 = {
	.name		= "orion_spi",
	.id		= 0,
	.resource	= dove_spi0_resources,
	.dev		= {
		.platform_data	= &dove_spi0_data,
	},
	.num_resources	= ARRAY_SIZE(dove_spi0_resources),
};

void __init dove_spi0_init(void)
{
	platform_device_register(&dove_spi0);
}

/*****************************************************************************
 * SPI1
 ****************************************************************************/
static struct orion_spi_info dove_spi1_data = {
	.tclk		= 0,
};

static struct resource dove_spi1_resources[] = {
	{
		.start	= DOVE_SPI1_PHYS_BASE,
		.end	= DOVE_SPI1_PHYS_BASE + SZ_512 - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_DOVE_SPI1,
		.end	= IRQ_DOVE_SPI1,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dove_spi1 = {
	.name		= "orion_spi",
	.id		= 1,
	.resource	= dove_spi1_resources,
	.dev		= {
		.platform_data	= &dove_spi1_data,
	},
	.num_resources	= ARRAY_SIZE(dove_spi1_resources),
};

void __init dove_spi1_init(void)
{
	platform_device_register(&dove_spi1);
}

/*****************************************************************************
 * I2C
 ****************************************************************************/
void __init dove_i2c_init(void)
{
	orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10);
}

/*****************************************************************************
 * Time handling
 ****************************************************************************/
void __init dove_init_early(void)
{
	orion_time_set_base(TIMER_VIRT_BASE);
}

static int get_tclk(void)
{
	/* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */
	return 166666667;
}

static void dove_timer_init(void)
{
	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
			IRQ_DOVE_BRIDGE, get_tclk());
}

struct sys_timer dove_timer = {
	.init = dove_timer_init,
};

/*****************************************************************************
 * XOR
 ****************************************************************************/
static struct mv_xor_platform_shared_data dove_xor_shared_data = {
	.dram		= &dove_mbus_dram_info,
};

/*****************************************************************************
 * XOR 0
 ****************************************************************************/
static u64 dove_xor0_dmamask = DMA_BIT_MASK(32);

static struct resource dove_xor0_shared_resources[] = {
	{
		.name	= "xor 0 low",
		.start	= DOVE_XOR0_PHYS_BASE,
		.end	= DOVE_XOR0_PHYS_BASE + 0xff,
		.flags	= IORESOURCE_MEM,
	}, {
		.name	= "xor 0 high",
		.start	= DOVE_XOR0_HIGH_PHYS_BASE,
		.end	= DOVE_XOR0_HIGH_PHYS_BASE + 0xff,
		.flags	= IORESOURCE_MEM,
	},
};

static struct platform_device dove_xor0_shared = {
	.name		= MV_XOR_SHARED_NAME,
	.id		= 0,
	.dev		= {
		.platform_data = &dove_xor_shared_data,
	},
	.num_resources	= ARRAY_SIZE(dove_xor0_shared_resources),
	.resource	= dove_xor0_shared_resources,
};

static struct resource dove_xor00_resources[] = {
	[0] = {
		.start	= IRQ_DOVE_XOR_00,
		.end	= IRQ_DOVE_XOR_00,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct mv_xor_platform_data dove_xor00_data = {
	.shared		= &dove_xor0_shared,
	.hw_id		= 0,
	.pool_size	= PAGE_SIZE,
};

static struct platform_device dove_xor00_channel = {
	.name		= MV_XOR_NAME,
	.id		= 0,
	.num_resources	= ARRAY_SIZE(dove_xor00_resources),
	.resource	= dove_xor00_resources,
	.dev		= {
		.dma_mask		= &dove_xor0_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(64),
		.platform_data		= &dove_xor00_data,
	},
};

static struct resource dove_xor01_resources[] = {
	[0] = {
		.start	= IRQ_DOVE_XOR_01,
		.end	= IRQ_DOVE_XOR_01,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct mv_xor_platform_data dove_xor01_data = {
	.shared		= &dove_xor0_shared,
	.hw_id		= 1,
	.pool_size	= PAGE_SIZE,
};

static struct platform_device dove_xor01_channel = {
	.name		= MV_XOR_NAME,
	.id		= 1,
	.num_resources	= ARRAY_SIZE(dove_xor01_resources),
	.resource	= dove_xor01_resources,
	.dev		= {
		.dma_mask		= &dove_xor0_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(64),
		.platform_data		= &dove_xor01_data,
	},
};

void __init dove_xor0_init(void)
{
	platform_device_register(&dove_xor0_shared);

	/*
	 * two engines can't do memset simultaneously, this limitation
	 * satisfied by removing memset support from one of the engines.
	 */
	dma_cap_set(DMA_MEMCPY, dove_xor00_data.cap_mask);
	dma_cap_set(DMA_XOR, dove_xor00_data.cap_mask);
	platform_device_register(&dove_xor00_channel);

	dma_cap_set(DMA_MEMCPY, dove_xor01_data.cap_mask);
	dma_cap_set(DMA_MEMSET, dove_xor01_data.cap_mask);
	dma_cap_set(DMA_XOR, dove_xor01_data.cap_mask);
	platform_device_register(&dove_xor01_channel);
}

/*****************************************************************************
 * XOR 1
 ****************************************************************************/
static u64 dove_xor1_dmamask = DMA_BIT_MASK(32);

static struct resource dove_xor1_shared_resources[] = {
	{
		.name	= "xor 0 low",
		.start	= DOVE_XOR1_PHYS_BASE,
		.end	= DOVE_XOR1_PHYS_BASE + 0xff,
		.flags	= IORESOURCE_MEM,
	}, {
		.name	= "xor 0 high",
		.start	= DOVE_XOR1_HIGH_PHYS_BASE,
		.end	= DOVE_XOR1_HIGH_PHYS_BASE + 0xff,
		.flags	= IORESOURCE_MEM,
	},
};

static struct platform_device dove_xor1_shared = {
	.name		= MV_XOR_SHARED_NAME,
	.id		= 1,
	.dev		= {
		.platform_data = &dove_xor_shared_data,
	},
	.num_resources	= ARRAY_SIZE(dove_xor1_shared_resources),
	.resource	= dove_xor1_shared_resources,
};

static struct resource dove_xor10_resources[] = {
	[0] = {
		.start	= IRQ_DOVE_XOR_10,
		.end	= IRQ_DOVE_XOR_10,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct mv_xor_platform_data dove_xor10_data = {
	.shared		= &dove_xor1_shared,
	.hw_id		= 0,
	.pool_size	= PAGE_SIZE,
};

static struct platform_device dove_xor10_channel = {
	.name		= MV_XOR_NAME,
	.id		= 2,
	.num_resources	= ARRAY_SIZE(dove_xor10_resources),
	.resource	= dove_xor10_resources,
	.dev		= {
		.dma_mask		= &dove_xor1_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(64),
		.platform_data		= &dove_xor10_data,
	},
};

static struct resource dove_xor11_resources[] = {
	[0] = {
		.start	= IRQ_DOVE_XOR_11,
		.end	= IRQ_DOVE_XOR_11,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct mv_xor_platform_data dove_xor11_data = {
	.shared		= &dove_xor1_shared,
	.hw_id		= 1,
	.pool_size	= PAGE_SIZE,
};

static struct platform_device dove_xor11_channel = {
	.name		= MV_XOR_NAME,
	.id		= 3,
	.num_resources	= ARRAY_SIZE(dove_xor11_resources),
	.resource	= dove_xor11_resources,
	.dev		= {
		.dma_mask		= &dove_xor1_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(64),
		.platform_data		= &dove_xor11_data,
	},
};

void __init dove_xor1_init(void)
{
	platform_device_register(&dove_xor1_shared);

	/*
	 * two engines can't do memset simultaneously, this limitation
	 * satisfied by removing memset support from one of the engines.
	 */
	dma_cap_set(DMA_MEMCPY, dove_xor10_data.cap_mask);
	dma_cap_set(DMA_XOR, dove_xor10_data.cap_mask);
	platform_device_register(&dove_xor10_channel);

	dma_cap_set(DMA_MEMCPY, dove_xor11_data.cap_mask);
	dma_cap_set(DMA_MEMSET, dove_xor11_data.cap_mask);
	dma_cap_set(DMA_XOR, dove_xor11_data.cap_mask);
	platform_device_register(&dove_xor11_channel);
}

/*****************************************************************************
 * SDIO
 ****************************************************************************/
static u64 sdio_dmamask = DMA_BIT_MASK(32);

static struct resource dove_sdio0_resources[] = {
	{
		.start	= DOVE_SDIO0_PHYS_BASE,
		.end	= DOVE_SDIO0_PHYS_BASE + 0xff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_DOVE_SDIO0,
		.end	= IRQ_DOVE_SDIO0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dove_sdio0 = {
	.name		= "sdhci-dove",
	.id		= 0,
	.dev		= {
		.dma_mask		= &sdio_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
	.resource	= dove_sdio0_resources,
	.num_resources	= ARRAY_SIZE(dove_sdio0_resources),
};

void __init dove_sdio0_init(void)
{
	platform_device_register(&dove_sdio0);
}

static struct resource dove_sdio1_resources[] = {
	{
		.start	= DOVE_SDIO1_PHYS_BASE,
		.end	= DOVE_SDIO1_PHYS_BASE + 0xff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_DOVE_SDIO1,
		.end	= IRQ_DOVE_SDIO1,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dove_sdio1 = {
	.name		= "sdhci-dove",
	.id		= 1,
	.dev		= {
		.dma_mask		= &sdio_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
	.resource	= dove_sdio1_resources,
	.num_resources	= ARRAY_SIZE(dove_sdio1_resources),
};

void __init dove_sdio1_init(void)
{
	platform_device_register(&dove_sdio1);
}

void __init dove_init(void)
{
	int tclk;

	tclk = get_tclk();

	printk(KERN_INFO "Dove 88AP510 SoC, ");
	printk(KERN_INFO "TCLK = %dMHz\n", (tclk + 499999) / 1000000);

#ifdef CONFIG_CACHE_TAUROS2
	tauros2_init();
#endif
	dove_setup_cpu_mbus();

	dove_spi0_data.tclk = tclk;
	dove_spi1_data.tclk = tclk;

	/* internal devices that every board has */
	dove_rtc_init();
	dove_xor0_init();
	dove_xor1_init();
}
Commit	Line	Data
edabd38e SB	1	/*
	2	* arch/arm/mach-dove/common.c
	3	*
	4	* Core functions for Marvell Dove 88AP510 System On Chip
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/delay.h>
	13	#include <linux/init.h>
	14	#include <linux/platform_device.h>
	15	#include <linux/pci.h>
	16	#include <linux/serial_8250.h>
	17	#include <linux/clk.h>
	18	#include <linux/mbus.h>
edabd38e	19	#include <linux/ata_platform.h>
5c602551	20	#include <linux/serial_8250.h>
edabd38e SB	21	#include <linux/spi/orion_spi.h>
	22	#include <linux/gpio.h>
	23	#include <asm/page.h>
	24	#include <asm/setup.h>
	25	#include <asm/timex.h>
573a652f	26	#include <asm/hardware/cache-tauros2.h>
edabd38e SB	27	#include <asm/mach/map.h>
	28	#include <asm/mach/time.h>
	29	#include <asm/mach/pci.h>
	30	#include <mach/dove.h>
	31	#include <mach/bridge-regs.h>
	32	#include <asm/mach/arch.h>
	33	#include <linux/irq.h>
	34	#include <plat/mv_xor.h>
	35	#include <plat/ehci-orion.h>
	36	#include <plat/time.h>
28a2b450	37	#include <plat/common.h>
edabd38e SB	38	#include "common.h"
edabd38e SB	39
28a2b450 AL	40	static int get_tclk(void);
28a2b450 AL	41
edabd38e SB	42	/*****************************************************************************
	43	* I/O Address Mapping
	44	****************************************************************************/
	45	static struct map_desc dove_io_desc[] __initdata = {
	46	{
	47	.virtual = DOVE_SB_REGS_VIRT_BASE,
	48	.pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
	49	.length = DOVE_SB_REGS_SIZE,
	50	.type = MT_DEVICE,
	51	}, {
	52	.virtual = DOVE_NB_REGS_VIRT_BASE,
	53	.pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
	54	.length = DOVE_NB_REGS_SIZE,
	55	.type = MT_DEVICE,
	56	}, {
	57	.virtual = DOVE_PCIE0_IO_VIRT_BASE,
	58	.pfn = __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE),
	59	.length = DOVE_PCIE0_IO_SIZE,
	60	.type = MT_DEVICE,
	61	}, {
	62	.virtual = DOVE_PCIE1_IO_VIRT_BASE,
	63	.pfn = __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE),
	64	.length = DOVE_PCIE1_IO_SIZE,
	65	.type = MT_DEVICE,
	66	},
	67	};
	68
	69	void __init dove_map_io(void)
	70	{
	71	iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
	72	}
	73
	74	/*****************************************************************************
	75	* EHCI
	76	****************************************************************************/
	77	static struct orion_ehci_data dove_ehci_data = {
	78	.dram = &dove_mbus_dram_info,
	79	.phy_version = EHCI_PHY_NA,
	80	};
	81
	82	static u64 ehci_dmamask = DMA_BIT_MASK(32);
	83
	84	/*****************************************************************************
	85	* EHCI0
	86	****************************************************************************/
	87	static struct resource dove_ehci0_resources[] = {
	88	{
	89	.start = DOVE_USB0_PHYS_BASE,
	90	.end = DOVE_USB0_PHYS_BASE + SZ_4K - 1,
	91	.flags = IORESOURCE_MEM,
	92	}, {
	93	.start = IRQ_DOVE_USB0,
	94	.end = IRQ_DOVE_USB0,
	95	.flags = IORESOURCE_IRQ,
	96	},
	97	};
	98
	99	static struct platform_device dove_ehci0 = {
	100	.name = "orion-ehci",
	101	.id = 0,
	102	.dev = {
	103	.dma_mask = &ehci_dmamask,
	104	.coherent_dma_mask = DMA_BIT_MASK(32),
	105	.platform_data = &dove_ehci_data,
106	},
107	.resource = dove_ehci0_resources,
108	.num_resources = ARRAY_SIZE(dove_ehci0_resources),
109	};
110
111	void __init dove_ehci0_init(void)
112	{
113	platform_device_register(&dove_ehci0);
114	}
115
116	/*****************************************************************************
117	* EHCI1
118	****************************************************************************/
119	static struct resource dove_ehci1_resources[] = {
120	{
121	.start = DOVE_USB1_PHYS_BASE,
122	.end = DOVE_USB1_PHYS_BASE + SZ_4K - 1,
123	.flags = IORESOURCE_MEM,
124	}, {
125	.start = IRQ_DOVE_USB1,
126	.end = IRQ_DOVE_USB1,
127	.flags = IORESOURCE_IRQ,
128	},
129	};
130
131	static struct platform_device dove_ehci1 = {
132	.name = "orion-ehci",
133	.id = 1,
134	.dev = {
135	.dma_mask = &ehci_dmamask,
136	.coherent_dma_mask = DMA_BIT_MASK(32),
137	.platform_data = &dove_ehci_data,
138	},
139	.resource = dove_ehci1_resources,
140	.num_resources = ARRAY_SIZE(dove_ehci1_resources),
141	};
142
143	void __init dove_ehci1_init(void)
144	{
145	platform_device_register(&dove_ehci1);
146	}
147
148	/*****************************************************************************
149	* GE00
150	****************************************************************************/
edabd38e SB	151	void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
edabd38e SB	152	{
7e3819d8 AL	153	orion_ge00_init(eth_data, &dove_mbus_dram_info,
	154	DOVE_GE00_PHYS_BASE, IRQ_DOVE_GE00_SUM,
	155	0, get_tclk());
edabd38e SB	156	}
	157
	158	/*****************************************************************************
	159	* SoC RTC
	160	****************************************************************************/
edabd38e SB	161	void __init dove_rtc_init(void)
edabd38e SB	162	{
f6eaccb3	163	orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
edabd38e SB	164	}
	165
	166	/*****************************************************************************
	167	* SATA
	168	****************************************************************************/
	169	static struct resource dove_sata_resources[] = {
	170	{
	171	.name = "sata base",
	172	.start = DOVE_SATA_PHYS_BASE,
	173	.end = DOVE_SATA_PHYS_BASE + 0x5000 - 1,
	174	.flags = IORESOURCE_MEM,
	175	}, {
	176	.name = "sata irq",
	177	.start = IRQ_DOVE_SATA,
	178	.end = IRQ_DOVE_SATA,
	179	.flags = IORESOURCE_IRQ,
	180	},
	181	};
	182
	183	static struct platform_device dove_sata = {
	184	.name = "sata_mv",
	185	.id = 0,
	186	.dev = {
	187	.coherent_dma_mask = DMA_BIT_MASK(32),
	188	},
	189	.num_resources = ARRAY_SIZE(dove_sata_resources),
	190	.resource = dove_sata_resources,
	191	};
	192
	193	void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
	194	{
	195	sata_data->dram = &dove_mbus_dram_info;
	196	dove_sata.dev.platform_data = sata_data;
	197	platform_device_register(&dove_sata);
	198	}
	199
	200	/*****************************************************************************
	201	* UART0
	202	****************************************************************************/
edabd38e SB	203	void __init dove_uart0_init(void)
edabd38e SB	204	{
28a2b450 AL	205	orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
28a2b450 AL	206	IRQ_DOVE_UART_0, get_tclk());
edabd38e SB	207	}
	208
	209	/*****************************************************************************
	210	* UART1
	211	****************************************************************************/
edabd38e SB	212	void __init dove_uart1_init(void)
edabd38e SB	213	{
28a2b450 AL	214	orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
28a2b450 AL	215	IRQ_DOVE_UART_1, get_tclk());
edabd38e SB	216	}
	217
	218	/*****************************************************************************
	219	* UART2
	220	****************************************************************************/
edabd38e SB	221	void __init dove_uart2_init(void)
edabd38e SB	222	{
28a2b450 AL	223	orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
28a2b450 AL	224	IRQ_DOVE_UART_2, get_tclk());
edabd38e SB	225	}
	226
	227	/*****************************************************************************
	228	* UART3
	229	****************************************************************************/
edabd38e SB	230	void __init dove_uart3_init(void)
edabd38e SB	231	{
28a2b450 AL	232	orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
28a2b450 AL	233	IRQ_DOVE_UART_3, get_tclk());
edabd38e SB	234	}
	235
	236	/*****************************************************************************
	237	* SPI0
	238	****************************************************************************/
	239	static struct orion_spi_info dove_spi0_data = {
	240	.tclk = 0,
	241	};
	242
	243	static struct resource dove_spi0_resources[] = {
	244	{
	245	.start = DOVE_SPI0_PHYS_BASE,
	246	.end = DOVE_SPI0_PHYS_BASE + SZ_512 - 1,
	247	.flags = IORESOURCE_MEM,
	248	}, {
	249	.start = IRQ_DOVE_SPI0,
	250	.end = IRQ_DOVE_SPI0,
	251	.flags = IORESOURCE_IRQ,
	252	},
	253	};
	254
	255	static struct platform_device dove_spi0 = {
	256	.name = "orion_spi",
	257	.id = 0,
	258	.resource = dove_spi0_resources,
	259	.dev = {
	260	.platform_data = &dove_spi0_data,
	261	},
	262	.num_resources = ARRAY_SIZE(dove_spi0_resources),
	263	};
	264
	265	void __init dove_spi0_init(void)
	266	{
	267	platform_device_register(&dove_spi0);
	268	}
	269
	270	/*****************************************************************************
	271	* SPI1
	272	****************************************************************************/
	273	static struct orion_spi_info dove_spi1_data = {
	274	.tclk = 0,
	275	};
	276
	277	static struct resource dove_spi1_resources[] = {
	278	{
	279	.start = DOVE_SPI1_PHYS_BASE,
	280	.end = DOVE_SPI1_PHYS_BASE + SZ_512 - 1,
	281	.flags = IORESOURCE_MEM,
	282	}, {
	283	.start = IRQ_DOVE_SPI1,
	284	.end = IRQ_DOVE_SPI1,
	285	.flags = IORESOURCE_IRQ,
	286	},
	287	};
	288
	289	static struct platform_device dove_spi1 = {
	290	.name = "orion_spi",
	291	.id = 1,
	292	.resource = dove_spi1_resources,
	293	.dev = {
	294	.platform_data = &dove_spi1_data,
	295	},
	296	.num_resources = ARRAY_SIZE(dove_spi1_resources),
	297	};
298
299	void __init dove_spi1_init(void)
300	{
301	platform_device_register(&dove_spi1);
302	}
303
304	/*****************************************************************************
305	* I2C
306	****************************************************************************/
edabd38e SB	307	void __init dove_i2c_init(void)
edabd38e SB	308	{
aac7ffa3	309	orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10);
edabd38e SB	310	}
	311
	312	/*****************************************************************************
	313	* Time handling
	314	****************************************************************************/
4ee1f6b5 LB	315	void __init dove_init_early(void)
	316	{
	317	orion_time_set_base(TIMER_VIRT_BASE);
	318	}
	319
edabd38e SB	320	static int get_tclk(void)
	321	{
	322	/* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */
	323	return 166666667;
	324	}
	325
	326	static void dove_timer_init(void)
	327	{
4ee1f6b5 LB	328	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
4ee1f6b5 LB	329	IRQ_DOVE_BRIDGE, get_tclk());
edabd38e SB	330	}
	331
	332	struct sys_timer dove_timer = {
	333	.init = dove_timer_init,
	334	};
	335
	336	/*****************************************************************************
	337	* XOR
	338	****************************************************************************/
	339	static struct mv_xor_platform_shared_data dove_xor_shared_data = {
	340	.dram = &dove_mbus_dram_info,
	341	};
	342
	343	/*****************************************************************************
	344	* XOR 0
	345	****************************************************************************/
	346	static u64 dove_xor0_dmamask = DMA_BIT_MASK(32);
	347
	348	static struct resource dove_xor0_shared_resources[] = {
	349	{
	350	.name = "xor 0 low",
	351	.start = DOVE_XOR0_PHYS_BASE,
	352	.end = DOVE_XOR0_PHYS_BASE + 0xff,
	353	.flags = IORESOURCE_MEM,
	354	}, {
	355	.name = "xor 0 high",
	356	.start = DOVE_XOR0_HIGH_PHYS_BASE,
	357	.end = DOVE_XOR0_HIGH_PHYS_BASE + 0xff,
	358	.flags = IORESOURCE_MEM,
	359	},
	360	};
	361
	362	static struct platform_device dove_xor0_shared = {
	363	.name = MV_XOR_SHARED_NAME,
	364	.id = 0,
	365	.dev = {
	366	.platform_data = &dove_xor_shared_data,
	367	},
	368	.num_resources = ARRAY_SIZE(dove_xor0_shared_resources),
	369	.resource = dove_xor0_shared_resources,
	370	};
	371
	372	static struct resource dove_xor00_resources[] = {
	373	[0] = {
	374	.start = IRQ_DOVE_XOR_00,
	375	.end = IRQ_DOVE_XOR_00,
	376	.flags = IORESOURCE_IRQ,
	377	},
	378	};
	379
	380	static struct mv_xor_platform_data dove_xor00_data = {
	381	.shared = &dove_xor0_shared,
	382	.hw_id = 0,
	383	.pool_size = PAGE_SIZE,
	384	};
	385
	386	static struct platform_device dove_xor00_channel = {
	387	.name = MV_XOR_NAME,
	388	.id = 0,
	389	.num_resources = ARRAY_SIZE(dove_xor00_resources),
	390	.resource = dove_xor00_resources,
	391	.dev = {
	392	.dma_mask = &dove_xor0_dmamask,
	393	.coherent_dma_mask = DMA_BIT_MASK(64),
639b9be6	394	.platform_data = &dove_xor00_data,
edabd38e SB	395	},
	396	};
	397
	398	static struct resource dove_xor01_resources[] = {
	399	[0] = {
	400	.start = IRQ_DOVE_XOR_01,
	401	.end = IRQ_DOVE_XOR_01,
	402	.flags = IORESOURCE_IRQ,
	403	},
	404	};
	405
	406	static struct mv_xor_platform_data dove_xor01_data = {
	407	.shared = &dove_xor0_shared,
	408	.hw_id = 1,
	409	.pool_size = PAGE_SIZE,
	410	};
	411
	412	static struct platform_device dove_xor01_channel = {
	413	.name = MV_XOR_NAME,
	414	.id = 1,
	415	.num_resources = ARRAY_SIZE(dove_xor01_resources),
	416	.resource = dove_xor01_resources,
	417	.dev = {
	418	.dma_mask = &dove_xor0_dmamask,
	419	.coherent_dma_mask = DMA_BIT_MASK(64),
639b9be6	420	.platform_data = &dove_xor01_data,
edabd38e SB	421	},
	422	};
	423
	424	void __init dove_xor0_init(void)
	425	{
	426	platform_device_register(&dove_xor0_shared);
	427
	428	/*
	429	* two engines can't do memset simultaneously, this limitation
	430	* satisfied by removing memset support from one of the engines.
	431	*/
	432	dma_cap_set(DMA_MEMCPY, dove_xor00_data.cap_mask);
	433	dma_cap_set(DMA_XOR, dove_xor00_data.cap_mask);
	434	platform_device_register(&dove_xor00_channel);
	435
	436	dma_cap_set(DMA_MEMCPY, dove_xor01_data.cap_mask);
	437	dma_cap_set(DMA_MEMSET, dove_xor01_data.cap_mask);
	438	dma_cap_set(DMA_XOR, dove_xor01_data.cap_mask);
	439	platform_device_register(&dove_xor01_channel);
	440	}
	441
	442	/*****************************************************************************
	443	* XOR 1
	444	****************************************************************************/
	445	static u64 dove_xor1_dmamask = DMA_BIT_MASK(32);
	446
	447	static struct resource dove_xor1_shared_resources[] = {
	448	{
	449	.name = "xor 0 low",
	450	.start = DOVE_XOR1_PHYS_BASE,
	451	.end = DOVE_XOR1_PHYS_BASE + 0xff,
	452	.flags = IORESOURCE_MEM,
	453	}, {
	454	.name = "xor 0 high",
	455	.start = DOVE_XOR1_HIGH_PHYS_BASE,
	456	.end = DOVE_XOR1_HIGH_PHYS_BASE + 0xff,
	457	.flags = IORESOURCE_MEM,
	458	},
	459	};
	460
	461	static struct platform_device dove_xor1_shared = {
	462	.name = MV_XOR_SHARED_NAME,
	463	.id = 1,
	464	.dev = {
	465	.platform_data = &dove_xor_shared_data,
	466	},
	467	.num_resources = ARRAY_SIZE(dove_xor1_shared_resources),
	468	.resource = dove_xor1_shared_resources,
	469	};
	470
	471	static struct resource dove_xor10_resources[] = {
	472	[0] = {
	473	.start = IRQ_DOVE_XOR_10,
	474	.end = IRQ_DOVE_XOR_10,
	475	.flags = IORESOURCE_IRQ,
	476	},
	477	};
	478
	479	static struct mv_xor_platform_data dove_xor10_data = {
	480	.shared = &dove_xor1_shared,
	481	.hw_id = 0,
	482	.pool_size = PAGE_SIZE,
	483	};
	484
485	static struct platform_device dove_xor10_channel = {
486	.name = MV_XOR_NAME,
487	.id = 2,
488	.num_resources = ARRAY_SIZE(dove_xor10_resources),
489	.resource = dove_xor10_resources,
490	.dev = {
491	.dma_mask = &dove_xor1_dmamask,
492	.coherent_dma_mask = DMA_BIT_MASK(64),
639b9be6	493	.platform_data = &dove_xor10_data,
edabd38e SB	494	},
	495	};
	496
	497	static struct resource dove_xor11_resources[] = {
	498	[0] = {
	499	.start = IRQ_DOVE_XOR_11,
	500	.end = IRQ_DOVE_XOR_11,
	501	.flags = IORESOURCE_IRQ,
	502	},
	503	};
	504
	505	static struct mv_xor_platform_data dove_xor11_data = {
	506	.shared = &dove_xor1_shared,
	507	.hw_id = 1,
	508	.pool_size = PAGE_SIZE,
	509	};
	510
	511	static struct platform_device dove_xor11_channel = {
	512	.name = MV_XOR_NAME,
	513	.id = 3,
	514	.num_resources = ARRAY_SIZE(dove_xor11_resources),
	515	.resource = dove_xor11_resources,
	516	.dev = {
	517	.dma_mask = &dove_xor1_dmamask,
	518	.coherent_dma_mask = DMA_BIT_MASK(64),
639b9be6	519	.platform_data = &dove_xor11_data,
edabd38e SB	520	},
	521	};
	522
	523	void __init dove_xor1_init(void)
	524	{
	525	platform_device_register(&dove_xor1_shared);
	526
	527	/*
	528	* two engines can't do memset simultaneously, this limitation
	529	* satisfied by removing memset support from one of the engines.
	530	*/
	531	dma_cap_set(DMA_MEMCPY, dove_xor10_data.cap_mask);
	532	dma_cap_set(DMA_XOR, dove_xor10_data.cap_mask);
	533	platform_device_register(&dove_xor10_channel);
	534
	535	dma_cap_set(DMA_MEMCPY, dove_xor11_data.cap_mask);
	536	dma_cap_set(DMA_MEMSET, dove_xor11_data.cap_mask);
	537	dma_cap_set(DMA_XOR, dove_xor11_data.cap_mask);
	538	platform_device_register(&dove_xor11_channel);
	539	}
	540
16bc90af SB	541	/*****************************************************************************
	542	* SDIO
	543	****************************************************************************/
	544	static u64 sdio_dmamask = DMA_BIT_MASK(32);
	545
	546	static struct resource dove_sdio0_resources[] = {
	547	{
	548	.start = DOVE_SDIO0_PHYS_BASE,
	549	.end = DOVE_SDIO0_PHYS_BASE + 0xff,
	550	.flags = IORESOURCE_MEM,
	551	}, {
	552	.start = IRQ_DOVE_SDIO0,
	553	.end = IRQ_DOVE_SDIO0,
	554	.flags = IORESOURCE_IRQ,
	555	},
	556	};
	557
	558	static struct platform_device dove_sdio0 = {
930e2fe7	559	.name = "sdhci-dove",
16bc90af SB	560	.id = 0,
	561	.dev = {
	562	.dma_mask = &sdio_dmamask,
	563	.coherent_dma_mask = DMA_BIT_MASK(32),
	564	},
	565	.resource = dove_sdio0_resources,
	566	.num_resources = ARRAY_SIZE(dove_sdio0_resources),
	567	};
	568
	569	void __init dove_sdio0_init(void)
	570	{
	571	platform_device_register(&dove_sdio0);
	572	}
	573
	574	static struct resource dove_sdio1_resources[] = {
	575	{
	576	.start = DOVE_SDIO1_PHYS_BASE,
	577	.end = DOVE_SDIO1_PHYS_BASE + 0xff,
	578	.flags = IORESOURCE_MEM,
	579	}, {
	580	.start = IRQ_DOVE_SDIO1,
	581	.end = IRQ_DOVE_SDIO1,
	582	.flags = IORESOURCE_IRQ,
	583	},
	584	};
	585
	586	static struct platform_device dove_sdio1 = {
930e2fe7	587	.name = "sdhci-dove",
16bc90af SB	588	.id = 1,
	589	.dev = {
	590	.dma_mask = &sdio_dmamask,
	591	.coherent_dma_mask = DMA_BIT_MASK(32),
	592	},
	593	.resource = dove_sdio1_resources,
	594	.num_resources = ARRAY_SIZE(dove_sdio1_resources),
	595	};
	596
	597	void __init dove_sdio1_init(void)
	598	{
	599	platform_device_register(&dove_sdio1);
	600	}
	601
edabd38e SB	602	void __init dove_init(void)
	603	{
	604	int tclk;
	605
	606	tclk = get_tclk();
	607
	608	printk(KERN_INFO "Dove 88AP510 SoC, ");
	609	printk(KERN_INFO "TCLK = %dMHz\n", (tclk + 499999) / 1000000);
	610
573a652f LB	611	#ifdef CONFIG_CACHE_TAUROS2
	612	tauros2_init();
	613	#endif
edabd38e SB	614	dove_setup_cpu_mbus();
edabd38e SB	615
edabd38e SB	616	dove_spi0_data.tclk = tclk;
	617	dove_spi1_data.tclk = tclk;
	618
	619	/* internal devices that every board has */
	620	dove_rtc_init();
	621	dove_xor0_init();
	622	dove_xor1_init();
	623	}