[deliverable/linux.git] / arch / arm / mach-dove / common.c

/*
 * arch/arm/mach-dove/common.c
 *
 * Core functions for Marvell Dove 88AP510 System On Chip
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/clk-provider.h>
#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_data/dma-mv_xor.h>
#include <linux/platform_data/usb-ehci-orion.h>
#include <linux/platform_device.h>
#include <linux/soc/dove/pmu.h>
#include <asm/hardware/cache-tauros2.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <mach/bridge-regs.h>
#include <mach/pm.h>
#include <plat/common.h>
#include <plat/irq.h>
#include <plat/time.h>
#include "common.h"

/* These can go away once Dove uses the mvebu-mbus DT binding */
#define DOVE_MBUS_PCIE0_MEM_TARGET    0x4
#define DOVE_MBUS_PCIE0_MEM_ATTR      0xe8
#define DOVE_MBUS_PCIE0_IO_TARGET     0x4
#define DOVE_MBUS_PCIE0_IO_ATTR       0xe0
#define DOVE_MBUS_PCIE1_MEM_TARGET    0x8
#define DOVE_MBUS_PCIE1_MEM_ATTR      0xe8
#define DOVE_MBUS_PCIE1_IO_TARGET     0x8
#define DOVE_MBUS_PCIE1_IO_ATTR       0xe0
#define DOVE_MBUS_CESA_TARGET         0x3
#define DOVE_MBUS_CESA_ATTR           0x1
#define DOVE_MBUS_BOOTROM_TARGET      0x1
#define DOVE_MBUS_BOOTROM_ATTR        0xfd
#define DOVE_MBUS_SCRATCHPAD_TARGET   0xd
#define DOVE_MBUS_SCRATCHPAD_ATTR     0x0

/*****************************************************************************
 * I/O Address Mapping
 ****************************************************************************/
static struct map_desc dove_io_desc[] __initdata = {
	{
		.virtual	= (unsigned long) DOVE_SB_REGS_VIRT_BASE,
		.pfn		= __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
		.length		= DOVE_SB_REGS_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long) DOVE_NB_REGS_VIRT_BASE,
		.pfn		= __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
		.length		= DOVE_NB_REGS_SIZE,
		.type		= MT_DEVICE,
	},
};

void __init dove_map_io(void)
{
	iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
}

/*****************************************************************************
 * CLK tree
 ****************************************************************************/
static int dove_tclk;

static DEFINE_SPINLOCK(gating_lock);
static struct clk *tclk;

static struct clk __init *dove_register_gate(const char *name,
					     const char *parent, u8 bit_idx)
{
	return clk_register_gate(NULL, name, parent, 0,
				 (void __iomem *)CLOCK_GATING_CONTROL,
				 bit_idx, 0, &gating_lock);
}

static void __init dove_clk_init(void)
{
	struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1;
	struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma;
	struct clk *xor0, *xor1, *ge, *gephy;

	tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
				       dove_tclk);

	usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0);
	usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1);
	sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA);
	pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0);
	pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1);
	sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0);
	sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1);
	nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND);
	camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA);
	i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0);
	i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1);
	crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO);
	ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97);
	pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA);
	xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0);
	xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1);
	gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY);
	ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE);

	orion_clkdev_add(NULL, "orion_spi.0", tclk);
	orion_clkdev_add(NULL, "orion_spi.1", tclk);
	orion_clkdev_add(NULL, "orion_wdt", tclk);
	orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk);

	orion_clkdev_add(NULL, "orion-ehci.0", usb0);
	orion_clkdev_add(NULL, "orion-ehci.1", usb1);
	orion_clkdev_add(NULL, "mv643xx_eth_port.0", ge);
	orion_clkdev_add(NULL, "sata_mv.0", sata);
	orion_clkdev_add("0", "pcie", pex0);
	orion_clkdev_add("1", "pcie", pex1);
	orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
	orion_clkdev_add(NULL, "sdhci-dove.1", sdio1);
	orion_clkdev_add(NULL, "orion_nand", nand);
	orion_clkdev_add(NULL, "cafe1000-ccic.0", camera);
	orion_clkdev_add(NULL, "mvebu-audio.0", i2s0);
	orion_clkdev_add(NULL, "mvebu-audio.1", i2s1);
	orion_clkdev_add(NULL, "mv_crypto", crypto);
	orion_clkdev_add(NULL, "dove-ac97", ac97);
	orion_clkdev_add(NULL, "dove-pdma", pdma);
	orion_clkdev_add(NULL, MV_XOR_NAME ".0", xor0);
	orion_clkdev_add(NULL, MV_XOR_NAME ".1", xor1);
}

/*****************************************************************************
 * EHCI0
 ****************************************************************************/
void __init dove_ehci0_init(void)
{
	orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA);
}

/*****************************************************************************
 * EHCI1
 ****************************************************************************/
void __init dove_ehci1_init(void)
{
	orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
}

/*****************************************************************************
 * GE00
 ****************************************************************************/
void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
{
	orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE,
			IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR,
			1600);
}

/*****************************************************************************
 * SoC RTC
 ****************************************************************************/
static void __init dove_rtc_init(void)
{
	orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
}

/*****************************************************************************
 * SATA
 ****************************************************************************/
void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
{
	orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);

}

/*****************************************************************************
 * UART0
 ****************************************************************************/
void __init dove_uart0_init(void)
{
	orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
			 IRQ_DOVE_UART_0, tclk);
}

/*****************************************************************************
 * UART1
 ****************************************************************************/
void __init dove_uart1_init(void)
{
	orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
			 IRQ_DOVE_UART_1, tclk);
}

/*****************************************************************************
 * UART2
 ****************************************************************************/
void __init dove_uart2_init(void)
{
	orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
			 IRQ_DOVE_UART_2, tclk);
}

/*****************************************************************************
 * UART3
 ****************************************************************************/
void __init dove_uart3_init(void)
{
	orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
			 IRQ_DOVE_UART_3, tclk);
}

/*****************************************************************************
 * SPI
 ****************************************************************************/
void __init dove_spi0_init(void)
{
	orion_spi_init(DOVE_SPI0_PHYS_BASE);
}

void __init dove_spi1_init(void)
{
	orion_spi_1_init(DOVE_SPI1_PHYS_BASE);
}

/*****************************************************************************
 * I2C
 ****************************************************************************/
void __init dove_i2c_init(void)
{
	orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10);
}

/*****************************************************************************
 * Time handling
 ****************************************************************************/
void __init dove_init_early(void)
{
	orion_time_set_base(TIMER_VIRT_BASE);
	mvebu_mbus_init("marvell,dove-mbus",
			BRIDGE_WINS_BASE, BRIDGE_WINS_SZ,
			DOVE_MC_WINS_BASE, DOVE_MC_WINS_SZ);
}

static int __init dove_find_tclk(void)
{
	return 166666667;
}

void __init dove_timer_init(void)
{
	dove_tclk = dove_find_tclk();
	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
			IRQ_DOVE_BRIDGE, dove_tclk);
}

/*****************************************************************************
 * XOR 0
 ****************************************************************************/
static void __init dove_xor0_init(void)
{
	orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
			IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
}

/*****************************************************************************
 * XOR 1
 ****************************************************************************/
static void __init dove_xor1_init(void)
{
	orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE,
			IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11);
}

/*****************************************************************************
 * SDIO
 ****************************************************************************/
static u64 sdio_dmamask = DMA_BIT_MASK(32);

static struct resource dove_sdio0_resources[] = {
	{
		.start	= DOVE_SDIO0_PHYS_BASE,
		.end	= DOVE_SDIO0_PHYS_BASE + 0xff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_DOVE_SDIO0,
		.end	= IRQ_DOVE_SDIO0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dove_sdio0 = {
	.name		= "sdhci-dove",
	.id		= 0,
	.dev		= {
		.dma_mask		= &sdio_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
	.resource	= dove_sdio0_resources,
	.num_resources	= ARRAY_SIZE(dove_sdio0_resources),
};

void __init dove_sdio0_init(void)
{
	platform_device_register(&dove_sdio0);
}

static struct resource dove_sdio1_resources[] = {
	{
		.start	= DOVE_SDIO1_PHYS_BASE,
		.end	= DOVE_SDIO1_PHYS_BASE + 0xff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_DOVE_SDIO1,
		.end	= IRQ_DOVE_SDIO1,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dove_sdio1 = {
	.name		= "sdhci-dove",
	.id		= 1,
	.dev		= {
		.dma_mask		= &sdio_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
	.resource	= dove_sdio1_resources,
	.num_resources	= ARRAY_SIZE(dove_sdio1_resources),
};

void __init dove_sdio1_init(void)
{
	platform_device_register(&dove_sdio1);
}

void __init dove_setup_cpu_wins(void)
{
	/*
	 * The PCIe windows will no longer be statically allocated
	 * here once Dove is migrated to the pci-mvebu driver. The
	 * non-PCIe windows will no longer be created here once Dove
	 * fully moves to DT.
	 */
	mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE0_IO_TARGET,
					  DOVE_MBUS_PCIE0_IO_ATTR,
					  DOVE_PCIE0_IO_PHYS_BASE,
					  DOVE_PCIE0_IO_SIZE,
					  DOVE_PCIE0_IO_BUS_BASE);
	mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE1_IO_TARGET,
					  DOVE_MBUS_PCIE1_IO_ATTR,
					  DOVE_PCIE1_IO_PHYS_BASE,
					  DOVE_PCIE1_IO_SIZE,
					  DOVE_PCIE1_IO_BUS_BASE);
	mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE0_MEM_TARGET,
				    DOVE_MBUS_PCIE0_MEM_ATTR,
				    DOVE_PCIE0_MEM_PHYS_BASE,
				    DOVE_PCIE0_MEM_SIZE);
	mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE1_MEM_TARGET,
				    DOVE_MBUS_PCIE1_MEM_ATTR,
				    DOVE_PCIE1_MEM_PHYS_BASE,
				    DOVE_PCIE1_MEM_SIZE);
	mvebu_mbus_add_window_by_id(DOVE_MBUS_CESA_TARGET,
				    DOVE_MBUS_CESA_ATTR,
				    DOVE_CESA_PHYS_BASE,
				    DOVE_CESA_SIZE);
	mvebu_mbus_add_window_by_id(DOVE_MBUS_BOOTROM_TARGET,
				    DOVE_MBUS_BOOTROM_ATTR,
				    DOVE_BOOTROM_PHYS_BASE,
				    DOVE_BOOTROM_SIZE);
	mvebu_mbus_add_window_by_id(DOVE_MBUS_SCRATCHPAD_TARGET,
				    DOVE_MBUS_SCRATCHPAD_ATTR,
				    DOVE_SCRATCHPAD_PHYS_BASE,
				    DOVE_SCRATCHPAD_SIZE);
}

static struct resource orion_wdt_resource[] = {
		DEFINE_RES_MEM(TIMER_PHYS_BASE, 0x04),
		DEFINE_RES_MEM(RSTOUTn_MASK_PHYS, 0x04),
};

static struct platform_device orion_wdt_device = {
	.name		= "orion_wdt",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(orion_wdt_resource),
	.resource	= orion_wdt_resource,
};

static void __init __maybe_unused orion_wdt_init(void)
{
	platform_device_register(&orion_wdt_device);
}

static const struct dove_pmu_domain_initdata pmu_domains[] __initconst = {
	{
		.pwr_mask = PMU_PWR_VPU_PWR_DWN_MASK,
		.rst_mask = PMU_SW_RST_VIDEO_MASK,
		.iso_mask = PMU_ISO_VIDEO_MASK,
		.name = "vpu-domain",
	}, {
		.pwr_mask = PMU_PWR_GPU_PWR_DWN_MASK,
		.rst_mask = PMU_SW_RST_GPU_MASK,
		.iso_mask = PMU_ISO_GPU_MASK,
		.name = "gpu-domain",
	}, {
		/* sentinel */
	},
};

static const struct dove_pmu_initdata pmu_data __initconst = {
	.pmc_base = DOVE_PMU_VIRT_BASE,
	.pmu_base = DOVE_PMU_VIRT_BASE + 0x8000,
	.irq = IRQ_DOVE_PMU,
	.irq_domain_start = IRQ_DOVE_PMU_START,
	.domains = pmu_domains,
};

void __init dove_init(void)
{
	pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
		(dove_tclk + 499999) / 1000000);

#ifdef CONFIG_CACHE_TAUROS2
	tauros2_init(0);
#endif
	dove_setup_cpu_wins();

	/* Setup root of clk tree */
	dove_clk_init();

	/* internal devices that every board has */
	dove_init_pmu_legacy(&pmu_data);
	dove_rtc_init();
	dove_xor0_init();
	dove_xor1_init();
}

void dove_restart(enum reboot_mode mode, const char *cmd)
{
	/*
	 * Enable soft reset to assert RSTOUTn.
	 */
	writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);

	/*
	 * Assert soft reset.
	 */
	writel(SOFT_RESET, SYSTEM_SOFT_RESET);

	while (1)
		;
}
Commit	Line	Data
edabd38e SB	1	/*
	2	* arch/arm/mach-dove/common.c
	3	*
	4	* Core functions for Marvell Dove 88AP510 System On Chip
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10
2f129bf4	11	#include <linux/clk-provider.h>
b3af7a1f SH	12	#include <linux/dma-mapping.h>
b3af7a1f SH	13	#include <linux/init.h>
81d2ef7c SH	14	#include <linux/of.h>
81d2ef7c SH	15	#include <linux/of_platform.h>
b3af7a1f SH	16	#include <linux/platform_data/dma-mv_xor.h>
	17	#include <linux/platform_data/usb-ehci-orion.h>
	18	#include <linux/platform_device.h>
c5d431e8	19	#include <linux/soc/dove/pmu.h>
573a652f	20	#include <asm/hardware/cache-tauros2.h>
b3af7a1f	21	#include <asm/mach/arch.h>
edabd38e SB	22	#include <asm/mach/map.h>
edabd38e SB	23	#include <asm/mach/time.h>
edabd38e	24	#include <mach/bridge-regs.h>
b3af7a1f	25	#include <mach/pm.h>
28a2b450	26	#include <plat/common.h>
b3af7a1f SH	27	#include <plat/irq.h>
b3af7a1f SH	28	#include <plat/time.h>
edabd38e SB	29	#include "common.h"
edabd38e SB	30
89a7fbfb TP	31	/* These can go away once Dove uses the mvebu-mbus DT binding */
	32	#define DOVE_MBUS_PCIE0_MEM_TARGET 0x4
	33	#define DOVE_MBUS_PCIE0_MEM_ATTR 0xe8
	34	#define DOVE_MBUS_PCIE0_IO_TARGET 0x4
	35	#define DOVE_MBUS_PCIE0_IO_ATTR 0xe0
	36	#define DOVE_MBUS_PCIE1_MEM_TARGET 0x8
	37	#define DOVE_MBUS_PCIE1_MEM_ATTR 0xe8
	38	#define DOVE_MBUS_PCIE1_IO_TARGET 0x8
	39	#define DOVE_MBUS_PCIE1_IO_ATTR 0xe0
	40	#define DOVE_MBUS_CESA_TARGET 0x3
	41	#define DOVE_MBUS_CESA_ATTR 0x1
	42	#define DOVE_MBUS_BOOTROM_TARGET 0x1
	43	#define DOVE_MBUS_BOOTROM_ATTR 0xfd
	44	#define DOVE_MBUS_SCRATCHPAD_TARGET 0xd
	45	#define DOVE_MBUS_SCRATCHPAD_ATTR 0x0
	46
edabd38e SB	47	/*****************************************************************************
	48	* I/O Address Mapping
	49	****************************************************************************/
	50	static struct map_desc dove_io_desc[] __initdata = {
	51	{
c3c5a281	52	.virtual = (unsigned long) DOVE_SB_REGS_VIRT_BASE,
edabd38e SB	53	.pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
	54	.length = DOVE_SB_REGS_SIZE,
	55	.type = MT_DEVICE,
	56	}, {
c3c5a281	57	.virtual = (unsigned long) DOVE_NB_REGS_VIRT_BASE,
edabd38e SB	58	.pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
	59	.length = DOVE_NB_REGS_SIZE,
	60	.type = MT_DEVICE,
edabd38e SB	61	},
	62	};
	63
	64	void __init dove_map_io(void)
	65	{
	66	iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
	67	}
	68
2f129bf4 AL	69	/*****************************************************************************
	70	* CLK tree
	71	****************************************************************************/
5817d10b	72	static int dove_tclk;
52167471 SH	73
52167471 SH	74	static DEFINE_SPINLOCK(gating_lock);
2f129bf4 AL	75	static struct clk *tclk;
2f129bf4 AL	76
52167471 SH	77	static struct clk __init dove_register_gate(const char name,
52167471 SH	78	const char *parent, u8 bit_idx)
2f129bf4	79	{
52167471 SH	80	return clk_register_gate(NULL, name, parent, 0,
	81	(void __iomem *)CLOCK_GATING_CONTROL,
	82	bit_idx, 0, &gating_lock);
	83	}
	84
5817d10b	85	static void __init dove_clk_init(void)
2f129bf4	86	{
52167471 SH	87	struct clk usb0, usb1, sata, pex0, pex1, sdio0, *sdio1;
	88	struct clk nand, camera, i2s0, i2s1, crypto, ac97, *pdma;
	89	struct clk xor0, xor1, ge, gephy;
4574b886	90
2f129bf4	91	tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
5817d10b	92	dove_tclk);
4574b886	93
52167471 SH	94	usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0);
	95	usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1);
	96	sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA);
	97	pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0);
	98	pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1);
	99	sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0);
	100	sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1);
	101	nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND);
	102	camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA);
	103	i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0);
	104	i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1);
	105	crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO);
	106	ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97);
	107	pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA);
	108	xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0);
	109	xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1);
	110	gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY);
	111	ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE);
	112
	113	orion_clkdev_add(NULL, "orion_spi.0", tclk);
	114	orion_clkdev_add(NULL, "orion_spi.1", tclk);
	115	orion_clkdev_add(NULL, "orion_wdt", tclk);
	116	orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk);
	117
	118	orion_clkdev_add(NULL, "orion-ehci.0", usb0);
	119	orion_clkdev_add(NULL, "orion-ehci.1", usb1);
3fbcd3d0 SH	120	orion_clkdev_add(NULL, "mv643xx_eth_port.0", ge);
3fbcd3d0 SH	121	orion_clkdev_add(NULL, "sata_mv.0", sata);
52167471 SH	122	orion_clkdev_add("0", "pcie", pex0);
	123	orion_clkdev_add("1", "pcie", pex1);
	124	orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
	125	orion_clkdev_add(NULL, "sdhci-dove.1", sdio1);
	126	orion_clkdev_add(NULL, "orion_nand", nand);
	127	orion_clkdev_add(NULL, "cafe1000-ccic.0", camera);
64ddf1f8 RK	128	orion_clkdev_add(NULL, "mvebu-audio.0", i2s0);
64ddf1f8 RK	129	orion_clkdev_add(NULL, "mvebu-audio.1", i2s1);
52167471 SH	130	orion_clkdev_add(NULL, "mv_crypto", crypto);
	131	orion_clkdev_add(NULL, "dove-ac97", ac97);
	132	orion_clkdev_add(NULL, "dove-pdma", pdma);
0dddee7a TP	133	orion_clkdev_add(NULL, MV_XOR_NAME ".0", xor0);
0dddee7a TP	134	orion_clkdev_add(NULL, MV_XOR_NAME ".1", xor1);
2f129bf4 AL	135	}
2f129bf4 AL	136
edabd38e SB	137	/*****************************************************************************
	138	* EHCI0
	139	****************************************************************************/
edabd38e SB	140	void __init dove_ehci0_init(void)
edabd38e SB	141	{
72053353	142	orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA);
edabd38e SB	143	}
	144
	145	/*****************************************************************************
	146	* EHCI1
	147	****************************************************************************/
edabd38e SB	148	void __init dove_ehci1_init(void)
edabd38e SB	149	{
db33f4de	150	orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
edabd38e SB	151	}
	152
	153	/*****************************************************************************
	154	* GE00
	155	****************************************************************************/
edabd38e SB	156	void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
edabd38e SB	157	{
30e0f580	158	orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE,
58569aee APR	159	IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR,
58569aee APR	160	1600);
edabd38e SB	161	}
	162
	163	/*****************************************************************************
	164	* SoC RTC
	165	****************************************************************************/
887c206a	166	static void __init dove_rtc_init(void)
edabd38e	167	{
f6eaccb3	168	orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
edabd38e SB	169	}
	170
	171	/*****************************************************************************
	172	* SATA
	173	****************************************************************************/
edabd38e SB	174	void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
edabd38e SB	175	{
db33f4de	176	orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);
9e613f8a	177
edabd38e SB	178	}
	179
	180	/*****************************************************************************
	181	* UART0
	182	****************************************************************************/
edabd38e SB	183	void __init dove_uart0_init(void)
edabd38e SB	184	{
28a2b450	185	orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
74c33576	186	IRQ_DOVE_UART_0, tclk);
edabd38e SB	187	}
	188
	189	/*****************************************************************************
	190	* UART1
	191	****************************************************************************/
edabd38e SB	192	void __init dove_uart1_init(void)
edabd38e SB	193	{
28a2b450	194	orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
74c33576	195	IRQ_DOVE_UART_1, tclk);
edabd38e SB	196	}
	197
	198	/*****************************************************************************
	199	* UART2
	200	****************************************************************************/
edabd38e SB	201	void __init dove_uart2_init(void)
edabd38e SB	202	{
28a2b450	203	orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
74c33576	204	IRQ_DOVE_UART_2, tclk);
edabd38e SB	205	}
	206
	207	/*****************************************************************************
	208	* UART3
	209	****************************************************************************/
edabd38e SB	210	void __init dove_uart3_init(void)
edabd38e SB	211	{
28a2b450	212	orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
74c33576	213	IRQ_DOVE_UART_3, tclk);
edabd38e SB	214	}
	215
	216	/*****************************************************************************
980f9f60	217	* SPI
edabd38e	218	****************************************************************************/
edabd38e SB	219	void __init dove_spi0_init(void)
edabd38e SB	220	{
4574b886	221	orion_spi_init(DOVE_SPI0_PHYS_BASE);
edabd38e SB	222	}
edabd38e SB	223
edabd38e SB	224	void __init dove_spi1_init(void)
edabd38e SB	225	{
4574b886	226	orion_spi_1_init(DOVE_SPI1_PHYS_BASE);
edabd38e SB	227	}
	228
	229	/*****************************************************************************
	230	* I2C
	231	****************************************************************************/
edabd38e SB	232	void __init dove_i2c_init(void)
edabd38e SB	233	{
aac7ffa3	234	orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10);
edabd38e SB	235	}
	236
	237	/*****************************************************************************
	238	* Time handling
	239	****************************************************************************/
4ee1f6b5 LB	240	void __init dove_init_early(void)
	241	{
	242	orion_time_set_base(TIMER_VIRT_BASE);
7d554902 TP	243	mvebu_mbus_init("marvell,dove-mbus",
	244	BRIDGE_WINS_BASE, BRIDGE_WINS_SZ,
	245	DOVE_MC_WINS_BASE, DOVE_MC_WINS_SZ);
4ee1f6b5 LB	246	}
4ee1f6b5 LB	247
5817d10b	248	static int __init dove_find_tclk(void)
edabd38e	249	{
edabd38e SB	250	return 166666667;
	251	}
	252
6bb27d73	253	void __init dove_timer_init(void)
edabd38e	254	{
5817d10b	255	dove_tclk = dove_find_tclk();
4ee1f6b5	256	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
5817d10b	257	IRQ_DOVE_BRIDGE, dove_tclk);
edabd38e SB	258	}
edabd38e SB	259
edabd38e SB	260	/*****************************************************************************
	261	* XOR 0
	262	****************************************************************************/
887c206a	263	static void __init dove_xor0_init(void)
edabd38e	264	{
db33f4de	265	orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
ee962723	266	IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
edabd38e SB	267	}
	268
	269	/*****************************************************************************
	270	* XOR 1
	271	****************************************************************************/
887c206a	272	static void __init dove_xor1_init(void)
edabd38e	273	{
ee962723 AL	274	orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE,
ee962723 AL	275	IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11);
edabd38e SB	276	}
edabd38e SB	277
16bc90af SB	278	/*****************************************************************************
	279	* SDIO
	280	****************************************************************************/
	281	static u64 sdio_dmamask = DMA_BIT_MASK(32);
	282
	283	static struct resource dove_sdio0_resources[] = {
	284	{
	285	.start = DOVE_SDIO0_PHYS_BASE,
	286	.end = DOVE_SDIO0_PHYS_BASE + 0xff,
	287	.flags = IORESOURCE_MEM,
	288	}, {
	289	.start = IRQ_DOVE_SDIO0,
	290	.end = IRQ_DOVE_SDIO0,
	291	.flags = IORESOURCE_IRQ,
	292	},
	293	};
	294
	295	static struct platform_device dove_sdio0 = {
930e2fe7	296	.name = "sdhci-dove",
16bc90af SB	297	.id = 0,
	298	.dev = {
	299	.dma_mask = &sdio_dmamask,
	300	.coherent_dma_mask = DMA_BIT_MASK(32),
	301	},
	302	.resource = dove_sdio0_resources,
	303	.num_resources = ARRAY_SIZE(dove_sdio0_resources),
	304	};
	305
	306	void __init dove_sdio0_init(void)
	307	{
	308	platform_device_register(&dove_sdio0);
	309	}
	310
	311	static struct resource dove_sdio1_resources[] = {
	312	{
	313	.start = DOVE_SDIO1_PHYS_BASE,
	314	.end = DOVE_SDIO1_PHYS_BASE + 0xff,
	315	.flags = IORESOURCE_MEM,
	316	}, {
	317	.start = IRQ_DOVE_SDIO1,
	318	.end = IRQ_DOVE_SDIO1,
	319	.flags = IORESOURCE_IRQ,
	320	},
	321	};
	322
	323	static struct platform_device dove_sdio1 = {
930e2fe7	324	.name = "sdhci-dove",
16bc90af SB	325	.id = 1,
	326	.dev = {
	327	.dma_mask = &sdio_dmamask,
	328	.coherent_dma_mask = DMA_BIT_MASK(32),
	329	},
	330	.resource = dove_sdio1_resources,
	331	.num_resources = ARRAY_SIZE(dove_sdio1_resources),
	332	};
	333
	334	void __init dove_sdio1_init(void)
	335	{
	336	platform_device_register(&dove_sdio1);
	337	}
	338
7d554902 TP	339	void __init dove_setup_cpu_wins(void)
	340	{
	341	/*
	342	* The PCIe windows will no longer be statically allocated
89a7fbfb TP	343	* here once Dove is migrated to the pci-mvebu driver. The
	344	* non-PCIe windows will no longer be created here once Dove
	345	* fully moves to DT.
7d554902	346	*/
89a7fbfb TP	347	mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE0_IO_TARGET,
89a7fbfb TP	348	DOVE_MBUS_PCIE0_IO_ATTR,
7d554902 TP	349	DOVE_PCIE0_IO_PHYS_BASE,
7d554902 TP	350	DOVE_PCIE0_IO_SIZE,
89a7fbfb TP	351	DOVE_PCIE0_IO_BUS_BASE);
	352	mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE1_IO_TARGET,
	353	DOVE_MBUS_PCIE1_IO_ATTR,
7d554902 TP	354	DOVE_PCIE1_IO_PHYS_BASE,
7d554902 TP	355	DOVE_PCIE1_IO_SIZE,
89a7fbfb TP	356	DOVE_PCIE1_IO_BUS_BASE);
	357	mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE0_MEM_TARGET,
	358	DOVE_MBUS_PCIE0_MEM_ATTR,
	359	DOVE_PCIE0_MEM_PHYS_BASE,
	360	DOVE_PCIE0_MEM_SIZE);
	361	mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE1_MEM_TARGET,
	362	DOVE_MBUS_PCIE1_MEM_ATTR,
	363	DOVE_PCIE1_MEM_PHYS_BASE,
	364	DOVE_PCIE1_MEM_SIZE);
	365	mvebu_mbus_add_window_by_id(DOVE_MBUS_CESA_TARGET,
	366	DOVE_MBUS_CESA_ATTR,
	367	DOVE_CESA_PHYS_BASE,
	368	DOVE_CESA_SIZE);
	369	mvebu_mbus_add_window_by_id(DOVE_MBUS_BOOTROM_TARGET,
	370	DOVE_MBUS_BOOTROM_ATTR,
	371	DOVE_BOOTROM_PHYS_BASE,
	372	DOVE_BOOTROM_SIZE);
	373	mvebu_mbus_add_window_by_id(DOVE_MBUS_SCRATCHPAD_TARGET,
	374	DOVE_MBUS_SCRATCHPAD_ATTR,
	375	DOVE_SCRATCHPAD_PHYS_BASE,
	376	DOVE_SCRATCHPAD_SIZE);
7d554902 TP	377	}
7d554902 TP	378
06f3008a AB	379	static struct resource orion_wdt_resource[] = {
	380	DEFINE_RES_MEM(TIMER_PHYS_BASE, 0x04),
	381	DEFINE_RES_MEM(RSTOUTn_MASK_PHYS, 0x04),
	382	};
	383
	384	static struct platform_device orion_wdt_device = {
	385	.name = "orion_wdt",
	386	.id = -1,
	387	.num_resources = ARRAY_SIZE(orion_wdt_resource),
	388	.resource = orion_wdt_resource,
	389	};
	390
	391	static void __init __maybe_unused orion_wdt_init(void)
	392	{
	393	platform_device_register(&orion_wdt_device);
	394	}
	395
c5d431e8 RK	396	static const struct dove_pmu_domain_initdata pmu_domains[] __initconst = {
	397	{
	398	.pwr_mask = PMU_PWR_VPU_PWR_DWN_MASK,
	399	.rst_mask = PMU_SW_RST_VIDEO_MASK,
	400	.iso_mask = PMU_ISO_VIDEO_MASK,
	401	.name = "vpu-domain",
	402	}, {
	403	.pwr_mask = PMU_PWR_GPU_PWR_DWN_MASK,
	404	.rst_mask = PMU_SW_RST_GPU_MASK,
	405	.iso_mask = PMU_ISO_GPU_MASK,
	406	.name = "gpu-domain",
	407	}, {
	408	/* sentinel */
	409	},
	410	};
	411
	412	static const struct dove_pmu_initdata pmu_data __initconst = {
	413	.pmc_base = DOVE_PMU_VIRT_BASE,
	414	.pmu_base = DOVE_PMU_VIRT_BASE + 0x8000,
	415	.irq = IRQ_DOVE_PMU,
	416	.irq_domain_start = IRQ_DOVE_PMU_START,
	417	.domains = pmu_domains,
	418	};
	419
edabd38e SB	420	void __init dove_init(void)
edabd38e SB	421	{
5817d10b SH	422	pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
5817d10b SH	423	(dove_tclk + 499999) / 1000000);
edabd38e	424
573a652f	425	#ifdef CONFIG_CACHE_TAUROS2
5cc58157	426	tauros2_init(0);
573a652f	427	#endif
7d554902	428	dove_setup_cpu_wins();
edabd38e	429
2f129bf4	430	/* Setup root of clk tree */
5817d10b	431	dove_clk_init();
2f129bf4	432
edabd38e	433	/* internal devices that every board has */
c5d431e8	434	dove_init_pmu_legacy(&pmu_data);
edabd38e SB	435	dove_rtc_init();
	436	dove_xor0_init();
	437	dove_xor1_init();
	438	}
6ca6ff97	439
7b6d864b	440	void dove_restart(enum reboot_mode mode, const char *cmd)
6ca6ff97 RK	441	{
	442	/*
	443	* Enable soft reset to assert RSTOUTn.
	444	*/
	445	writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
	446
	447	/*
	448	* Assert soft reset.
	449	*/
	450	writel(SOFT_RESET, SYSTEM_SOFT_RESET);
	451
	452	while (1)
	453	;
	454	}